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Line 40... |
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module tx_dequeue(/*AUTOARG*/
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module tx_dequeue(/*AUTOARG*/
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// Outputs
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// Outputs
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txdfifo_ren, txhfifo_ren, txhfifo_wdata, txhfifo_wstatus,
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txdfifo_ren, txhfifo_ren, txhfifo_wdata, txhfifo_wstatus,
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txhfifo_wen, xgmii_txd, xgmii_txc, status_txdfifo_udflow_tog,
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txhfifo_wen, xgmii_txd, xgmii_txc, status_txdfifo_udflow_tog,
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status_good_frame_tx_tog, status_good_frame_tx_size,
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// Inputs
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// Inputs
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clk_xgmii_tx, reset_xgmii_tx_n, ctrl_tx_enable_ctx,
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clk_xgmii_tx, reset_xgmii_tx_n, ctrl_tx_enable_ctx,
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status_local_fault_ctx, status_remote_fault_ctx, txdfifo_rdata,
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status_local_fault_ctx, status_remote_fault_ctx, txdfifo_rdata,
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txdfifo_rstatus, txdfifo_rempty, txdfifo_ralmost_empty,
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txdfifo_rstatus, txdfifo_rempty, txdfifo_ralmost_empty,
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txhfifo_rdata, txhfifo_rstatus, txhfifo_rempty,
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txhfifo_rdata, txhfifo_rstatus, txhfifo_rempty,
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| Line 85... |
Line 86... |
output [63:0] xgmii_txd;
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output [63:0] xgmii_txd;
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output [7:0] xgmii_txc;
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output [7:0] xgmii_txc;
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output status_txdfifo_udflow_tog;
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output status_txdfifo_udflow_tog;
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output status_good_frame_tx_tog;
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output [13:0] status_good_frame_tx_size;
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/*AUTOREG*/
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/*AUTOREG*/
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// Beginning of automatic regs (for this module's undeclared outputs)
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// Beginning of automatic regs (for this module's undeclared outputs)
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reg [13:0] status_good_frame_tx_size;
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reg status_good_frame_tx_tog;
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reg status_txdfifo_udflow_tog;
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reg status_txdfifo_udflow_tog;
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reg txdfifo_ren;
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reg txdfifo_ren;
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reg txhfifo_ren;
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reg txhfifo_ren;
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reg [63:0] txhfifo_wdata;
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reg [63:0] txhfifo_wdata;
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reg txhfifo_wen;
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reg txhfifo_wen;
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Line 164... |
reg [7:0] next_txhfifo_wstatus;
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reg [7:0] next_txhfifo_wstatus;
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reg next_txhfifo_wen;
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reg next_txhfifo_wen;
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reg txdfifo_ren_d1;
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reg txdfifo_ren_d1;
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reg frame_end;
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parameter [2:0]
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parameter [2:0]
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SM_IDLE = 3'd0,
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SM_IDLE = 3'd0,
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SM_PREAMBLE = 3'd1,
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SM_PREAMBLE = 3'd1,
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SM_TX = 3'd2,
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SM_TX = 3'd2,
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SM_EOP = 3'd3,
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SM_EOP = 3'd3,
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Line 250... |
xgxs_txd <= {8{`IDLE}};
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xgxs_txd <= {8{`IDLE}};
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xgxs_txc <= 8'hff;
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xgxs_txc <= 8'hff;
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status_txdfifo_udflow_tog <= 1'b0;
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status_txdfifo_udflow_tog <= 1'b0;
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status_good_frame_tx_tog <= 1'b0;
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status_good_frame_tx_size <= 14'b0;
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end
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end
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else begin
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else begin
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curr_state_enc <= next_state_enc;
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curr_state_enc <= next_state_enc;
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Line 298... |
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if (txdfifo_ren && txdfifo_rempty) begin
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if (txdfifo_ren && txdfifo_rempty) begin
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status_txdfifo_udflow_tog <= ~status_txdfifo_udflow_tog;
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status_txdfifo_udflow_tog <= ~status_txdfifo_udflow_tog;
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end
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end
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//---
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// Frame count and size
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if (frame_end) begin
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status_good_frame_tx_tog <= ~status_good_frame_tx_tog;
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status_good_frame_tx_size <= byte_cnt;
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end
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end
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end
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end
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end
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always @(/*AS*/crc32_tx or ctrl_tx_enable_ctx or curr_state_enc or eop
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always @(/*AS*/crc32_tx or ctrl_tx_enable_ctx or curr_state_enc or eop
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Line 760... |
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// On EOP, decide if padding is required for this packet.
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// On EOP, decide if padding is required for this packet.
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if (txdfifo_rstatus[`TXSTATUS_EOP]) begin
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if (txdfifo_rstatus[`TXSTATUS_EOP]) begin
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if (byte_cnt < 14'd56) begin
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if (byte_cnt < 14'd60) begin
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next_txhfifo_wstatus = `TXSTATUS_NONE;
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next_txhfifo_wstatus = `TXSTATUS_NONE;
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txdfifo_ren = 1'b0;
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txdfifo_ren = 1'b0;
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next_state_pad = SM_PAD_PAD;
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next_state_pad = SM_PAD_PAD;
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end
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end
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else if (byte_cnt == 14'd56 &&
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else if (byte_cnt == 14'd60 &&
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(txdfifo_rstatus[2:0] == 3'd1 ||
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(txdfifo_rstatus[2:0] == 3'd1 ||
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txdfifo_rstatus[2:0] == 3'd2 ||
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txdfifo_rstatus[2:0] == 3'd2 ||
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txdfifo_rstatus[2:0] == 3'd3)) begin
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txdfifo_rstatus[2:0] == 3'd3)) begin
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// Pad up to LANE3, keep the other 4 bytes for crc that will
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// Pad up to LANE3, keep the other 4 bytes for crc that will
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Line 812... |
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next_txhfifo_wdata = 64'b0;
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next_txhfifo_wdata = 64'b0;
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next_txhfifo_wstatus = `TXSTATUS_NONE;
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next_txhfifo_wstatus = `TXSTATUS_NONE;
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next_txhfifo_wen = 1'b1;
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next_txhfifo_wen = 1'b1;
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if (byte_cnt == 14'd56) begin
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if (byte_cnt == 14'd60) begin
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// Pad up to LANE3, keep the other 4 bytes for crc that will
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// Pad up to LANE3, keep the other 4 bytes for crc that will
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// be inserted by dequeue engine.
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// be inserted by dequeue engine.
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Line 861... |
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crc32_d64 <= 32'b0;
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crc32_d64 <= 32'b0;
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crc32_d8 <= 32'b0;
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crc32_d8 <= 32'b0;
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crc32_tx <= 32'b0;
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crc32_tx <= 32'b0;
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frame_end <= 1'b0;
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end
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end
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else begin
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else begin
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curr_state_pad <= next_state_pad;
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curr_state_pad <= next_state_pad;
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Line 874... |
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txhfifo_wdata <= next_txhfifo_wdata;
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txhfifo_wdata <= next_txhfifo_wdata;
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txhfifo_wstatus <= next_txhfifo_wstatus;
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txhfifo_wstatus <= next_txhfifo_wstatus;
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txhfifo_wen <= next_txhfifo_wen;
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txhfifo_wen <= next_txhfifo_wen;
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frame_end <= 1'b0;
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//---
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//---
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// Reset byte count on SOP
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// Reset byte count on SOP
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if (next_txhfifo_wen) begin
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if (next_txhfifo_wen) begin
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if (next_txhfifo_wstatus[`TXSTATUS_SOP]) begin
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if (next_txhfifo_wstatus[`TXSTATUS_SOP]) begin
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byte_cnt <= 14'd8;
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// Init byte count, 8-bytes + 4-bytes for CRC at the end of frame
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byte_cnt <= 14'd12;
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end
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else begin
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if (next_txhfifo_wstatus[`TXSTATUS_EOP] && next_txhfifo_wstatus[2:0] != 3'b0) begin
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byte_cnt <= byte_cnt + {11'b0, next_txhfifo_wstatus[2:0]};
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end
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end
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else begin
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else begin
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byte_cnt <= byte_cnt + 14'd8;
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byte_cnt <= byte_cnt + 14'd8;
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end
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end
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end
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end
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frame_end <= next_txhfifo_wstatus[`TXSTATUS_EOP];
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end
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//---
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//---
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// Calculate CRC as data is written to holding fifo. The holding fifo creates
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// Calculate CRC as data is written to holding fifo. The holding fifo creates
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// a delay that allow the CRC calculation to complete before the end of the frame
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// a delay that allow the CRC calculation to complete before the end of the frame
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// is ready to be transmited.
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// is ready to be transmited.
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