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[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [wishbone_if.v] - Diff between revs 12 and 20

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Rev 12 Rev 20
Line 144... Line 144...
        wb_dat_o <= 32'b0;
        wb_dat_o <= 32'b0;
        wb_int_o <= 1'b0;
        wb_int_o <= 1'b0;
 
 
        cpuack <= 1'b0;
        cpuack <= 1'b0;
 
 
        status_remote_fault_d1 <= status_remote_fault;
        status_remote_fault_d1 <= 1'b0;
        status_local_fault_d1 <= status_local_fault;
        status_local_fault_d1 <= 1'b0;
 
 
    end
    end
    else begin
    else begin
 
 
        wb_int_o <= |(cpureg_int_pending & cpureg_int_mask);
        wb_int_o <= |(cpureg_int_pending & cpureg_int_mask);
Line 223... Line 223...
 
 
end
end
 
 
endmodule
endmodule
 
 
 
 
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