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[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [wishbone_if.v] - Diff between revs 20 and 23

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Rev 20	Rev 23
Line 43...	Line 43...
`wb_dat_o, wb_ack_o, wb_int_o, ctrl_tx_enable,`	`wb_dat_o, wb_ack_o, wb_int_o, ctrl_tx_enable,`
`// Inputs`	`// Inputs`
`wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_we_i, wb_stb_i, wb_cyc_i,`	`wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_we_i, wb_stb_i, wb_cyc_i,`
`status_crc_error, status_fragment_error, status_txdfifo_ovflow,`	`status_crc_error, status_fragment_error, status_txdfifo_ovflow,`
`status_txdfifo_udflow, status_rxdfifo_ovflow, status_rxdfifo_udflow,`	`status_txdfifo_udflow, status_rxdfifo_ovflow, status_rxdfifo_udflow,`
`status_pause_frame_rx, status_local_fault, status_remote_fault`	`status_pause_frame_rx, status_local_fault, status_remote_fault,`
	`stats_tx_pkts, stats_rx_pkts`
`);`	`);`


`input wb_clk_i;`	`input wb_clk_i;`
`input wb_rst_i;`	`input wb_rst_i;`
Line 76...	Line 77...
`input status_pause_frame_rx;`	`input status_pause_frame_rx;`

`input status_local_fault;`	`input status_local_fault;`
`input status_remote_fault;`	`input status_remote_fault;`

	`input [31:0] stats_tx_pkts;`
	`input [31:0] stats_rx_pkts;`

`output ctrl_tx_enable;`	`output ctrl_tx_enable;`


`/AUTOREG/`	`/AUTOREG/`
`// Beginning of automatic regs (for this module's undeclared outputs)`	`// Beginning of automatic regs (for this module's undeclared outputs)`
Line 184...	Line 188...

`CPUREG_INT_MASK: begin	`CPUREG_INT_MASK: begin
`wb_dat_o <= {23'b0, cpureg_int_mask};`	`wb_dat_o <= {23'b0, cpureg_int_mask};`
`end`	`end`

	`CPUREG_STATSTXPKTS: begin
	`wb_dat_o <= stats_tx_pkts;`
	`end`

	`CPUREG_STATSRXPKTS: begin
	`wb_dat_o <= stats_rx_pkts;`
	`end`

`default: begin`	`default: begin`
`end`	`end`

`endcase`	`endcase`

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[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [wishbone_if.v] - Diff between revs 20 and 23