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`include "defines.v"
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`include "defines.v"
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module wishbone_if(/*AUTOARG*/
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module wishbone_if(/*AUTOARG*/
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// Outputs
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// Outputs
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wb_dat_o, wb_ack_o, wb_int_o, ctrl_tx_enable,
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wb_dat_o, wb_ack_o, wb_int_o, ctrl_tx_enable, clear_stats_tx_octets,
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clear_stats_tx_pkts, clear_stats_rx_octets, clear_stats_rx_pkts,
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// Inputs
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// Inputs
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wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_we_i, wb_stb_i, wb_cyc_i,
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wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_we_i, wb_stb_i, wb_cyc_i,
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status_crc_error, status_fragment_error, status_txdfifo_ovflow,
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status_crc_error, status_fragment_error, status_txdfifo_ovflow,
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status_txdfifo_udflow, status_rxdfifo_ovflow, status_rxdfifo_udflow,
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status_txdfifo_udflow, status_rxdfifo_ovflow, status_rxdfifo_udflow,
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status_pause_frame_rx, status_local_fault, status_remote_fault,
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status_pause_frame_rx, status_local_fault, status_remote_fault,
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input [31:0] stats_rx_octets;
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input [31:0] stats_rx_octets;
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input [31:0] stats_rx_pkts;
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input [31:0] stats_rx_pkts;
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output ctrl_tx_enable;
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output ctrl_tx_enable;
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output clear_stats_tx_octets;
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output clear_stats_tx_pkts;
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output clear_stats_rx_octets;
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output clear_stats_rx_pkts;
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/*AUTOREG*/
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/*AUTOREG*/
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// Beginning of automatic regs (for this module's undeclared outputs)
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// Beginning of automatic regs (for this module's undeclared outputs)
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reg clear_stats_rx_octets;
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reg clear_stats_rx_pkts;
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reg clear_stats_tx_octets;
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reg clear_stats_tx_pkts;
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reg [31:0] wb_dat_o;
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reg [31:0] wb_dat_o;
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reg wb_int_o;
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reg wb_int_o;
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// End of automatics
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// End of automatics
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reg [31:0] next_wb_dat_o;
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reg next_wb_int_o;
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reg [0:0] cpureg_config0;
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reg [0:0] cpureg_config0;
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reg [0:0] next_cpureg_config0;
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reg [8:0] cpureg_int_pending;
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reg [8:0] cpureg_int_pending;
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reg [8:0] next_cpureg_int_pending;
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reg [8:0] cpureg_int_mask;
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reg [8:0] cpureg_int_mask;
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reg [8:0] next_cpureg_int_mask;
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reg cpuack;
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reg cpuack;
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reg next_cpuack;
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reg status_remote_fault_d1;
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reg status_remote_fault_d1;
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reg status_local_fault_d1;
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reg status_local_fault_d1;
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/*AUTOWIRE*/
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/*AUTOWIRE*/
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wire [8:0] int_sources;
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wire [8:0] int_sources;
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//---
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//---
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// Config Register 0
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// Config Register 0
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assign ctrl_tx_enable = cpureg_config0[0];
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assign ctrl_tx_enable = cpureg_config0[0];
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//---
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//---
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// Wishbone signals
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// Wishbone signals
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assign wb_ack_o = cpuack && wb_stb_i;
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assign wb_ack_o = cpuack && wb_stb_i;
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always @(posedge wb_clk_i or posedge wb_rst_i) begin
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always @(/*AS*/cpureg_config0 or cpureg_int_mask or cpureg_int_pending
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or int_sources or stats_rx_octets or stats_rx_pkts
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if (wb_rst_i == 1'b1) begin
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or stats_tx_octets or stats_tx_pkts or wb_adr_i or wb_cyc_i
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or wb_dat_i or wb_dat_o or wb_stb_i or wb_we_i) begin
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cpureg_config0 <= 1'h1;
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cpureg_int_pending <= 9'b0;
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cpureg_int_mask <= 9'b0;
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wb_dat_o <= 32'b0;
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next_wb_dat_o = wb_dat_o;
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wb_int_o <= 1'b0;
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cpuack <= 1'b0;
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next_wb_int_o = |(cpureg_int_pending & cpureg_int_mask);
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status_remote_fault_d1 <= 1'b0;
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next_cpureg_int_pending = cpureg_int_pending | int_sources;
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status_local_fault_d1 <= 1'b0;
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end
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next_cpuack = wb_cyc_i && wb_stb_i;
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else begin
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wb_int_o <= |(cpureg_int_pending & cpureg_int_mask);
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//---
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// Registers
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cpureg_int_pending <= cpureg_int_pending | int_sources;
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next_cpureg_config0 = cpureg_config0;
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next_cpureg_int_mask = cpureg_int_mask;
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cpuack <= wb_cyc_i && wb_stb_i;
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//---
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// Clear on read signals
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status_remote_fault_d1 <= status_remote_fault;
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clear_stats_tx_octets = 1'b0;
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status_local_fault_d1 <= status_local_fault;
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clear_stats_tx_pkts = 1'b0;
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clear_stats_rx_octets = 1'b0;
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clear_stats_rx_pkts = 1'b0;
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//---
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//---
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// Read access
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// Read access
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if (wb_cyc_i && wb_stb_i && !wb_we_i) begin
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if (wb_cyc_i && wb_stb_i && !wb_we_i) begin
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case ({wb_adr_i[7:2], 2'b0})
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case ({wb_adr_i[7:2], 2'b0})
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`CPUREG_CONFIG0: begin
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`CPUREG_CONFIG0: begin
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wb_dat_o <= {31'b0, cpureg_config0};
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next_wb_dat_o = {31'b0, cpureg_config0};
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end
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end
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`CPUREG_INT_PENDING: begin
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`CPUREG_INT_PENDING: begin
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wb_dat_o <= {23'b0, cpureg_int_pending};
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next_wb_dat_o = {23'b0, cpureg_int_pending};
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cpureg_int_pending <= int_sources;
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next_cpureg_int_pending = int_sources;
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wb_int_o <= 1'b0;
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next_wb_int_o = 1'b0;
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end
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end
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`CPUREG_INT_STATUS: begin
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`CPUREG_INT_STATUS: begin
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wb_dat_o <= {23'b0, int_sources};
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next_wb_dat_o = {23'b0, int_sources};
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end
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end
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`CPUREG_INT_MASK: begin
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`CPUREG_INT_MASK: begin
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wb_dat_o <= {23'b0, cpureg_int_mask};
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next_wb_dat_o = {23'b0, cpureg_int_mask};
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end
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end
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`CPUREG_STATSTXOCTETS: begin
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`CPUREG_STATSTXOCTETS: begin
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wb_dat_o <= stats_tx_octets;
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next_wb_dat_o = stats_tx_octets;
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clear_stats_tx_octets = 1'b1;
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end
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end
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`CPUREG_STATSTXPKTS: begin
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`CPUREG_STATSTXPKTS: begin
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wb_dat_o <= stats_tx_pkts;
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next_wb_dat_o = stats_tx_pkts;
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clear_stats_tx_pkts = 1'b1;
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end
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end
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`CPUREG_STATSRXOCTETS: begin
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`CPUREG_STATSRXOCTETS: begin
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wb_dat_o <= stats_rx_octets;
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next_wb_dat_o = stats_rx_octets;
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clear_stats_rx_octets = 1'b1;
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end
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end
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`CPUREG_STATSRXPKTS: begin
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`CPUREG_STATSRXPKTS: begin
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wb_dat_o <= stats_rx_pkts;
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next_wb_dat_o = stats_rx_pkts;
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clear_stats_rx_pkts = 1'b1;
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end
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end
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default: begin
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default: begin
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end
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end
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if (wb_cyc_i && wb_stb_i && wb_we_i) begin
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if (wb_cyc_i && wb_stb_i && wb_we_i) begin
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case ({wb_adr_i[7:2], 2'b0})
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case ({wb_adr_i[7:2], 2'b0})
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`CPUREG_CONFIG0: begin
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`CPUREG_CONFIG0: begin
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cpureg_config0 <= wb_dat_i[0:0];
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next_cpureg_config0 = wb_dat_i[0:0];
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end
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end
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`CPUREG_INT_PENDING: begin
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`CPUREG_INT_PENDING: begin
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cpureg_int_pending <= wb_dat_i[8:0] | cpureg_int_pending | int_sources;
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next_cpureg_int_pending = wb_dat_i[8:0] | cpureg_int_pending | int_sources;
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end
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end
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`CPUREG_INT_MASK: begin
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`CPUREG_INT_MASK: begin
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cpureg_int_mask <= wb_dat_i[8:0];
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next_cpureg_int_mask = wb_dat_i[8:0];
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end
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end
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default: begin
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default: begin
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end
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end
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end
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end
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end
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end
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always @(posedge wb_clk_i or posedge wb_rst_i) begin
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if (wb_rst_i == 1'b1) begin
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cpureg_config0 <= 1'h1;
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cpureg_int_pending <= 9'b0;
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cpureg_int_mask <= 9'b0;
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wb_dat_o <= 32'b0;
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wb_int_o <= 1'b0;
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cpuack <= 1'b0;
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status_remote_fault_d1 <= 1'b0;
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status_local_fault_d1 <= 1'b0;
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end
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else begin
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cpureg_config0 <= next_cpureg_config0;
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cpureg_int_pending <= next_cpureg_int_pending;
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cpureg_int_mask <= next_cpureg_int_mask;
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wb_dat_o <= next_wb_dat_o;
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wb_int_o <= next_wb_int_o;
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cpuack <= next_cpuack;
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status_remote_fault_d1 <= status_remote_fault;
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status_local_fault_d1 <= status_local_fault;
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end
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end
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end
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endmodule
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endmodule
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