URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [tbench/] [systemc/] [sc_cpu_if.cpp] - Diff between revs 7 and 17

Rev 7	Rev 17
Line 87...	Line 87...
`// Wait for bus to be free, lock it, start transaction`	`// Wait for bus to be free, lock it, start transaction`

`bus_lock.lock();`	`bus_lock.lock();`
`bus_addr = addr;`	`bus_addr = addr;`
`bus_write = false;`	`bus_write = false;`
`bus_start.notify();`	`bus_start.post();`

`//--`	`//--`
`// Wait for transaction to complete`	`// Wait for transaction to complete`

`while (bus_done.trywait()) {`	`bus_done.wait();`
`wait(10, SC_NS);`
`};`

`//--`	`//--`
`// Get the data, free the bus`	`// Get the data, free the bus`

`data = bus_data;`	`data = bus_data;`
Line 115...	Line 113...

`bus_lock.lock();`	`bus_lock.lock();`
`bus_addr = addr;`	`bus_addr = addr;`
`bus_data = data;`	`bus_data = data;`
`bus_write = true;`	`bus_write = true;`
`bus_start.notify();`	`bus_start.post();`

`//--`	`//--`
`// Wait for transaction to complete`	`// Wait for transaction to complete`

`while (bus_done.trywait()) {`	`bus_done.wait();`
`wait(10, SC_NS);`
`};`

`//--`	`//--`
`// Free the bus`	`// Free the bus`

`cout << hex << "WRITE ADDR 0x" << addr << ": 0x" << data << dec << endl;`	`cout << hex << "WRITE ADDR 0x" << addr << ": 0x" << data << dec << endl;`
Line 150...	Line 146...


`while (true) {`	`while (true) {`

`// Wait for a transaction`	`// Wait for a transaction`
`wait(bus_start);`	`while (bus_start.trywait()) {`
	`wait();`
	`}`

`if (!bus_write) {`	`if (!bus_write) {`

`//---`	`//---`
`// Read access`	`// Read access`