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//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "tb_xge_mac.v" ////
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//// ////
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//// This file is part of the "10GE MAC" project ////
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//// http://www.opencores.org/cores/xge_mac/ ////
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//// ////
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//// Author(s): ////
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//// - A. Tanguay (antanguay@opencores.org) ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2008 AUTHORS. All rights reserved. ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "defines.v"
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//`define GXB
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//`define XIL
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module tb;
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/*AUTOREG*/
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reg [7:0] tx_buffer[0:10000];
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integer tx_length;
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reg clk_156m25;
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reg clk_312m50;
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reg clk_xgmii_rx;
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reg clk_xgmii_tx;
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reg reset_156m25_n;
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reg reset_xgmii_rx_n;
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reg reset_xgmii_tx_n;
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reg pkt_rx_ren;
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reg [63:0] pkt_tx_data;
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reg pkt_tx_val;
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reg pkt_tx_sop;
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reg pkt_tx_eop;
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reg [2:0] pkt_tx_mod;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire pkt_rx_avail; // From dut of xge_mac.v
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wire [63:0] pkt_rx_data; // From dut of xge_mac.v
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wire pkt_rx_eop; // From dut of xge_mac.v
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wire pkt_rx_err; // From dut of xge_mac.v
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wire [2:0] pkt_rx_mod; // From dut of xge_mac.v
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wire pkt_rx_sop; // From dut of xge_mac.v
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wire pkt_rx_val; // From dut of xge_mac.v
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wire pkt_tx_full; // From dut of xge_mac.v
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wire wb_ack_o; // From dut of xge_mac.v
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wire [31:0] wb_dat_o; // From dut of xge_mac.v
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wire wb_int_o; // From dut of xge_mac.v
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wire [7:0] xgmii_txc; // From dut of xge_mac.v
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wire [63:0] xgmii_txd; // From dut of xge_mac.v
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// End of automatics
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wire [7:0] wb_adr_i;
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wire [31:0] wb_dat_i;
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wire [7:0] xgmii_rxc;
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wire [63:0] xgmii_rxd;
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wire [3:0] tx_dataout;
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wire xaui_tx_l0_n;
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wire xaui_tx_l0_p;
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wire xaui_tx_l1_n;
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wire xaui_tx_l1_p;
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wire xaui_tx_l2_n;
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wire xaui_tx_l2_p;
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wire xaui_tx_l3_n;
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wire xaui_tx_l3_p;
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xge_mac dut(/*AUTOINST*/
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// Outputs
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.pkt_rx_avail (pkt_rx_avail),
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.pkt_rx_data (pkt_rx_data[63:0]),
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.pkt_rx_eop (pkt_rx_eop),
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.pkt_rx_err (pkt_rx_err),
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.pkt_rx_mod (pkt_rx_mod[2:0]),
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.pkt_rx_sop (pkt_rx_sop),
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.pkt_rx_val (pkt_rx_val),
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.pkt_tx_full (pkt_tx_full),
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.wb_ack_o (wb_ack_o),
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.wb_dat_o (wb_dat_o[31:0]),
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.wb_int_o (wb_int_o),
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.xgmii_txc (xgmii_txc[7:0]),
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.xgmii_txd (xgmii_txd[63:0]),
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// Inputs
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.clk_156m25 (clk_156m25),
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.clk_xgmii_rx (clk_xgmii_rx),
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.clk_xgmii_tx (clk_xgmii_tx),
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.pkt_rx_ren (pkt_rx_ren),
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.pkt_tx_data (pkt_tx_data[63:0]),
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.pkt_tx_eop (pkt_tx_eop),
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.pkt_tx_mod (pkt_tx_mod[2:0]),
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.pkt_tx_sop (pkt_tx_sop),
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.pkt_tx_val (pkt_tx_val),
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.reset_156m25_n (reset_156m25_n),
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.reset_xgmii_rx_n (reset_xgmii_rx_n),
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.reset_xgmii_tx_n (reset_xgmii_tx_n),
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.wb_adr_i (wb_adr_i[7:0]),
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.wb_clk_i (wb_clk_i),
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.wb_cyc_i (wb_cyc_i),
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.wb_dat_i (wb_dat_i[31:0]),
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.wb_rst_i (wb_rst_i),
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.wb_stb_i (wb_stb_i),
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.wb_we_i (wb_we_i),
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.xgmii_rxc (xgmii_rxc[7:0]),
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.xgmii_rxd (xgmii_rxd[63:0]));
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`ifdef GXB
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// Example of transceiver instance
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gxb gxb(// Outputs
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.rx_ctrldetect ({xgmii_rxc[7],
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xgmii_rxc[5],
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xgmii_rxc[3],
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xgmii_rxc[1],
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xgmii_rxc[6],
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xgmii_rxc[4],
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xgmii_rxc[2],
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xgmii_rxc[0]}),
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.rx_dataout ({xgmii_rxd[63:56],
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xgmii_rxd[47:40],
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xgmii_rxd[31:24],
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xgmii_rxd[15:8],
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xgmii_rxd[55:48],
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xgmii_rxd[39:32],
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xgmii_rxd[23:16],
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xgmii_rxd[7:0]}),
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.tx_dataout (tx_dataout[3:0]),
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// Inputs
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.pll_inclk (clk_156m25),
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.rx_analogreset (~reset_156m25_n),
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.rx_cruclk ({clk_156m25, clk_156m25, clk_156m25, clk_156m25}),
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.rx_datain (tx_dataout[3:0]),
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.rx_digitalreset (~reset_156m25_n),
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.tx_ctrlenable ({xgmii_txc[7],
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xgmii_txc[5],
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xgmii_txc[3],
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xgmii_txc[1],
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xgmii_txc[6],
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xgmii_txc[4],
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xgmii_txc[2],
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xgmii_txc[0]}),
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.tx_datain ({xgmii_txd[63:56],
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xgmii_txd[47:40],
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xgmii_txd[31:24],
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xgmii_txd[15:8],
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xgmii_txd[55:48],
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xgmii_txd[39:32],
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xgmii_txd[23:16],
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xgmii_txd[7:0]}),
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.tx_digitalreset (~reset_156m25_n));
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`endif
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`ifdef XIL
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// Example of transceiver instance
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xaui_block xaui(// Outputs
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.txoutclk (),
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.xgmii_rxd (xgmii_rxd[63:0]),
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.xgmii_rxc (xgmii_rxc[7:0]),
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.xaui_tx_l0_p (xaui_tx_l0_p),
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.xaui_tx_l0_n (xaui_tx_l0_n),
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.xaui_tx_l1_p (xaui_tx_l1_p),
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.xaui_tx_l1_n (xaui_tx_l1_n),
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.xaui_tx_l2_p (xaui_tx_l2_p),
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.xaui_tx_l2_n (xaui_tx_l2_n),
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.xaui_tx_l3_p (xaui_tx_l3_p),
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.xaui_tx_l3_n (xaui_tx_l3_n),
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.txlock (),
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.align_status (),
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.sync_status (),
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.mgt_tx_ready (),
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.drp_o (),
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.drp_rdy (),
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.status_vector (),
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// Inputs
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.dclk (clk_156m25),
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.clk156 (clk_156m25),
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.clk312 (clk_312m50),
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.refclk (clk_156m25),
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.reset (~reset_156m25_n),
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.reset156 (~reset_156m25_n),
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.xgmii_txd (xgmii_txd[63:0]),
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.xgmii_txc (xgmii_txc[7:0]),
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.xaui_rx_l0_p (xaui_tx_l0_p),
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.xaui_rx_l0_n (xaui_tx_l0_n),
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.xaui_rx_l1_p (xaui_tx_l1_p),
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.xaui_rx_l1_n (xaui_tx_l1_n),
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.xaui_rx_l2_p (xaui_tx_l2_p),
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.xaui_rx_l2_n (xaui_tx_l2_n),
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.xaui_rx_l3_p (xaui_tx_l3_p),
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.xaui_rx_l3_n (xaui_tx_l3_n),
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.signal_detect (4'b1111),
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.drp_addr (7'b0),
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.drp_en (2'b0),
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.drp_i (16'b0),
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.drp_we (2'b0),
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.configuration_vector (7'b0));
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glbl glbl();
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`endif
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//---
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// Unused for this testbench
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assign wb_adr_i = 8'b0;
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assign wb_clk_i = 1'b0;
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assign wb_cyc_i = 1'b0;
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assign wb_dat_i = 32'b0;
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assign wb_rst_i = 1'b1;
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assign wb_stb_i = 1'b0;
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assign wb_we_i = 1'b0;
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//---
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// XGMII Loopback
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// This test is done with loopback on XGMII or using one of the tranceiver examples
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`ifndef GXB
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`ifndef XIL
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assign xgmii_rxc = xgmii_txc;
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assign xgmii_rxd = xgmii_txd;
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`endif
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`endif
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//---
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// Clock generation
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initial begin
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clk_156m25 = 1'b0;
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clk_xgmii_rx = 1'b0;
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clk_xgmii_tx = 1'b0;
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forever begin
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WaitPS(3200);
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clk_156m25 = ~clk_156m25;
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clk_xgmii_rx = ~clk_xgmii_rx;
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clk_xgmii_tx = ~clk_xgmii_tx;
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end
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end
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initial begin
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clk_312m50 = 1'b0;
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forever begin
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WaitPS(1600);
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clk_312m50 = ~clk_312m50;
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end
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end
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//---
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// Reset Generation
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initial begin
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reset_156m25_n = 1'b0;
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reset_xgmii_rx_n = 1'b0;
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reset_xgmii_tx_n = 1'b0;
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WaitNS(20);
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reset_156m25_n = 1'b1;
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reset_xgmii_rx_n = 1'b1;
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reset_xgmii_tx_n = 1'b1;
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end
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//---
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// Init signals
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initial begin
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for (tx_length = 0; tx_length <= 1000; tx_length = tx_length + 1) begin
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tx_buffer[tx_length] = 0;
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end
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pkt_rx_ren = 1'b0;
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pkt_tx_data = 64'b0;
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pkt_tx_val = 1'b0;
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pkt_tx_sop = 1'b0;
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pkt_tx_eop = 1'b0;
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pkt_tx_mod = 3'b0;
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end
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task WaitNS;
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input [31:0] delay;
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begin
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#(1000*delay);
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end
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endtask
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task WaitPS;
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input [31:0] delay;
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begin
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#(delay);
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end
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endtask
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//---
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// Task to send a single packet
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task TxPacket;
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integer i;
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begin
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$display("Transmit packet with length: %d", tx_length);
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@(posedge clk_156m25);
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WaitNS(1);
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pkt_tx_val = 1'b1;
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for (i = 0; i < tx_length; i = i + 8) begin
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pkt_tx_sop = 1'b0;
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pkt_tx_eop = 1'b0;
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pkt_tx_mod = 2'b0;
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if (i == 0) pkt_tx_sop = 1'b1;
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if (i + 8 >= tx_length) begin
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pkt_tx_eop = 1'b1;
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pkt_tx_mod = tx_length % 8;
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end
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pkt_tx_data[`LANE7] = tx_buffer[i];
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pkt_tx_data[`LANE6] = tx_buffer[i+1];
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pkt_tx_data[`LANE5] = tx_buffer[i+2];
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pkt_tx_data[`LANE4] = tx_buffer[i+3];
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pkt_tx_data[`LANE3] = tx_buffer[i+4];
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pkt_tx_data[`LANE2] = tx_buffer[i+5];
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pkt_tx_data[`LANE1] = tx_buffer[i+6];
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pkt_tx_data[`LANE0] = tx_buffer[i+7];
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@(posedge clk_156m25);
|
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WaitNS(1);
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end
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pkt_tx_val = 1'b0;
|
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pkt_tx_eop = 1'b0;
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pkt_tx_mod = 3'b0;
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end
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endtask
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//---
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// Task to read a single packet from command file and transmit
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|
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task CmdTxPacket;
|
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input [31:0] file;
|
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integer count;
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integer data;
|
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integer i;
|
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begin
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count = $fscanf(file, "%2d", tx_length);
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if (count == 1) begin
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for (i = 0; i < tx_length; i = i + 1) begin
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|
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count = $fscanf(file, "%2X", data);
|
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if (count) begin
|
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tx_buffer[i] = data;
|
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end
|
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end
|
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|
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TxPacket();
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|
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end
|
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end
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endtask
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//---
|
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// Task to read commands from file and stop when complete
|
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|
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task ProcessCmdFile;
|
|
integer file_cmd;
|
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integer count;
|
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reg [8*8-1:0] str;
|
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begin
|
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|
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file_cmd = $fopen("../../tbench/verilog/packets_tx.txt", "r");
|
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if (!file_cmd) $stop;
|
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|
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while (!$feof(file_cmd)) begin
|
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|
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count = $fscanf(file_cmd, "%s", str);
|
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if (count != 1) continue;
|
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|
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$display("CMD %s", str);
|
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|
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case (str)
|
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|
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"SEND_PKT":
|
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begin
|
|
CmdTxPacket(file_cmd);
|
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end
|
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endcase
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end
|
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|
|
$fclose(file_cmd);
|
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|
|
WaitNS(50000);
|
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$stop;
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|
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end
|
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endtask
|
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|
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initial begin
|
|
WaitNS(5000);
|
|
`ifdef XIL
|
|
WaitNS(200000);
|
|
`endif
|
|
ProcessCmdFile();
|
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end
|
|
|
|
|
|
//---
|
|
// Task to read a single packet from receive interface and display
|
|
|
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task RxPacket;
|
|
reg done;
|
|
begin
|
|
|
|
done = 0;
|
|
|
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pkt_rx_ren <= 1'b1;
|
|
@(posedge clk_156m25);
|
|
|
|
while (!done) begin
|
|
|
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if (pkt_rx_val) begin
|
|
|
|
if (pkt_rx_sop) begin
|
|
$display("\n\n------------------------");
|
|
end
|
|
|
|
$display("%x", pkt_rx_data);
|
|
|
|
if (pkt_rx_eop) begin
|
|
done <= 1;
|
|
pkt_rx_ren <= 1'b0;
|
|
end
|
|
|
|
if (pkt_rx_eop) begin
|
|
$display("------------------------\n\n");
|
|
end
|
|
|
|
end
|
|
|
|
@(posedge clk_156m25);
|
|
|
|
end
|
|
|
|
end
|
|
endtask
|
|
|
|
initial begin
|
|
|
|
forever begin
|
|
|
|
if (pkt_rx_avail) begin
|
|
RxPacket();
|
|
end
|
|
|
|
@(posedge clk_156m25);
|
|
|
|
end
|
|
|
|
end
|
|
|
|
endmodule
|
