OpenCores
URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [tbench/] [verilog/] [tb_xge_mac.sv] - Diff between revs 17 and 21

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 17 Rev 21
Line 39... Line 39... 
`include "timescale.v"
 
`include "timescale.v"
 
`include "defines.v"
 
`include "defines.v"
 
 
 
 
 
//`define GXB
 
//`define GXB
 
//`define XIL
 
//`define XIL
 
 
 
//`define XIL_V10
 
 
 
 
 
module tb;
 
module tb;
 
 
 
 
 
 
 
 
 
/*AUTOREG*/
 
/*AUTOREG*/
Line 233... Line 234... 
                .configuration_vector   (7'b0));
 
                .configuration_vector   (7'b0));
 
 
 
 
 
glbl glbl();
 
glbl glbl();
 
`endif
 
`endif
 
 
 
 
 
 
 
`ifdef XIL_V10
 
 
 
// Example of transceiver instance
 
 
 
xaui_v10_2_block xaui(// Outputs
 
 
 
                .txoutclk               (),
 
 
 
                .xgmii_rxd              (xgmii_rxd[63:0]),
 
 
 
                .xgmii_rxc              (xgmii_rxc[7:0]),
 
 
 
                .xaui_tx_l0_p           (xaui_tx_l0_p),
 
 
 
                .xaui_tx_l0_n           (xaui_tx_l0_n),
 
 
 
                .xaui_tx_l1_p           (xaui_tx_l1_p),
 
 
 
                .xaui_tx_l1_n           (xaui_tx_l1_n),
 
 
 
                .xaui_tx_l2_p           (xaui_tx_l2_p),
 
 
 
                .xaui_tx_l2_n           (xaui_tx_l2_n),
 
 
 
                .xaui_tx_l3_p           (xaui_tx_l3_p),
 
 
 
                .xaui_tx_l3_n           (xaui_tx_l3_n),
 
 
 
                .txlock                 (),
 
 
 
                .align_status           (),
 
 
 
                .sync_status            (),
 
 
 
                .mgt_tx_ready           (),
 
 
 
                .drp_o                  (),
 
 
 
                .drp_rdy                (),
 
 
 
                .status_vector          (),
 
 
 
                // Inputs
 
 
 
                .dclk                   (clk_156m25),
 
 
 
                .clk156                 (clk_156m25),
 
 
 
                .refclk                 (clk_156m25),
 
 
 
                .reset                  (~reset_156m25_n),
 
 
 
                .reset156               (~reset_156m25_n),
 
 
 
                .xgmii_txd              (xgmii_txd[63:0]),
 
 
 
                .xgmii_txc              (xgmii_txc[7:0]),
 
 
 
                .xaui_rx_l0_p           (xaui_tx_l0_p),
 
 
 
                .xaui_rx_l0_n           (xaui_tx_l0_n),
 
 
 
                .xaui_rx_l1_p           (xaui_tx_l1_p),
 
 
 
                .xaui_rx_l1_n           (xaui_tx_l1_n),
 
 
 
                .xaui_rx_l2_p           (xaui_tx_l2_p),
 
 
 
                .xaui_rx_l2_n           (xaui_tx_l2_n),
 
 
 
                .xaui_rx_l3_p           (xaui_tx_l3_p),
 
 
 
                .xaui_rx_l3_n           (xaui_tx_l3_n),
 
 
 
                .signal_detect          (4'b1111),
 
 
 
                .drp_addr               (9'b0),
 
 
 
                .drp_en                 (4'b0),
 
 
 
                .drp_i                  (16'b0),
 
 
 
                .drp_we                 (4'b0),
 
 
 
                .configuration_vector   (7'b0));
 
 
 
 
 
 
 
glbl glbl();
 
 
 
`endif
 
 
 
 
 
//---
 
//---
 
// Unused for this testbench
 
// Unused for this testbench
 
 
 
 
 
assign wb_adr_i = 8'b0;
 
assign wb_adr_i = 8'b0;
 
assign wb_clk_i = 1'b0;
 
assign wb_clk_i = 1'b0;
Line 256... Line 304... 
// XGMII Loopback
 
// XGMII Loopback
 
// This test is done with loopback on XGMII or using one of the tranceiver examples
 
// This test is done with loopback on XGMII or using one of the tranceiver examples
 
 
 
 
 
`ifndef GXB
 
`ifndef GXB
 
  `ifndef XIL
 
  `ifndef XIL
 
 
 
    `ifndef XIL_V10
 
    assign xgmii_rxc = xgmii_txc;
 
    assign xgmii_rxc = xgmii_txc;
 
    assign xgmii_rxd = xgmii_txd;
 
    assign xgmii_rxd = xgmii_txd;
 
  `endif
 
  `endif
 
`endif
 
`endif
 
 
 
`endif
 
 
 
 
 
//---
 
//---
 
// Clock generation
 
// Clock generation
 
 
 
 
 
initial begin
 
initial begin

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.