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[/] [xge_mac/] [trunk/] [tbench/] [verilog/] [tb_xge_mac.sv] - Diff between revs 21 and 23

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Rev 21 Rev 23
Line 66... Line 66... 
reg           pkt_tx_val;
 
reg           pkt_tx_val;
 
reg           pkt_tx_sop;
 
reg           pkt_tx_sop;
 
reg           pkt_tx_eop;
 
reg           pkt_tx_eop;
 
reg  [2:0]    pkt_tx_mod;
 
reg  [2:0]    pkt_tx_mod;
 
 
 
 
 
 
 
reg           wb_clk_i;
 
 
 
reg  [31:0]   wb_adr_i;
 
 
 
reg           wb_cyc_i;
 
 
 
reg  [31:0]   wb_dat_i;
 
 
 
reg           wb_rst_i;
 
 
 
reg           wb_stb_i;
 
 
 
reg           wb_we_i;
 
 
 
 
 
integer       tx_count;
 
integer       tx_count;
 
integer       rx_count;
 
integer       rx_count;
 
 
 
 
 
/*AUTOWIRE*/
 
/*AUTOWIRE*/
 
// Beginning of automatic wires (for undeclared instantiated-module outputs)
 
// Beginning of automatic wires (for undeclared instantiated-module outputs)
Line 86... Line 94... 
wire                    wb_int_o;               // From dut of xge_mac.v
 
wire                    wb_int_o;               // From dut of xge_mac.v
 
wire [7:0]              xgmii_txc;              // From dut of xge_mac.v
 
wire [7:0]              xgmii_txc;              // From dut of xge_mac.v
 
wire [63:0]             xgmii_txd;              // From dut of xge_mac.v
 
wire [63:0]             xgmii_txd;              // From dut of xge_mac.v
 
// End of automatics
 
// End of automatics
 
 
 
 
 
wire  [7:0]   wb_adr_i;
 
 
 
wire  [31:0]  wb_dat_i;
 
 
 
 
 
 
 
wire [7:0]              xgmii_rxc;
 
wire [7:0]              xgmii_rxc;
 
wire [63:0]             xgmii_rxd;
 
wire [63:0]             xgmii_rxd;
 
 
 
 
 
wire [3:0]              tx_dataout;
 
wire [3:0]              tx_dataout;
 
 
 
 
Line 282... Line 287... 
 
 
 
 
glbl glbl();
 
glbl glbl();
 
`endif
 
`endif
 
 
 
 
 
//---
 
//---
 
// Unused for this testbench
 
// Wishbone
 
 
 
 
 
assign wb_adr_i = 8'b0;
 
 
 
assign wb_clk_i = 1'b0;
 
 
 
assign wb_cyc_i = 1'b0;
 
 
 
assign wb_dat_i = 32'b0;
 
 
 
assign wb_rst_i = 1'b1;
 
 
 
assign wb_stb_i = 1'b0;
 
 
 
assign wb_we_i = 1'b0;
 
 
 
 
 
 
 
 
 
initial begin
 
 
 
    wb_adr_i <= 8'b0;
 
 
 
    wb_cyc_i <= 1'b0;
 
 
 
    wb_dat_i <= 32'b0;
 
 
 
    wb_rst_i <= 1'b1;
 
 
 
    wb_stb_i <= 1'b0;
 
 
 
    wb_we_i <= 1'b0;
 
 
 
    @(posedge wb_clk_i);
 
 
 
    wb_rst_i <= 1'b0;
 
 
 
end
 
 
 
 
 
initial begin
 
initial begin
 
    tx_count = 0;
 
    tx_count = 0;
 
    rx_count = 0;
 
    rx_count = 0;
 
end
 
end
Line 315... Line 322... 
 
 
 
 
//---
 
//---
 
// Clock generation
 
// Clock generation
 
 
 
 
 
initial begin
 
initial begin
 
    clk_156m25 = 1'b0;
 
    clk_156m25 <= 1'b0;
 
    clk_xgmii_rx = 1'b0;
 
    clk_xgmii_rx <= 1'b0;
 
    clk_xgmii_tx = 1'b0;
 
    clk_xgmii_tx <= 1'b0;
 
    forever begin
 
    forever begin
 
        WaitPS(3200);
 
        WaitPS(3200);
 
        clk_156m25 = ~clk_156m25;
 
        clk_156m25 <= ~clk_156m25;
 
        clk_xgmii_rx = ~clk_xgmii_rx;
 
        clk_xgmii_rx <= ~clk_xgmii_rx;
 
        clk_xgmii_tx = ~clk_xgmii_tx;
 
        clk_xgmii_tx <= ~clk_xgmii_tx;
 
 
 
    end
 
 
 
end
 
 
 
 
 
 
 
initial begin
 
 
 
    wb_clk_i <= 1'b0;
 
 
 
    forever begin
 
 
 
        WaitPS(20000);
 
 
 
        wb_clk_i <= ~wb_clk_i;
 
    end
 
    end
 
end
 
end
 
 
 
 
 
initial begin
 
initial begin
 
    clk_312m50 = 1'b0;
 
    clk_312m50 = 1'b0;
Line 381... Line 396... 
    begin
 
    begin
 
        #(delay);
 
        #(delay);
 
    end
 
    end
 
endtask
 
endtask
 
 
 
 
 
 
 
//---
 
 
 
// Task to read register
 
 
 
 
 
 
 
task CpuRead;
 
 
 
  input [31:0] addr;
 
 
 
  output [31:0] data;
 
 
 
    begin
 
 
 
        @(posedge wb_clk_i);
 
 
 
        wb_adr_i <= addr;
 
 
 
        wb_cyc_i <= 1'b1;
 
 
 
        wb_stb_i <= 1'b1;
 
 
 
        @(posedge wb_clk_i);
 
 
 
        wb_stb_i <= 1'b0;
 
 
 
        @(posedge wb_clk_i);
 
 
 
        wb_cyc_i <= 1'b0;
 
 
 
        data <= wb_dat_o;
 
 
 
        @(posedge wb_clk_i);
 
 
 
    end
 
 
 
endtask
 
 
 
 
 
//---
 
//---
 
// Task to send a single packet
 
// Task to send a single packet
 
 
 
 
 
task TxPacket;
 
task TxPacket;
Line 471... Line 505... 
 
 
 
 
task ProcessCmdFile;
 
task ProcessCmdFile;
 
  integer    file_cmd;
 
  integer    file_cmd;
 
  integer  count;
 
  integer  count;
 
  reg [8*8-1:0] str;
 
  reg [8*8-1:0] str;
 
 
 
  reg [31:0] data;
 
    begin
 
    begin
 
 
 
 
 
        file_cmd = $fopen("../../tbench/verilog/packets_tx.txt", "r");
 
        file_cmd = $fopen("../../tbench/verilog/packets_tx.txt", "r");
 
        if (!file_cmd) $stop;
 
        if (!file_cmd) $stop;
 
 
 
 
Line 497... Line 532... 
        end
 
        end
 
 
 
 
 
        $fclose(file_cmd);
 
        $fclose(file_cmd);
 
 
 
 
 
        WaitNS(50000);
 
        WaitNS(50000);
 
 
 
 
 
 
 
        CpuRead(`CPUREG_STATSTXPKTS, data);
 
 
 
        CpuRead(`CPUREG_STATSRXPKTS, data);
 
 
 
 
 
        $stop;
 
        $stop;
 
 
 
 
 
    end
 
    end
 
endtask
 
endtask
 
 
 
 

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