Subversion Repositories xucpu

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.numeric_std.ALL;

USE work.mux_parts.ALL;

USE work.hexio.ALL;

USE work.ram_parts.all;

-- Pipelined 32k memory

ENTITY RAM32K_P IS

  -- This component is based upon the above defined memory

  -- It is constructed using a 4-to-1 multiplexer and 4 8k word

  -- memories.

  GENERIC (

    w_data   : NATURAL RANGE 1 TO 32 := 16;

    filename : STRING                := "");

  PORT (

    clk : IN  STD_LOGIC;

    we  : IN  STD_LOGIC;

    a1  : IN  STD_LOGIC_VECTOR(14 DOWNTO 0);  -- Data port address

    a2  : IN  STD_LOGIC_VECTOR(14 DOWNTO 0);  -- Instruction port address

    d1  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);   -- Data port input

    q1  : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);   -- Data port output

    q2  : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));  -- Instruction port output

END RAM32K_P;

ARCHITECTURE Structural OF RAM32K_P IS

  CONSTANT memory_array : B32K_array_type := init_b32k(filename);

  SIGNAL data_address  : STD_LOGIC_VECTOR(12 DOWNTO 0);

  SIGNAL data_select   : STD_LOGIC_VECTOR(1 DOWNTO 0);

  SIGNAL instr_address : STD_LOGIC_VECTOR(12 DOWNTO 0);

  SIGNAL instr_select  : STD_LOGIC_VECTOR(1 DOWNTO 0);

  SIGNAL wr_sel : STD_LOGIC_VECTOR(3 DOWNTO 0);

  TYPE bus_array_t IS ARRAY(0 TO 3) OF STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);

  SIGNAL data : bus_array_t;

  SIGNAL inst : bus_array_t;

  TYPE file_array IS ARRAY(INTEGER RANGE <>) OF STRING(1 TO 100);

BEGIN  -- Structural

  data_address <= a1(12 DOWNTO 0);

  data_select  <= a1(14 DOWNTO 13);

  instr_address <= a2(12 DOWNTO 0);

  instr_select  <= a2(14 DOWNTO 13);

  wr_sel <= "0001" WHEN data_select = "00" AND we = '1' ELSE

            "0010" WHEN data_select = "01" AND we = '1' ELSE

            "0100" WHEN data_select = "10" AND we = '1' ELSE

            "1000" WHEN data_select = "11" AND we = '1' ELSE

            "0000";

  M1 : mux4to1

    PORT MAP (

      SEL => data_select,

      S0  => data(0),

      S1  => data(1),

      S2  => data(2),

      S3  => data(3),

      Y   => q1);

  M2 : mux4to1

    PORT MAP (

      SEL => instr_select,

      S0  => inst(0),

      S1  => inst(1),

      S2  => inst(2),

      S3  => inst(3),

      Y   => q2);

  RAM : FOR i IN 0 TO 3 GENERATE

    R0 : generic_memory_block

      GENERIC MAP (

        init_data => memory_array(i),

        w_data   => w_data,

        w_addr   => 13)

      PORT MAP (

        clk => clk,

        we  => wr_sel(i),

        a1  => data_address,

        a2  => instr_address,

        d1  => d1,

        q1  => data(i),

        q2  => inst(i));

  END GENERATE RAM;

END Structural;