URL
https://opencores.org/ocsvn/xucpu/xucpu/trunk
[/] [xucpu/] [trunk/] [target/] [Xilinx/] [1k/] [functional.wcfg] - Diff between revs 12 and 41
Show entire file |
Details |
Blame |
View Log
| Rev 12 |
Rev 41 |
?rev1line? |
?rev2line? |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
clock
|
|
clock
|
|
|
|
|
|
reset
|
|
reset
|
|
|
|
|
|
sys_clk
|
|
sys_clk
|
|
|
|
|
|
sys_rst
|
|
sys_rst
|
|
|
|
|
|
int_rst
|
|
int_rst
|
|
|
|
|
|
addr_out[14:0]
|
|
addr_out[14:0]
|
|
|
|
|
|
address[14:0]
|
|
address[14:0]
|
|
|
|
|
|
clka
|
|
clka
|
|
|
|
|
|
addra[14:0]
|
|
addra[14:0]
|
|
|
|
|
|
douta[15:0]
|
|
douta[15:0]
|
|
|
|
|
|
databus_in[15:0]
|
|
databus_in[15:0]
|
|
|
|
|
|
data_in[15:0]
|
|
data_in[15:0]
|
|
|
|
|
|
d_ir_load
|
|
d_ir_load
|
|
|
|
|
|
ir[15:0]
|
|
ir[15:0]
|
|
|
|
|
|
state
|
|
state
|
|
|
|
|
|
data_in[15:0]
|
|
data_in[15:0]
|
|
|
|
|
|
we
|
|
we
|
|
|
|
|
|
register_file[0:31]
|
|
register_file[0:31]
|
|
|
|
|
|
pc[14:0]
|
|
pc[14:0]
|
|
|
|
|
|
addr_out_reg[14:0]
|
|
addr_out_reg[14:0]
|
|
|
|
|
|
data_out_reg[15:0]
|
|
data_out_reg[15:0]
|
|
|
|
|
|
a[15:0]
|
|
a[15:0]
|
|
|
|
|
|
b[15:0]
|
|
b[15:0]
|
|
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.
