| Line 1... |
Line 1... |
/*******************************************************************************************/
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/*******************************************************************************************/
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/** **/
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/** **/
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/** COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
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/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
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/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
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/** **/
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/** **/
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/** control module Rev 0.0 08/22/2011 **/
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/** control module Rev 0.0 06/13/2012 **/
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/** **/
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/** **/
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/*******************************************************************************************/
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/*******************************************************************************************/
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module control (add_sel, alua_sel, alub_sel, aluop_sel, cflg_en, di_ctl, do_ctl, ex_af_pls,
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module control (add_sel, alua_sel, alub_sel, aluop_sel, cflg_en, di_ctl, do_ctl, ex_af_pls,
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ex_bank_pls, ex_dehl_inst, halt_nxt, hflg_ctl, ief_ctl, if_frst, inta_frst,
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ex_bank_pls, ex_dehl_inst, halt_nxt, hflg_ctl, ief_ctl, if_frst, inta_frst,
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imd_ctl, ld_dmaa, ld_inst, ld_inta, ld_page, ld_wait, nflg_ctl, output_inh,
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imd_ctl, ld_dmaa, ld_inst, ld_inta, ld_page, ld_wait, nflg_ctl, output_inh,
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page_sel, pc_sel, pflg_ctl, rd_frst, rd_nxt, reti_nxt, rreg_en, sflg_en, state_nxt,
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page_sel, pc_sel, pflg_ctl, rd_frst, rd_nxt, reti_nxt, rreg_en, sflg_en, state_nxt,
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tflg_ctl, tran_sel, wr_addr, wr_frst, zflg_en, carry_bit, dmar_reg, inst_reg,
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tflg_ctl, tran_sel, wr_addr, wr_frst, zflg_en, carry_bit, dmar_reg, inst_reg,
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intr_reg, page_reg, par_bit, sign_bit, state_reg, tflg_reg, vector_int,
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intr_reg, page_reg, par_bit, sign_bit, state_reg, tflg_reg, vector_int,
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xhlt_reg, zero_bit);
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xhlt_reg, zero_bit, int_req);
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|
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input carry_bit; /* carry flag */
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input carry_bit; /* carry flag */
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input dmar_reg; /* latched dma request */
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input dmar_reg; /* latched dma request */
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input intr_reg; /* latched interrupt request */
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input intr_reg; /* latched interrupt request */
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input int_req; /* interrupt request (for SLP) */
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input par_bit; /* parity flag */
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input par_bit; /* parity flag */
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input sign_bit; /* sign flag */
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input sign_bit; /* sign flag */
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input tflg_reg; /* temporary flag */
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input tflg_reg; /* temporary flag */
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input vector_int; /* int vector enable */
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input vector_int; /* int vector enable */
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input xhlt_reg; /* halt exit */
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input xhlt_reg; /* halt exit */
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| Line 314... |
Line 316... |
casex ({page_reg, inst_reg}) //synopsys parallel_case
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casex ({page_reg, inst_reg}) //synopsys parallel_case
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12'b0010xxxxx110,
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12'b0010xxxxx110,
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12'b010x11100001,
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12'b010x11100001,
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12'b010x11100011,
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12'b010x11100011,
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12'b010x11100101,
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12'b010x11100101,
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12'b1xxx00xxx11x, //ld (hl),rr; ld (hl),ii; ld rr,(hl); ld ii,(hl)
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12'b1xxx0100x101,
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12'b1xxx0100x101,
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12'b1xxx0110x111,
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12'b1xxx0110x111,
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12'b1xxx01xxx00x,
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12'b1xxx01xxx00x,
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12'b1xxx01110110, //slp
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12'b1xxx100xx01x, //indm,indmr,inim,inimr, otdm,otdmr,otim,otimr
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12'b1xxx101xx0xx,
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12'b1xxx101xx0xx,
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12'b1xxx10xxx100, //ind2,ind2r,ini2,ini2r, outd2,otd2r,outi2,oti2r
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12'b1xxx1100x01x, //indrx,inirx, otdrx,otirx
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12'b010x11101001: ld_wait = 1'b0;
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12'b010x11101001: ld_wait = 1'b0;
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default: ld_wait = 1'b1;
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default: ld_wait = 1'b1;
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endcase
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endcase
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end
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end
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`OF2A,
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`OF2A,
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| Line 482... |
Line 489... |
12'b010011100011,
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12'b010011100011,
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12'b010011100101,
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12'b010011100101,
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12'b010111100001,
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12'b010111100001,
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12'b010111100011,
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12'b010111100011,
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12'b010111100101,
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12'b010111100101,
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12'b1xxx00110100,
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12'b1xxx01000101,
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12'b1xxx01000101,
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12'b1xxx01001101,
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12'b1xxx01001101,
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12'b1xxx01100111,
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12'b1xxx01100111,
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12'b1xxx01101111,
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12'b1xxx01101111,
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12'b1xxx01xxx000,
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12'b1xxx01xxx000,
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12'b1xxx01xxx001,
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12'b1xxx01xxx001,
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12'b1xxx10000011,
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12'b1xxx10001011,
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12'b1xxx10010011,
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12'b1xxx10011011,
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12'b1xxx10100000,
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12'b1xxx10100000,
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12'b1xxx10100001,
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12'b1xxx10100001,
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12'b1xxx10100010,
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12'b1xxx10100010,
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12'b1xxx10100011,
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12'b1xxx10100011,
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12'b1xxx10101000,
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12'b1xxx10101000,
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| Line 571... |
Line 583... |
12'b010011111001,
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12'b010011111001,
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12'b010100100011,
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12'b010100100011,
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12'b010100101011,
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12'b010100101011,
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12'b010100xx1001,
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12'b010100xx1001,
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12'b010111111001,
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12'b010111111001,
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12'b1xxx000xx100,12'b1xxx0010x100,12'b1xxx00111100,
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12'b1xxx01000100,
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12'b1xxx01000100,
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12'b1xxx01000110,
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12'b1xxx01000110,
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12'b1xxx01000111,
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12'b1xxx01000111,
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12'b1xxx01001111,
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12'b1xxx01001111,
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12'b1xxx01010110,
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12'b1xxx01010110,
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12'b1xxx01010111,
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12'b1xxx01010111,
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12'b1xxx01011110,
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12'b1xxx01011110,
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12'b1xxx01011111,
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12'b1xxx01011111,
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12'b1xxx01xx0010,
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12'b1xxx01xx0010,
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12'b1xxx01xx1010: state_nxt = `sIF1B;
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12'b1xxx01xx1010,
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12'b1xxx01xx1100: state_nxt = `sIF1B;
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12'b010011101001,
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12'b010011101001,
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12'b010111101001: state_nxt = `sPCO;
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12'b010111101001,
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12'b1xxx01110110: state_nxt = `sPCO;
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default: state_nxt = `sOF1B;
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default: state_nxt = `sOF1B;
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endcase
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endcase
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end
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end
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`OF1B: begin
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`OF1B: begin
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casex ({page_reg, inst_reg}) //synopsys parallel_case
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casex ({page_reg, inst_reg}) //synopsys parallel_case
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| Line 613... |
Line 628... |
12'b010110010110,
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12'b010110010110,
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12'b010110011110,
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12'b010110011110,
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12'b010110100110,
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12'b010110100110,
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12'b010110101110,
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12'b010110101110,
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12'b010110110110,
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12'b010110110110,
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12'b010110111110: state_nxt = `sADR1;
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12'b010110111110,
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12'b1xxx00xxx000,
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12'b1xxx00xxx001,
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12'b1xxx01110100: state_nxt = `sADR1;
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12'b010000100110,
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12'b010000100110,
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12'b010000101110,
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12'b010000101110,
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12'b010100100110,
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12'b010100100110,
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12'b010100101110,
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12'b010100101110,
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12'b0000000xx110,12'b00000010x110,12'b000000111110,
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12'b0000000xx110,12'b00000010x110,12'b000000111110,
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| Line 626... |
Line 644... |
12'b000011010110,
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12'b000011010110,
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12'b000011011110,
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12'b000011011110,
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12'b000011100110,
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12'b000011100110,
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12'b000011101110,
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12'b000011101110,
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12'b000011110110,
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12'b000011110110,
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12'b000011111110: state_nxt = `sIF1A;
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12'b000011111110,
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12'b1xxx01100100: state_nxt = `sIF1A;
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12'b000000100000: state_nxt = ( !zero_bit) ? `sPCA : `sIF1A;
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12'b000000100000: state_nxt = ( !zero_bit) ? `sPCA : `sIF1A;
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12'b000000101000: state_nxt = ( zero_bit) ? `sPCA : `sIF1A;
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12'b000000101000: state_nxt = ( zero_bit) ? `sPCA : `sIF1A;
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12'b000000110000: state_nxt = (!carry_bit) ? `sPCA : `sIF1A;
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12'b000000110000: state_nxt = (!carry_bit) ? `sPCA : `sIF1A;
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12'b000000111000: state_nxt = ( carry_bit) ? `sPCA : `sIF1A;
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12'b000000111000: state_nxt = ( carry_bit) ? `sPCA : `sIF1A;
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12'b000000100010,
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12'b000000100010,
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| Line 705... |
Line 724... |
12'b010111100001,
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12'b010111100001,
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12'b010111100011,
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12'b010111100011,
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12'b1xxx01000101,
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12'b1xxx01000101,
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12'b1xxx01001101,
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12'b1xxx01001101,
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12'b1xxx01xx1011,
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12'b1xxx01xx1011,
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12'b1xxx100xx011,
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12'b1xxx10100000,
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12'b1xxx10100000,
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12'b1xxx10100001,
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12'b1xxx10100001,
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12'b1xxx10100010,
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12'b1xxx10100010,
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12'b1xxx10100011,
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12'b1xxx10100011,
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12'b1xxx10101000,
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12'b1xxx10101000,
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| Line 736... |
Line 756... |
12'b000000110010,
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12'b000000110010,
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12'b000001110xxx,
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12'b000001110xxx,
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12'b000011010011,
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12'b000011010011,
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12'b010001110xxx,
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12'b010001110xxx,
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12'b010101110xxx,
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12'b010101110xxx,
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12'b1xxx00xxx001,
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12'b1xxx01xxx001: state_nxt = `sWR2A;
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12'b1xxx01xxx001: state_nxt = `sWR2A;
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default: state_nxt = `sRD2A;
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default: state_nxt = `sRD2A;
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endcase
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endcase
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end
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end
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`RD1A: state_nxt = `sRD1B;
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`RD1A: state_nxt = `sRD1B;
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| Line 747... |
Line 768... |
casex ({page_reg, inst_reg}) //synopsys parallel_case
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casex ({page_reg, inst_reg}) //synopsys parallel_case
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12'b1xxx10100001,
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12'b1xxx10100001,
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12'b1xxx10101001,
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12'b1xxx10101001,
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12'b1xxx10110001,
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12'b1xxx10110001,
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12'b1xxx10111001: state_nxt = `sBLK1;
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12'b1xxx10111001: state_nxt = `sBLK1;
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12'b1xxx100xx011,
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12'b1xxx10100000,
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12'b1xxx10100000,
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12'b1xxx10100010,
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12'b1xxx10100010,
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12'b1xxx10100011,
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12'b1xxx10100011,
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12'b1xxx10101000,
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12'b1xxx10101000,
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12'b1xxx10101010,
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12'b1xxx10101010,
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| Line 816... |
Line 838... |
12'b010110110110,
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12'b010110110110,
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12'b010110111110,
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12'b010110111110,
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12'b010111100001,
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12'b010111100001,
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12'b011001xxx110,
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12'b011001xxx110,
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12'b011101xxx110,
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12'b011101xxx110,
|
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12'b1xxx00xxx000,
|
|
12'b1xxx0x110100,
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12'b1xxx01xxx000,
|
12'b1xxx01xxx000,
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12'b1xxx01xx1011: state_nxt = `sIF1A;
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12'b1xxx01xx1011: state_nxt = `sIF1A;
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12'b000011001001,
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12'b000011001001,
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12'b000011xxx000,
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12'b000011xxx000,
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12'b1xxx01000101,
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12'b1xxx01000101,
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| Line 832... |
Line 856... |
endcase
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endcase
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end
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end
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`WR1A: state_nxt = `sWR1B;
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`WR1A: state_nxt = `sWR1B;
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`WR1B: begin
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`WR1B: begin
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casex ({page_reg, inst_reg}) //synopsys parallel_case
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casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx1000x011,
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12'b1xxx10100000,
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12'b1xxx10100000,
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12'b1xxx10100010,
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12'b1xxx10100010,
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12'b1xxx10100011,
|
12'b1xxx10100011,
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12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101010,
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12'b1xxx10101010,
|
12'b1xxx10101011: state_nxt = `sIF1A;
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12'b1xxx10101011: state_nxt = `sIF1A;
|
|
12'b1xxx1001x011,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10111010,
|
12'b1xxx10111010,
|
12'b1xxx10110011,
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12'b1xxx10110011,
|
12'b1xxx10111011,
|
12'b1xxx10111011,
|
12'b1xxx10110000,
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12'b1xxx10110000,
|
| Line 850... |
Line 876... |
endcase
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endcase
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end
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end
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`WR2A: state_nxt = `sWR2B;
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`WR2A: state_nxt = `sWR2B;
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`WR2B: begin
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`WR2B: begin
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casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx1001x011,
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12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10111010,
|
12'b1xxx10111010,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111011,
|
12'b1xxx10111011,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
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| Line 871... |
Line 898... |
end
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end
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`PCA: state_nxt = `sPCO;
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`PCA: state_nxt = `sPCO;
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`PCO: begin
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`PCO: begin
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casex ({page_reg, inst_reg}) //synopsys parallel_case
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casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b000001110110: state_nxt = `sHLTA;
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12'b000001110110: state_nxt = `sHLTA;
|
|
12'b1xxx01110110: state_nxt = `sHLTA;
|
default: state_nxt = `sIF1A;
|
default: state_nxt = `sIF1A;
|
endcase
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endcase
|
end
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end
|
`HLTA: state_nxt = `sHLTB;
|
`HLTA: state_nxt = `sHLTB;
|
`HLTB: state_nxt = (xhlt_reg) ? `sIF1A : `sHLTA;
|
`HLTB: state_nxt = (xhlt_reg || (int_req && page_reg[3])) ? `sIF1A : `sHLTA;
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`IF1A: state_nxt = `sIF1B;
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`IF1A: state_nxt = `sIF1B;
|
`IF1B: state_nxt = `sDEC1;
|
`IF1B: state_nxt = `sDEC1;
|
`INTA: state_nxt = `sINTB;
|
`INTA: state_nxt = `sINTB;
|
`INTB: state_nxt = (vector_int) ? `sADR1 : `sWR1A;
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`INTB: state_nxt = (vector_int) ? `sADR1 : `sWR1A;
|
`DMA1: state_nxt = `sDMA2;
|
`DMA1: state_nxt = `sDMA2;
|
| Line 958... |
Line 986... |
`IF3B: tran_sel = `TRAN_MEM;
|
`IF3B: tran_sel = `TRAN_MEM;
|
`ADR2: begin
|
`ADR2: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b000011010011,
|
12'b000011010011,
|
12'b000011011011,
|
12'b000011011011,
|
|
12'b1xxx00xxx000,
|
|
12'b1xxx00xxx001,
|
12'b1xxx01xxx000,
|
12'b1xxx01xxx000,
|
12'b1xxx01xxx001,
|
12'b1xxx01xxx001,
|
|
12'b1xxx01110100,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10111010: tran_sel = `TRAN_IO;
|
12'b1xxx10111010: tran_sel = `TRAN_IO;
|
12'b000011001001,
|
12'b000011001001,
|
| Line 984... |
Line 1015... |
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b1xxx10100001,
|
12'b1xxx10100001,
|
12'b1xxx10101001,
|
12'b1xxx10101001,
|
12'b1xxx10110001,
|
12'b1xxx10110001,
|
12'b1xxx10111001: tran_sel = `TRAN_IDL;
|
12'b1xxx10111001: tran_sel = `TRAN_IDL;
|
|
12'b1xxx100xx011,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111011: tran_sel = `TRAN_IO;
|
12'b1xxx10111011: tran_sel = `TRAN_IO;
|
12'b000011001001,
|
12'b000011001001,
|
| Line 1048... |
Line 1080... |
12'b010110110110,
|
12'b010110110110,
|
12'b010110111110,
|
12'b010110111110,
|
12'b010111100001,
|
12'b010111100001,
|
12'b011001xxx110,
|
12'b011001xxx110,
|
12'b011101xxx110,
|
12'b011101xxx110,
|
|
12'b1xxx01110100,
|
12'b1xxx01xxx000,
|
12'b1xxx01xxx000,
|
12'b1xxx01xx1011: tran_sel = `TRAN_IF;
|
12'b1xxx01xx1011: tran_sel = `TRAN_IF;
|
|
12'b1xxx100xx011,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111011: tran_sel = `TRAN_IO;
|
12'b1xxx10111011: tran_sel = `TRAN_IO;
|
12'b000011100011,
|
12'b000011100011,
|
| Line 1065... |
Line 1099... |
end
|
end
|
`WR1B: begin
|
`WR1B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10111010: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_IO;
|
12'b1xxx10111010: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_IO;
|
|
12'b1xxx1001x011,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111011: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_MEM;
|
12'b1xxx10111011: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_MEM;
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
| Line 1086... |
Line 1121... |
end
|
end
|
`WR2B: begin
|
`WR2B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10111010: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_IO;
|
12'b1xxx10111010: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_IO;
|
|
12'b1xxx1001x011,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111011: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_MEM;
|
12'b1xxx10111011: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_MEM;
|
default: tran_sel = `TRAN_IF;
|
default: tran_sel = `TRAN_IF;
|
| Line 1102... |
Line 1138... |
default: tran_sel = `TRAN_IF;
|
default: tran_sel = `TRAN_IF;
|
endcase
|
endcase
|
end
|
end
|
`PCO: begin
|
`PCO: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b000001110110: tran_sel = `TRAN_IDL;
|
12'b000001110110,
|
|
12'b1xxx01110110: tran_sel = `TRAN_IDL;
|
default: tran_sel = `TRAN_IF;
|
default: tran_sel = `TRAN_IF;
|
endcase
|
endcase
|
end
|
end
|
`IF1B: begin
|
`IF1B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
| Line 1116... |
Line 1153... |
12'b0001xxxxxxxx: tran_sel = `TRAN_IF;
|
12'b0001xxxxxxxx: tran_sel = `TRAN_IF;
|
default: tran_sel = (dmar_reg) ? `TRAN_IDL :
|
default: tran_sel = (dmar_reg) ? `TRAN_IDL :
|
(intr_reg) ? `TRAN_IAK : `TRAN_IF;
|
(intr_reg) ? `TRAN_IAK : `TRAN_IF;
|
endcase
|
endcase
|
end
|
end
|
`HLTB: tran_sel = (xhlt_reg) ? `TRAN_IF : `TRAN_IDL;
|
`HLTB: tran_sel = (xhlt_reg || (page_reg[3] && int_req)) ? `TRAN_IF : `TRAN_IDL;
|
`INTB: tran_sel = (vector_int) ? `TRAN_IDL : `TRAN_MEM;
|
`INTB: tran_sel = (vector_int) ? `TRAN_IDL : `TRAN_MEM;
|
`DMA2: tran_sel = (dmar_reg) ? `TRAN_IDL : `TRAN_IF;
|
`DMA2: tran_sel = (dmar_reg) ? `TRAN_IDL : `TRAN_IF;
|
`RSTE: tran_sel = `TRAN_IF;
|
`RSTE: tran_sel = `TRAN_IF;
|
default: tran_sel = `TRAN_RSTVAL;
|
default: tran_sel = `TRAN_RSTVAL;
|
endcase
|
endcase
|
| Line 1133... |
Line 1170... |
/*****************************************************************************************/
|
/*****************************************************************************************/
|
always @ (inst_reg or page_reg or state_reg or xhlt_reg) begin
|
always @ (inst_reg or page_reg or state_reg or xhlt_reg) begin
|
casex (state_reg)
|
casex (state_reg)
|
`PCO,
|
`PCO,
|
`HLTB: begin
|
`HLTB: begin
|
casex ({page_reg, inst_reg})
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b000001110110: halt_nxt = !xhlt_reg;
|
12'b000001110110: halt_nxt = !xhlt_reg;
|
|
12'b1xxx01110110: halt_nxt = !int_req;
|
default: halt_nxt = 1'b0;
|
default: halt_nxt = 1'b0;
|
endcase
|
endcase
|
end
|
end
|
default: halt_nxt = 1'b0;
|
default: halt_nxt = 1'b0;
|
endcase
|
endcase
|
| Line 1173... |
Line 1211... |
endcase
|
endcase
|
end
|
end
|
`DMA2: output_inh = dmar_reg;
|
`DMA2: output_inh = dmar_reg;
|
`PCO,
|
`PCO,
|
`HLTB: begin
|
`HLTB: begin
|
casex ({page_reg, inst_reg})
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b000001110110: output_inh = !xhlt_reg;
|
12'b000001110110: output_inh = !xhlt_reg;
|
|
12'b1xxx01110110: output_inh = !int_req;
|
default: output_inh = 1'b0;
|
default: output_inh = 1'b0;
|
endcase
|
endcase
|
end
|
end
|
default: output_inh = 1'b0;
|
default: output_inh = 1'b0;
|
endcase
|
endcase
|
| Line 1238... |
Line 1277... |
12'b010011101001,
|
12'b010011101001,
|
12'b010111100101,
|
12'b010111100101,
|
12'b010111101001,
|
12'b010111101001,
|
12'b1xxx01xxx000,
|
12'b1xxx01xxx000,
|
12'b1xxx01xxx001,
|
12'b1xxx01xxx001,
|
|
12'b1xxx100xx011,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100001,
|
12'b1xxx10100001,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
| Line 1265... |
Line 1305... |
12'b001000110110,
|
12'b001000110110,
|
12'b001000111110,
|
12'b001000111110,
|
12'b001001xxx110,
|
12'b001001xxx110,
|
12'b001010xxx110,
|
12'b001010xxx110,
|
12'b001011xxx110,
|
12'b001011xxx110,
|
|
12'b1xxx00110100,
|
12'b1xxx01100111,
|
12'b1xxx01100111,
|
12'b1xxx01101111: add_sel = `ADD_HL;
|
12'b1xxx01101111: add_sel = `ADD_HL;
|
12'b010011100001,
|
12'b010011100001,
|
12'b010011100011,
|
12'b010011100011,
|
12'b010111100001,
|
12'b010111100001,
|
| Line 1292... |
Line 1333... |
12'b000011110100: add_sel = ( !sign_bit) ? `ADD_ALU : `ADD_PC;
|
12'b000011110100: add_sel = ( !sign_bit) ? `ADD_ALU : `ADD_PC;
|
12'b000011111100: add_sel = ( sign_bit) ? `ADD_ALU : `ADD_PC;
|
12'b000011111100: add_sel = ( sign_bit) ? `ADD_ALU : `ADD_PC;
|
default: add_sel = `ADD_PC;
|
default: add_sel = `ADD_PC;
|
endcase
|
endcase
|
end
|
end
|
`IF3A,
|
`IF3A: add_sel = `ADD_ALU;
|
`ADR1,
|
`ADR1: begin
|
`RD1A: add_sel = `ADD_ALU;
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx01110100,
|
|
12'b1xxx00xxx000,
|
|
12'b1xxx00xxx001: add_sel = `ADD_ALU8;
|
|
default: add_sel = `ADD_ALU;
|
|
endcase
|
|
end
|
|
`RD1A: begin
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx100xx011: add_sel = `ADD_ALU8;
|
|
default: add_sel = `ADD_ALU;
|
|
endcase
|
|
end
|
`RD2A: begin
|
`RD2A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b000011100011,
|
12'b000011100011,
|
12'b0001xxxxxxxx,
|
12'b0001xxxxxxxx,
|
12'b010000110100,
|
12'b010000110100,
|
| Line 1323... |
Line 1376... |
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
12'b1xxx10111001,
|
12'b1xxx10111001,
|
12'b1xxx10111010,
|
12'b1xxx10111010,
|
12'b1xxx10111011: add_sel = `ADD_ALU;
|
12'b1xxx10111011: add_sel = `ADD_ALU;
|
|
//12'b1xxx01110100,
|
|
12'b1xxx100xx011: add_sel = `ADD_ALU8;
|
12'b000000110100,
|
12'b000000110100,
|
12'b000000110101,
|
12'b000000110101,
|
12'b000000xxx100,
|
12'b000000xxx100,
|
12'b000000xxx101,
|
12'b000000xxx101,
|
12'b001000000110,
|
12'b001000000110,
|
| Line 1354... |
Line 1409... |
default: add_sel = `ADD_PC;
|
default: add_sel = `ADD_PC;
|
endcase
|
endcase
|
end
|
end
|
`WR1A: begin
|
`WR1A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx1000x011,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
| Line 1369... |
Line 1425... |
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b000011001101,
|
12'b000011001101,
|
12'b000011xxx100,
|
12'b000011xxx100,
|
12'b000011xxx111,
|
12'b000011xxx111,
|
12'b0001xxxxxxxx,
|
12'b0001xxxxxxxx,
|
|
12'b1xxx100xx011,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
| Line 1407... |
Line 1464... |
default: add_sel = `ADD_ALU;
|
default: add_sel = `ADD_ALU;
|
endcase
|
endcase
|
end
|
end
|
`IF1A: add_sel = `ADD_PC;
|
`IF1A: add_sel = `ADD_PC;
|
`INTA: add_sel = (vector_int) ? `ADD_PC : `ADD_ALU;
|
`INTA: add_sel = (vector_int) ? `ADD_PC : `ADD_ALU;
|
|
`HLTA: add_sel = `ADD_PC;
|
`DMA1: add_sel = `ADD_PC;
|
`DMA1: add_sel = `ADD_PC;
|
default: add_sel = `ADD_RSTVAL;
|
default: add_sel = `ADD_RSTVAL;
|
endcase
|
endcase
|
end
|
end
|
|
|
| Line 1524... |
Line 1582... |
12'b010110100110,
|
12'b010110100110,
|
12'b010110101110,
|
12'b010110101110,
|
12'b010110110110,
|
12'b010110110110,
|
12'b010110111110,
|
12'b010110111110,
|
12'b010111101001,
|
12'b010111101001,
|
|
12'b1xxx00xxx000,
|
|
12'b1xxx00xxx001,
|
|
12'b1xxx01100100,
|
|
12'b1xxx01110100,
|
12'b1xxx01000101,
|
12'b1xxx01000101,
|
12'b1xxx01001101,
|
12'b1xxx01001101,
|
12'b1xxx01xx0011,
|
12'b1xxx01xx0011,
|
12'b1xxx01xx1011: pc_sel = `PC_LD;
|
12'b1xxx01xx1011: pc_sel = `PC_LD;
|
12'b010010001100,
|
12'b010010001100,
|
| Line 1595... |
Line 1657... |
12'b010011111001,
|
12'b010011111001,
|
12'b010100100011,
|
12'b010100100011,
|
12'b010100101011,
|
12'b010100101011,
|
12'b010100xx1001,
|
12'b010100xx1001,
|
12'b010111111001,
|
12'b010111111001,
|
|
12'b1xxx000xx100,12'b1xxx0010x100,12'b1xxx00111100,
|
|
12'b1xxx01xx1100,
|
12'b1xxx01000100,
|
12'b1xxx01000100,
|
12'b1xxx01000110,
|
12'b1xxx01000110,
|
12'b1xxx01000111,
|
12'b1xxx01000111,
|
12'b1xxx01001111,
|
12'b1xxx01001111,
|
12'b1xxx01010110,
|
12'b1xxx01010110,
|
| Line 1638... |
Line 1702... |
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b01xx11001011: pc_sel = `PC_LD;
|
12'b01xx11001011: pc_sel = `PC_LD;
|
default: pc_sel = `PC_NUL;
|
default: pc_sel = `PC_NUL;
|
endcase
|
endcase
|
end
|
end
|
`WR2B: begin
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b000011001101,
|
|
12'b000011xxx100,
|
|
12'b000011xxx111,
|
|
12'b0001xxxxxxxx: pc_sel = `PC_LD;
|
|
default: pc_sel = `PC_NUL;
|
|
endcase
|
|
end
|
|
`RD1B,
|
`RD1B,
|
`RD2B: begin
|
`RD2B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx1001x011,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10110001,
|
12'b1xxx10110001,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
| Line 1661... |
Line 1717... |
12'b1xxx10111010,
|
12'b1xxx10111010,
|
12'b1xxx10111011: pc_sel = `PC_INT;
|
12'b1xxx10111011: pc_sel = `PC_INT;
|
default: pc_sel = `PC_NUL;
|
default: pc_sel = `PC_NUL;
|
endcase
|
endcase
|
end
|
end
|
|
`WR2B: begin
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b000011001101,
|
|
12'b000011xxx100,
|
|
12'b000011xxx111,
|
|
12'b0001xxxxxxxx: pc_sel = `PC_LD;
|
|
default: pc_sel = `PC_NUL;
|
|
endcase
|
|
end
|
`PCA: begin
|
`PCA: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b000000010000: pc_sel = (tflg_reg) ? `PC_NUL : `PC_LD;
|
12'b000000010000: pc_sel = (tflg_reg) ? `PC_NUL : `PC_LD;
|
12'b000000011000,
|
12'b000000011000,
|
12'b0000001xx000,
|
12'b0000001xx000,
|
| Line 1680... |
Line 1745... |
`PCO: begin
|
`PCO: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b000011101001,
|
12'b000011101001,
|
12'b010011101001,
|
12'b010011101001,
|
12'b010111101001,
|
12'b010111101001,
|
|
12'b1xxx1001x011,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10110001,
|
12'b1xxx10110001,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
| Line 1696... |
Line 1762... |
`IF1A: begin
|
`IF1A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b1xxx01000101,
|
12'b1xxx01000101,
|
12'b1xxx01001101,
|
12'b1xxx01001101,
|
12'b0001xxxxxxxx: pc_sel = `PC_LD;
|
12'b0001xxxxxxxx: pc_sel = `PC_LD;
|
|
12'b1xxx1001x011,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10110001,
|
12'b1xxx10110001,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
| Line 1803... |
Line 1870... |
12'b010x11100101,
|
12'b010x11100101,
|
12'b000011xxx100,
|
12'b000011xxx100,
|
12'b000011xx0101,
|
12'b000011xx0101,
|
12'b000011xxx111,
|
12'b000011xxx111,
|
12'b0001xxxxxxxx: do_ctl = `DO_MSB;
|
12'b0001xxxxxxxx: do_ctl = `DO_MSB;
|
|
12'b1xxx100xx011,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111011: do_ctl = `DO_IO;
|
12'b1xxx10111011: do_ctl = `DO_IO;
|
default: do_ctl = `DO_LSB;
|
default: do_ctl = `DO_LSB;
|
| Line 1818... |
Line 1886... |
12'b010x00100010,
|
12'b010x00100010,
|
12'b010x11100011,
|
12'b010x11100011,
|
12'b000011100011,
|
12'b000011100011,
|
12'b1xxx01xx0011: do_ctl = `DO_MSB;
|
12'b1xxx01xx0011: do_ctl = `DO_MSB;
|
12'b000011010011,
|
12'b000011010011,
|
12'b1xxx0x0xx001,
|
12'b1xxx0xxxx001,
|
12'b1xxx0x10x001,
|
12'b1xxx100xx011,
|
12'b1xxx0x111001,
|
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111011: do_ctl = `DO_IO;
|
12'b1xxx10111011: do_ctl = `DO_IO;
|
default: do_ctl = `DO_LSB;
|
default: do_ctl = `DO_LSB;
|
| Line 1901... |
Line 1968... |
12'b010010100100,
|
12'b010010100100,
|
12'b010010100101,
|
12'b010010100101,
|
12'b010110100100,
|
12'b010110100100,
|
12'b010110100101,
|
12'b010110100101,
|
12'b001001xxxxxx,
|
12'b001001xxxxxx,
|
12'b001010xxxxxx: aluop_sel = `ALUOP_BAND;
|
12'b001010xxxxxx,
|
|
12'b1xxx00xxx100: aluop_sel = `ALUOP_BAND;
|
12'b010000100101,
|
12'b010000100101,
|
12'b010000101101,
|
12'b010000101101,
|
12'b010100100101,
|
12'b010100100101,
|
12'b010100101101: aluop_sel = `ALUOP_BDEC;
|
12'b010100101101: aluop_sel = `ALUOP_BDEC;
|
12'b010010110100,
|
12'b010010110100,
|
| Line 1928... |
Line 1996... |
12'b1xxx01000100: aluop_sel = `ALUOP_BSUB;
|
12'b1xxx01000100: aluop_sel = `ALUOP_BSUB;
|
12'b010010101100,
|
12'b010010101100,
|
12'b010010101101,
|
12'b010010101101,
|
12'b010110101100,
|
12'b010110101100,
|
12'b010110101101: aluop_sel = `ALUOP_BXOR;
|
12'b010110101101: aluop_sel = `ALUOP_BXOR;
|
|
12'b1xxx01xx1100: aluop_sel = `ALUOP_MLT;
|
12'b001000010xxx: aluop_sel = `ALUOP_RL;
|
12'b001000010xxx: aluop_sel = `ALUOP_RL;
|
12'b001000000xxx: aluop_sel = `ALUOP_RLC;
|
12'b001000000xxx: aluop_sel = `ALUOP_RLC;
|
12'b001000011xxx: aluop_sel = `ALUOP_RR;
|
12'b001000011xxx: aluop_sel = `ALUOP_RR;
|
12'b001000001xxx: aluop_sel = `ALUOP_RRC;
|
12'b001000001xxx: aluop_sel = `ALUOP_RRC;
|
12'b1xxx01xx0010: aluop_sel = `ALUOP_SBC;
|
12'b1xxx01xx0010: aluop_sel = `ALUOP_SBC;
|
| Line 1948... |
Line 2017... |
12'b000000101000: aluop_sel = ( zero_bit) ? `ALUOP_ADS : `ALUOP_ADD;
|
12'b000000101000: aluop_sel = ( zero_bit) ? `ALUOP_ADS : `ALUOP_ADD;
|
12'b000000110000: aluop_sel = (!carry_bit) ? `ALUOP_ADS : `ALUOP_ADD;
|
12'b000000110000: aluop_sel = (!carry_bit) ? `ALUOP_ADS : `ALUOP_ADD;
|
12'b000000111000: aluop_sel = ( carry_bit) ? `ALUOP_ADS : `ALUOP_ADD;
|
12'b000000111000: aluop_sel = ( carry_bit) ? `ALUOP_ADS : `ALUOP_ADD;
|
12'b000000010000,
|
12'b000000010000,
|
12'b000000011000: aluop_sel = `ALUOP_ADS;
|
12'b000000011000: aluop_sel = `ALUOP_ADS;
|
|
12'b1xxx01110100,
|
12'b000000110110: aluop_sel = `ALUOP_PASS;
|
12'b000000110110: aluop_sel = `ALUOP_PASS;
|
default: aluop_sel = `ALUOP_ADD;
|
default: aluop_sel = `ALUOP_ADD;
|
endcase
|
endcase
|
end
|
end
|
`OF2A: begin
|
`OF2A: begin
|
| Line 1986... |
Line 2056... |
endcase
|
endcase
|
end
|
end
|
`IF3A: aluop_sel = `ALUOP_ADS;
|
`IF3A: aluop_sel = `ALUOP_ADS;
|
`ADR1: begin
|
`ADR1: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx00xxx00x,
|
12'b000000100010,
|
12'b000000100010,
|
12'b000000101010,
|
12'b000000101010,
|
12'b000000110010,
|
12'b000000110010,
|
12'b000000111010,
|
12'b000000111010,
|
12'b000011010011,
|
12'b000011010011,
|
| Line 1997... |
Line 2068... |
12'b0001xxxxxxxx,
|
12'b0001xxxxxxxx,
|
12'b010000100010,
|
12'b010000100010,
|
12'b010000101010,
|
12'b010000101010,
|
12'b010100100010,
|
12'b010100100010,
|
12'b010100101010,
|
12'b010100101010,
|
|
12'b1xxx01100100,
|
|
12'b1xxx01110100,
|
12'b1xxx01xx0011,
|
12'b1xxx01xx0011,
|
12'b1xxx01xx1011: aluop_sel = `ALUOP_PASS;
|
12'b1xxx01xx1011: aluop_sel = `ALUOP_PASS;
|
default: aluop_sel = `ALUOP_ADS;
|
default: aluop_sel = `ALUOP_ADS;
|
endcase
|
endcase
|
end
|
end
|
| Line 2012... |
Line 2085... |
12'b1xxx10101001,
|
12'b1xxx10101001,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10110001,
|
12'b1xxx10110001,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
12'b1xxx10111001: aluop_sel = `ALUOP_ADD;
|
12'b1xxx10111001: aluop_sel = `ALUOP_ADD;
|
|
12'b1xxx100xx011,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10111010: aluop_sel = `ALUOP_BADD;
|
12'b1xxx10111010: aluop_sel = `ALUOP_BADD;
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
| Line 2025... |
Line 2099... |
default: aluop_sel = `ALUOP_PASS;
|
default: aluop_sel = `ALUOP_PASS;
|
endcase
|
endcase
|
end
|
end
|
`RD1A: begin
|
`RD1A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx100xx011,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
| Line 2046... |
Line 2121... |
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b1xxx10100001,
|
12'b1xxx10100001,
|
12'b1xxx10101001,
|
12'b1xxx10101001,
|
12'b1xxx10110001,
|
12'b1xxx10110001,
|
12'b1xxx10111001: aluop_sel = `ALUOP_BSUB;
|
12'b1xxx10111001: aluop_sel = `ALUOP_BSUB;
|
|
12'b1xxx100xx011,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10111000: aluop_sel = `ALUOP_PASS;
|
12'b1xxx10111000: aluop_sel = `ALUOP_PASS;
|
default: aluop_sel = `ALUOP_BAND;
|
default: aluop_sel = `ALUOP_BAND;
|
| Line 2071... |
Line 2147... |
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
12'b1xxx10111010: aluop_sel = `ALUOP_ADD;
|
12'b1xxx10111010: aluop_sel = `ALUOP_ADD;
|
|
12'b1xxx100xx011: aluop_sel = `ALUOP_BADD;
|
default: aluop_sel = `ALUOP_PASS;
|
default: aluop_sel = `ALUOP_PASS;
|
endcase
|
endcase
|
end
|
end
|
`RD2B: begin
|
`RD2B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
| Line 2104... |
Line 2181... |
12'b0001xxxxxxxx,
|
12'b0001xxxxxxxx,
|
12'b010011100011,
|
12'b010011100011,
|
12'b010111100011,
|
12'b010111100011,
|
12'b1xxx01000101,
|
12'b1xxx01000101,
|
12'b1xxx01001101,
|
12'b1xxx01001101,
|
|
//12'b1xxx01110100,
|
|
12'b1xxx100xx011,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10111000: aluop_sel = `ALUOP_PASS;
|
12'b1xxx10111000: aluop_sel = `ALUOP_PASS;
|
12'b0x1x00000xxx: aluop_sel = `ALUOP_RLC;
|
12'b0x1x00000xxx: aluop_sel = `ALUOP_RLC;
|
| Line 2140... |
Line 2219... |
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10111000: aluop_sel = `ALUOP_ADD;
|
12'b1xxx10111000: aluop_sel = `ALUOP_ADD;
|
|
12'b1xxx100xx011,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111010,
|
12'b1xxx10111010,
|
12'b1xxx10111011: aluop_sel = `ALUOP_BADD;
|
12'b1xxx10111011: aluop_sel = `ALUOP_BADD;
|
default: aluop_sel = `ALUOP_PASS;
|
default: aluop_sel = `ALUOP_PASS;
|
endcase
|
endcase
|
end
|
end
|
`WR2A: begin
|
`WR2A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx100xx011,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
| Line 2164... |
Line 2245... |
default: aluop_sel = `ALUOP_PASS;
|
default: aluop_sel = `ALUOP_PASS;
|
endcase
|
endcase
|
end
|
end
|
`WR2B: begin
|
`WR2B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx100xx011,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
| Line 2191... |
Line 2273... |
12'b000011001110,
|
12'b000011001110,
|
12'b010x10001110: aluop_sel = `ALUOP_BADC;
|
12'b010x10001110: aluop_sel = `ALUOP_BADC;
|
12'b000010000xxx,
|
12'b000010000xxx,
|
12'b000011000110,
|
12'b000011000110,
|
12'b010x10000110,
|
12'b010x10000110,
|
|
12'b1xxx100xx011,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111011: aluop_sel = `ALUOP_BADD;
|
12'b1xxx10111011: aluop_sel = `ALUOP_BADD;
|
12'b000010100xxx,
|
12'b000010100xxx,
|
12'b0x1x01xxxxxx,
|
12'b0x1x01xxxxxx,
|
12'b010x10100110,
|
12'b010x10100110,
|
12'b000011100110,
|
12'b000011100110,
|
|
12'b1xxx00110100,
|
|
12'b1xxx00xxx000,
|
|
12'b1xxx011x0100,
|
12'b1xxx01xxx000: aluop_sel = `ALUOP_BAND;
|
12'b1xxx01xxx000: aluop_sel = `ALUOP_BAND;
|
12'b000010110xxx,
|
12'b000010110xxx,
|
12'b010x10110110,
|
12'b010x10110110,
|
12'b000011110110: aluop_sel = `ALUOP_BOR;
|
12'b000011110110: aluop_sel = `ALUOP_BOR;
|
12'b000010011xxx,
|
12'b000010011xxx,
|
| Line 2316... |
Line 2402... |
endcase
|
endcase
|
end
|
end
|
`RD2A: begin
|
`RD2A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b0001xxxxxxxx,
|
12'b0001xxxxxxxx,
|
|
12'b1xxx100x1011,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
12'b1xxx10111010: alua_sel = `ALUA_M1;
|
12'b1xxx10111010: alua_sel = `ALUA_M1;
|
default: alua_sel = `ALUA_ONE;
|
default: alua_sel = `ALUA_ONE;
|
| Line 2355... |
Line 2442... |
12'b010000100010,
|
12'b010000100010,
|
12'b010011100011,
|
12'b010011100011,
|
12'b010100100010,
|
12'b010100100010,
|
12'b010111100011,
|
12'b010111100011,
|
12'b1xxx01xx0011,
|
12'b1xxx01xx0011,
|
|
12'b1xxx100x0011,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10110011: alua_sel = `ALUA_ONE;
|
12'b1xxx10110011: alua_sel = `ALUA_ONE;
|
default: alua_sel = `ALUA_M1;
|
default: alua_sel = `ALUA_M1;
|
endcase
|
endcase
|
end
|
end
|
`WR1B: begin
|
`WR1B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx1001x011,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
12'b1xxx10111010,
|
12'b1xxx10111010,
|
| Line 2376... |
Line 2465... |
endcase
|
endcase
|
end
|
end
|
`WR2A: begin
|
`WR2A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b0001xxxxxxxx: alua_sel = `ALUA_INT;
|
12'b0001xxxxxxxx: alua_sel = `ALUA_INT;
|
|
12'b1xxx100x1011,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
12'b1xxx10111011: alua_sel = `ALUA_M1;
|
12'b1xxx10111011: alua_sel = `ALUA_M1;
|
12'b000011xxx111: alua_sel = `ALUA_RST;
|
12'b000011xxx111: alua_sel = `ALUA_RST;
|
default: alua_sel = `ALUA_ONE;
|
default: alua_sel = `ALUA_ONE;
|
endcase
|
endcase
|
end
|
end
|
`WR2B: begin
|
`WR2B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx100xx011,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
| Line 2411... |
Line 2502... |
end
|
end
|
`PCA: alua_sel = (tflg_reg) ? `ALUA_ZER : `ALUA_M2;
|
`PCA: alua_sel = (tflg_reg) ? `ALUA_ZER : `ALUA_M2;
|
`IF1A: begin
|
`IF1A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b0x1x01xxxxxx: alua_sel = `ALUA_BIT;
|
12'b0x1x01xxxxxx: alua_sel = `ALUA_BIT;
|
|
12'b1xxx00xxx000,
|
12'b1xxx01xxx000,
|
12'b1xxx01xxx000,
|
|
12'b1xxx100x1011,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
12'b1xxx10111010,
|
12'b1xxx10111010,
|
12'b1xxx10111011: alua_sel = `ALUA_M1;
|
12'b1xxx10111011: alua_sel = `ALUA_M1;
|
|
12'b1xxx100x0011,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10110010: alua_sel = `ALUA_ONE;
|
12'b1xxx10110010: alua_sel = `ALUA_ONE;
|
|
12'b1xxx01110100: alua_sel = `ALUA_TMP;
|
default: alua_sel = `ALUA_AA;
|
default: alua_sel = `ALUA_AA;
|
endcase
|
endcase
|
end
|
end
|
`INTA: alua_sel = `ALUA_M1;
|
`INTA: alua_sel = `ALUA_M1;
|
default: alua_sel = `ALUA_ONE;
|
default: alua_sel = `ALUA_ONE;
|
| Line 2561... |
Line 2656... |
12'b010111101001,
|
12'b010111101001,
|
12'b010111111001: alub_sel = `ALUB_IY;
|
12'b010111111001: alub_sel = `ALUB_IY;
|
12'b1xxx01000101,
|
12'b1xxx01000101,
|
12'b1xxx01001101: alub_sel = `ALUB_PC;
|
12'b1xxx01001101: alub_sel = `ALUB_PC;
|
12'b010x0110x000,
|
12'b010x0110x000,
|
|
12'b1xxx00000100,
|
12'b0010xxxxx000: alub_sel = `ALUB_BB;
|
12'b0010xxxxx000: alub_sel = `ALUB_BB;
|
12'b010x0110x001,
|
12'b010x0110x001,
|
|
12'b1xxx00001100,
|
12'b0010xxxxx001: alub_sel = `ALUB_CC;
|
12'b0010xxxxx001: alub_sel = `ALUB_CC;
|
12'b010x0110x010,
|
12'b010x0110x010,
|
|
12'b1xxx00010100,
|
12'b0010xxxxx010: alub_sel = `ALUB_DD;
|
12'b0010xxxxx010: alub_sel = `ALUB_DD;
|
12'b010x0110x011,
|
12'b010x0110x011,
|
|
12'b1xxx00011100,
|
12'b0010xxxxx011: alub_sel = `ALUB_EE;
|
12'b0010xxxxx011: alub_sel = `ALUB_EE;
|
|
12'b1xxx00100100,
|
12'b0010xxxxx100: alub_sel = `ALUB_HH;
|
12'b0010xxxxx100: alub_sel = `ALUB_HH;
|
|
12'b1xxx00101100,
|
12'b0010xxxxx101: alub_sel = `ALUB_LL;
|
12'b0010xxxxx101: alub_sel = `ALUB_LL;
|
12'b010x0110x111,
|
12'b010x0110x111,
|
|
12'b1xxx00111100,
|
12'b0010xxxxx111: alub_sel = `ALUB_AA;
|
12'b0010xxxxx111: alub_sel = `ALUB_AA;
|
|
12'b1xxx01001100,
|
12'b1xxx0100x010: alub_sel = `ALUB_BC;
|
12'b1xxx0100x010: alub_sel = `ALUB_BC;
|
|
12'b1xxx01011100,
|
12'b1xxx0101x010: alub_sel = `ALUB_DE;
|
12'b1xxx0101x010: alub_sel = `ALUB_DE;
|
|
12'b1xxx01111100,
|
12'b1xxx0111x010: alub_sel = `ALUB_SP;
|
12'b1xxx0111x010: alub_sel = `ALUB_SP;
|
12'b010011100101,
|
12'b010011100101,
|
12'b010111100101: alub_sel = `ALUB_SP;
|
12'b010111100101: alub_sel = `ALUB_SP;
|
12'b010x00001001: alub_sel = `ALUB_BC;
|
12'b010x00001001: alub_sel = `ALUB_BC;
|
12'b010x00011001: alub_sel = `ALUB_DE;
|
12'b010x00011001: alub_sel = `ALUB_DE;
|
| Line 2587... |
Line 2692... |
default: alub_sel = `ALUB_HL;
|
default: alub_sel = `ALUB_HL;
|
endcase
|
endcase
|
end
|
end
|
`OF1B: begin
|
`OF1B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx01110100,
|
12'b000000010000,
|
12'b000000010000,
|
12'b000000011000,
|
12'b000000011000,
|
12'b000000110110: alub_sel = `ALUB_DIN;
|
12'b000000110110: alub_sel = `ALUB_DIN;
|
12'b000000100000: alub_sel = ( !zero_bit) ? `ALUB_DIN : `ALUB_PC;
|
12'b000000100000: alub_sel = ( !zero_bit) ? `ALUB_DIN : `ALUB_PC;
|
12'b000000101000: alub_sel = ( zero_bit) ? `ALUB_DIN : `ALUB_PC;
|
12'b000000101000: alub_sel = ( zero_bit) ? `ALUB_DIN : `ALUB_PC;
|
| Line 2632... |
Line 2738... |
endcase
|
endcase
|
end
|
end
|
`IF3A: alub_sel = `ALUB_DIN;
|
`IF3A: alub_sel = `ALUB_DIN;
|
`ADR1: begin
|
`ADR1: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx01110100: alub_sel = `ALUB_CC;
|
12'b000011010011,
|
12'b000011010011,
|
12'b000011011011: alub_sel = `ALUB_IO;
|
12'b000011011011: alub_sel = `ALUB_IO;
|
12'b0001xxxxxxxx: alub_sel = `ALUB_TMP;
|
12'b0001xxxxxxxx: alub_sel = `ALUB_TMP;
|
default: alub_sel = `ALUB_DIN;
|
default: alub_sel = `ALUB_DIN;
|
endcase
|
endcase
|
| Line 2644... |
Line 2751... |
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b000000000010,
|
12'b000000000010,
|
12'b000000010010,
|
12'b000000010010,
|
12'b000000110010,
|
12'b000000110010,
|
12'b000011010011: alub_sel = `ALUB_AA;
|
12'b000011010011: alub_sel = `ALUB_AA;
|
|
12'b1xxx100xx011,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
| Line 2667... |
Line 2775... |
12'b010100100010: alub_sel = `ALUB_IY;
|
12'b010100100010: alub_sel = `ALUB_IY;
|
12'b010111100101: alub_sel = `ALUB_IYH;
|
12'b010111100101: alub_sel = `ALUB_IYH;
|
12'b000011xxx111: alub_sel = `ALUB_PCH;
|
12'b000011xxx111: alub_sel = `ALUB_PCH;
|
12'b000001xxx000,
|
12'b000001xxx000,
|
12'b010x01110000,
|
12'b010x01110000,
|
|
12'b1xxx00000001,
|
12'b1xxx01000001: alub_sel = `ALUB_BB;
|
12'b1xxx01000001: alub_sel = `ALUB_BB;
|
12'b000001xxx001,
|
12'b000001xxx001,
|
12'b010x01110001,
|
12'b010x01110001,
|
|
12'b1xxx01110100,
|
|
12'b1xxx00001001,
|
12'b1xxx01001001: alub_sel = `ALUB_CC;
|
12'b1xxx01001001: alub_sel = `ALUB_CC;
|
12'b000001xxx010,
|
12'b000001xxx010,
|
12'b010x01110010,
|
12'b010x01110010,
|
|
12'b1xxx00010001,
|
12'b1xxx01010001: alub_sel = `ALUB_DD;
|
12'b1xxx01010001: alub_sel = `ALUB_DD;
|
12'b000001xxx011,
|
12'b000001xxx011,
|
12'b010x01110011,
|
12'b010x01110011,
|
|
12'b1xxx00011001,
|
12'b1xxx01011001: alub_sel = `ALUB_EE;
|
12'b1xxx01011001: alub_sel = `ALUB_EE;
|
12'b000001xxx100,
|
12'b000001xxx100,
|
12'b010x01110100,
|
12'b010x01110100,
|
|
12'b1xxx00100001,
|
12'b1xxx01100001: alub_sel = `ALUB_HH;
|
12'b1xxx01100001: alub_sel = `ALUB_HH;
|
12'b000001xxx101,
|
12'b000001xxx101,
|
12'b010x01110101,
|
12'b010x01110101,
|
|
12'b1xxx00101001,
|
12'b1xxx01101001: alub_sel = `ALUB_LL;
|
12'b1xxx01101001: alub_sel = `ALUB_LL;
|
12'b000001xxx111,
|
12'b000001xxx111,
|
12'b010x01110111,
|
12'b010x01110111,
|
|
12'b1xxx00111001,
|
12'b1xxx01111001: alub_sel = `ALUB_AA;
|
12'b1xxx01111001: alub_sel = `ALUB_AA;
|
12'b1xxx01000011: alub_sel = `ALUB_BC;
|
12'b1xxx01000011: alub_sel = `ALUB_BC;
|
12'b1xxx01010011: alub_sel = `ALUB_DE;
|
12'b1xxx01010011: alub_sel = `ALUB_DE;
|
12'b1xxx01110011: alub_sel = `ALUB_SP;
|
12'b1xxx01110011: alub_sel = `ALUB_SP;
|
12'b000011000101: alub_sel = `ALUB_BB;
|
12'b000011000101: alub_sel = `ALUB_BB;
|
| Line 2702... |
Line 2818... |
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111011: alub_sel = `ALUB_BC;
|
12'b1xxx10111011: alub_sel = `ALUB_BC;
|
|
12'b1xxx100xx011: alub_sel = `ALUB_CC;
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10111000: alub_sel = `ALUB_DE;
|
12'b1xxx10111000: alub_sel = `ALUB_DE;
|
12'b1xxx10100001,
|
12'b1xxx10100001,
|
| Line 2729... |
Line 2846... |
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111011: alub_sel = `ALUB_BC;
|
12'b1xxx10111011: alub_sel = `ALUB_BC;
|
|
12'b1xxx01110100,
|
|
12'b1xxx100xx011: alub_sel = `ALUB_CC;
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10111000: alub_sel = `ALUB_DE;
|
12'b1xxx10111000: alub_sel = `ALUB_DE;
|
12'b001010xxxxxx,
|
12'b001010xxxxxx,
|
| Line 2802... |
Line 2921... |
12'b010110110110,
|
12'b010110110110,
|
12'b010110111110,
|
12'b010110111110,
|
12'b010111100001,
|
12'b010111100001,
|
12'b011001xxx110,
|
12'b011001xxx110,
|
12'b011101xxx110,
|
12'b011101xxx110,
|
|
12'b1xxx00xxx000,
|
|
12'b1xxx00xxx100,
|
12'b1xxx01xxx000,
|
12'b1xxx01xxx000,
|
|
12'b1xxx01xxx100,
|
12'b1xxx01xx1011: alub_sel = `ALUB_PC;
|
12'b1xxx01xx1011: alub_sel = `ALUB_PC;
|
12'b0001xxxxxxxx: alub_sel = `ALUB_PCH;
|
12'b0001xxxxxxxx: alub_sel = `ALUB_PCH;
|
default: alub_sel = `ALUB_DIN;
|
default: alub_sel = `ALUB_DIN;
|
endcase
|
endcase
|
end
|
end
|
| Line 2814... |
Line 2936... |
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10111010: alub_sel = `ALUB_BC;
|
12'b1xxx10111010: alub_sel = `ALUB_BC;
|
|
12'b1xxx100xx011,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
| Line 2831... |
Line 2954... |
default: alub_sel = `ALUB_SP;
|
default: alub_sel = `ALUB_SP;
|
endcase
|
endcase
|
end
|
end
|
`WR1B: begin
|
`WR1B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx1001x011,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111010,
|
12'b1xxx10111010,
|
12'b1xxx10111011: alub_sel = `ALUB_BB;
|
12'b1xxx10111011: alub_sel = `ALUB_BB;
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
| Line 2869... |
Line 2993... |
default: alub_sel = `ALUB_HL;
|
default: alub_sel = `ALUB_HL;
|
endcase
|
endcase
|
end
|
end
|
`WR2B: begin
|
`WR2B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx100xx011,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
| Line 2894... |
Line 3019... |
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111011: alub_sel = `ALUB_BB;
|
12'b1xxx10111011: alub_sel = `ALUB_BB;
|
|
12'b1xxx100xx011: alub_sel = `ALUB_CC;
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10111000: alub_sel = `ALUB_DE;
|
12'b1xxx10111000: alub_sel = `ALUB_DE;
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
| Line 2940... |
Line 3066... |
12'b000011111100: wr_addr = ( sign_bit) ? `WREG_SP : `WREG_NUL;
|
12'b000011111100: wr_addr = ( sign_bit) ? `WREG_SP : `WREG_NUL;
|
default: wr_addr = `WREG_NUL;
|
default: wr_addr = `WREG_NUL;
|
endcase
|
endcase
|
end
|
end
|
`IF3B: wr_addr = `WREG_TMP;
|
`IF3B: wr_addr = `WREG_TMP;
|
|
`ADR1: begin
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx01110100: wr_addr = `WREG_TMP;
|
|
default: wr_addr = `WREG_NUL;
|
|
endcase
|
|
end
|
`ADR2: begin
|
`ADR2: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b000011xxx111,
|
12'b000011xxx111,
|
12'b000011xx0101,
|
12'b000011xx0101,
|
12'b010011100101,
|
12'b010011100101,
|
| Line 2963... |
Line 3095... |
default: wr_addr = `WREG_NUL;
|
default: wr_addr = `WREG_NUL;
|
endcase
|
endcase
|
end
|
end
|
`RD1A: begin
|
`RD1A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx100xx011,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
| Line 2996... |
Line 3129... |
default: wr_addr = `WREG_NUL;
|
default: wr_addr = `WREG_NUL;
|
endcase
|
endcase
|
end
|
end
|
`RD2A: begin
|
`RD2A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx100xx011,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
| Line 3017... |
Line 3151... |
default: wr_addr = `WREG_NUL;
|
default: wr_addr = `WREG_NUL;
|
endcase
|
endcase
|
end
|
end
|
`RD2B: begin
|
`RD2B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx100xx011: wr_addr = `WREG_CC;
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10111000: wr_addr = `WREG_DE;
|
12'b1xxx10111000: wr_addr = `WREG_DE;
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
| Line 3038... |
Line 3173... |
default: wr_addr = `WREG_NUL;
|
default: wr_addr = `WREG_NUL;
|
endcase
|
endcase
|
end
|
end
|
`WR1B: begin
|
`WR1B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx100xx011,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
| Line 3058... |
Line 3194... |
default: wr_addr = `WREG_NUL;
|
default: wr_addr = `WREG_NUL;
|
endcase
|
endcase
|
end
|
end
|
`WR2B: begin
|
`WR2B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx100xx011,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
| Line 3179... |
Line 3316... |
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111011: wr_addr = `WREG_BB;
|
12'b1xxx10111011: wr_addr = `WREG_BB;
|
12'b000000000001,
|
12'b000000000001,
|
12'b00000000x011,
|
12'b00000000x011,
|
12'b000011000001,
|
12'b000011000001,
|
|
12'b1xxx01001100,
|
12'b1xxx01001011: wr_addr = `WREG_BC;
|
12'b1xxx01001011: wr_addr = `WREG_BC;
|
12'b00000000110x,
|
12'b00000000110x,
|
12'b000000001110,
|
12'b000000001110,
|
12'b000001001xxx,
|
12'b000001001xxx,
|
12'b001000xxx001,
|
12'b001000xxx001,
|
12'b00101xxxx001,
|
12'b00101xxxx001,
|
//12'b011x00xxx001,
|
//12'b011x00xxx001,
|
//12'b011x1xxxx001,
|
//12'b011x1xxxx001,
|
12'b010x0100110x,
|
12'b010x0100110x,
|
12'b010x01001110,
|
12'b010x01001110,
|
|
12'b1xxx100xx011,
|
12'b1xxx0x001000: wr_addr = `WREG_CC;
|
12'b1xxx0x001000: wr_addr = `WREG_CC;
|
12'b00000001010x,
|
12'b00000001010x,
|
12'b000000010110,
|
12'b000000010110,
|
12'b000001010xxx,
|
12'b000001010xxx,
|
12'b001000xxx010,
|
12'b001000xxx010,
|
| Line 3203... |
Line 3342... |
12'b010x01010110,
|
12'b010x01010110,
|
12'b1xxx0x010000: wr_addr = `WREG_DD;
|
12'b1xxx0x010000: wr_addr = `WREG_DD;
|
12'b000011010001,
|
12'b000011010001,
|
12'b00000001x011,
|
12'b00000001x011,
|
12'b000000010001,
|
12'b000000010001,
|
|
12'b1xxx01011100,
|
12'b1xxx01011011,
|
12'b1xxx01011011,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10111000: wr_addr = `WREG_DE;
|
12'b1xxx10111000: wr_addr = `WREG_DE;
|
| Line 3234... |
Line 3374... |
12'b000000101010,
|
12'b000000101010,
|
12'b00000010x011,
|
12'b00000010x011,
|
12'b000000xx1001,
|
12'b000000xx1001,
|
12'b000011100001,
|
12'b000011100001,
|
12'b000011100011,
|
12'b000011100011,
|
|
12'b1xxx01101100,
|
12'b1xxx01101011,
|
12'b1xxx01101011,
|
12'b1xxx01xx0010,
|
12'b1xxx01xx0010,
|
12'b1xxx01xx1010,
|
12'b1xxx01xx1010,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
| Line 3294... |
Line 3435... |
12'b1xxx01001111: wr_addr = `WREG_RR;
|
12'b1xxx01001111: wr_addr = `WREG_RR;
|
12'b000000110001,
|
12'b000000110001,
|
12'b00000011x011,
|
12'b00000011x011,
|
12'b000011111001,
|
12'b000011111001,
|
12'b010x11111001,
|
12'b010x11111001,
|
|
12'b1xxx01111100,
|
12'b1xxx01111011: wr_addr = `WREG_SP;
|
12'b1xxx01111011: wr_addr = `WREG_SP;
|
default: wr_addr = `WREG_NUL;
|
default: wr_addr = `WREG_NUL;
|
endcase
|
endcase
|
end
|
end
|
`INTB: wr_addr = (vector_int) ? `WREG_TMP : `WREG_SP;
|
`INTB: wr_addr = (vector_int) ? `WREG_TMP : `WREG_SP;
|
| Line 3420... |
Line 3562... |
12'b010110110101,
|
12'b010110110101,
|
12'b010110110110,
|
12'b010110110110,
|
12'b010110111100,
|
12'b010110111100,
|
12'b010110111101,
|
12'b010110111101,
|
12'b010110111110,
|
12'b010110111110,
|
|
12'b1xxx00110100,
|
|
12'b1xxx00xxxx00,
|
|
12'b1xxx011x0100,
|
12'b1xxx01000100,
|
12'b1xxx01000100,
|
12'b1xxx01010111,
|
12'b1xxx01010111,
|
12'b1xxx01011111,
|
12'b1xxx01011111,
|
12'b1xxx01100111,
|
12'b1xxx01100111,
|
12'b1xxx01101111,
|
12'b1xxx01101111,
|
| Line 3445... |
Line 3590... |
always @ (inst_reg or page_reg or state_reg) begin
|
always @ (inst_reg or page_reg or state_reg) begin
|
casex (state_reg) //synopsys parallel_case
|
casex (state_reg) //synopsys parallel_case
|
`RD1A,
|
`RD1A,
|
`RD2A: begin
|
`RD2A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx100xx011,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
| Line 3568... |
Line 3714... |
12'b010110111100,
|
12'b010110111100,
|
12'b010110111101,
|
12'b010110111101,
|
12'b010110111110,
|
12'b010110111110,
|
12'b011001xxx110,
|
12'b011001xxx110,
|
12'b011101xxx110,
|
12'b011101xxx110,
|
|
12'b1xxx00xxxx00,
|
12'b1xxx01000100,
|
12'b1xxx01000100,
|
12'b1xxx01010111,
|
12'b1xxx01010111,
|
12'b1xxx01011111,
|
12'b1xxx01011111,
|
12'b1xxx01100111,
|
12'b1xxx01100111,
|
12'b1xxx01101111,
|
12'b1xxx01101111,
|
|
12'b1xxx011x0100,
|
12'b1xxx01xxx000,
|
12'b1xxx01xxx000,
|
12'b1xxx01xx0010,
|
12'b1xxx01xx0010,
|
12'b1xxx01xx1010,
|
12'b1xxx01xx1010,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
| Line 3649... |
Line 3797... |
12'b010110101101,
|
12'b010110101101,
|
12'b010110101110,
|
12'b010110101110,
|
12'b010110110100,
|
12'b010110110100,
|
12'b010110110101,
|
12'b010110110101,
|
12'b010110110110,
|
12'b010110110110,
|
|
12'b1xxx00xxx000,
|
12'b1xxx01010111,
|
12'b1xxx01010111,
|
12'b1xxx01011111,
|
12'b1xxx01011111,
|
12'b1xxx01xxx000,
|
12'b1xxx01xxx000,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
| Line 3669... |
Line 3818... |
12'b010010100110,
|
12'b010010100110,
|
12'b010110100100,
|
12'b010110100100,
|
12'b010110100101,
|
12'b010110100101,
|
12'b010110100110,
|
12'b010110100110,
|
12'b011001xxx110,
|
12'b011001xxx110,
|
12'b011101xxx110: hflg_ctl = `HFLG_1;
|
12'b011101xxx110,
|
|
12'b1xxx00xxx100,
|
|
12'b1xxx011x0100: hflg_ctl = `HFLG_1;
|
12'b000000111111,
|
12'b000000111111,
|
12'b000000100111,
|
12'b000000100111,
|
12'b0000000xx100,12'b00000010x100,12'b000000111100,
|
12'b0000000xx100,12'b00000010x100,12'b000000111100,
|
12'b0000000xx101,12'b00000010x101,12'b000000111101,
|
12'b0000000xx101,12'b00000010x101,12'b000000111101,
|
12'b000000xx1001,
|
12'b000000xx1001,
|
| Line 3807... |
Line 3958... |
12'b010110101101,
|
12'b010110101101,
|
12'b010110101110,
|
12'b010110101110,
|
12'b010110110100,
|
12'b010110110100,
|
12'b010110110101,
|
12'b010110110101,
|
12'b010110110110,
|
12'b010110110110,
|
|
12'b1xxx00xxxx00,
|
|
12'b1xxx00110100,
|
|
12'b1xxx011x0100,
|
12'b1xxx01100111,
|
12'b1xxx01100111,
|
12'b1xxx01101111,
|
12'b1xxx01101111,
|
12'b1xxx01xxx000: pflg_ctl = `PFLG_P;
|
12'b1xxx01xxx000: pflg_ctl = `PFLG_P;
|
12'b0000000xx100,12'b00000010x100,12'b000000111100,
|
12'b0000000xx100,12'b00000010x100,12'b000000111100,
|
12'b0000000xx101,12'b00000010x101,12'b000000111101,
|
12'b0000000xx101,12'b00000010x101,12'b000000111101,
|
| Line 3962... |
Line 4116... |
12'b010110110100,
|
12'b010110110100,
|
12'b010110110101,
|
12'b010110110101,
|
12'b010110110110,
|
12'b010110110110,
|
12'b00100xxxxxxx,
|
12'b00100xxxxxxx,
|
12'b011x0xxxxxxx,
|
12'b011x0xxxxxxx,
|
|
12'b1xxx00xxxx00,
|
|
12'b1xxx00110100,
|
|
12'b1xxx011x0100,
|
12'b1xxx01010111,
|
12'b1xxx01010111,
|
12'b1xxx01011111,
|
12'b1xxx01011111,
|
12'b1xxx01100111,
|
12'b1xxx01100111,
|
12'b1xxx01101111,
|
12'b1xxx01101111,
|
12'b1xxx01xxx000,
|
12'b1xxx01xxx000,
|
| Line 4010... |
Line 4167... |
12'b010110111100,
|
12'b010110111100,
|
12'b010110111101,
|
12'b010110111101,
|
12'b010110111110,
|
12'b010110111110,
|
12'b1xxx01000100,
|
12'b1xxx01000100,
|
12'b1xxx01xx0010,
|
12'b1xxx01xx0010,
|
|
12'b1xxx100xx011,
|
12'b1xxx10100001,
|
12'b1xxx10100001,
|
12'b1xxx10101001,
|
12'b1xxx10101001,
|
12'b1xxx10110001,
|
12'b1xxx10110001,
|
12'b1xxx10111001: nflg_ctl = `NFLG_1;
|
12'b1xxx10111001: nflg_ctl = `NFLG_1;
|
default: nflg_ctl = `NFLG_NUL;
|
default: nflg_ctl = `NFLG_NUL;
|
| Line 4120... |
Line 4278... |
12'b010110011101,
|
12'b010110011101,
|
12'b010110011110,
|
12'b010110011110,
|
12'b010110111100,
|
12'b010110111100,
|
12'b010110111101,
|
12'b010110111101,
|
12'b010110111110,
|
12'b010110111110,
|
|
12'b1xxx00xxxx00,
|
|
12'b1xxx00110100,
|
|
12'b1xxx011x0100,
|
12'b1xxx01000100,
|
12'b1xxx01000100,
|
12'b1xxx01xx0010,
|
12'b1xxx01xx0010,
|
12'b1xxx01xx1010: cflg_en = 1'b1;
|
12'b1xxx01xx1010: cflg_en = 1'b1;
|
default: cflg_en = 1'b0;
|
default: cflg_en = 1'b0;
|
endcase
|
endcase
|
