URL
https://opencores.org/ocsvn/graphicsaccelerator/graphicsaccelerator/trunk
Subversion Repositories graphicsaccelerator
[/] [graphicsaccelerator/] [trunk/] [xst/] [work/] [hdpdeps.ref] - Rev 2
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V3 31FL /home/omar/LineFPGA/Bresenhamer.vhd 2011/05/17.19:21:10 O.40dEN work/Bresenhamer 1305649285 FL /home/omar/LineFPGA/Bresenhamer.vhd \PB ieee/std_logic_1164 1296775758 PB ieee/NUMERIC_STD 1296775759 \PB ieee/STD_LOGIC_UNSIGNED 1296775760AR work/Bresenhamer/Behavioral 1305649286 \FL /home/omar/LineFPGA/Bresenhamer.vhd EN work/Bresenhamer 1305649285FL /home/omar/LineFPGA/Debouncer.vhd 2011/05/13.23:51:58 O.40dEN work/Debouncer 1305649283 FL /home/omar/LineFPGA/Debouncer.vhd \PB ieee/std_logic_1164 1296775758 PB ieee/NUMERIC_STD 1296775759 \PB ieee/STD_LOGIC_UNSIGNED 1296775760AR work/Debouncer/Behavioral 1305649284 \FL /home/omar/LineFPGA/Debouncer.vhd EN work/Debouncer 1305649283FL /home/omar/LineFPGA/FrameBuffer2.vhd 2011/05/16.10:41:42 O.40dEN work/FrameBuffer 1305649279 FL /home/omar/LineFPGA/FrameBuffer2.vhd \PB ieee/std_logic_1164 1296775758 PB ieee/NUMERIC_STD 1296775759 \PB ieee/STD_LOGIC_UNSIGNED 1296775760 PB ieee/std_logic_arith 1296775759AR work/FrameBuffer/Behavioral 1305649280 \FL /home/omar/LineFPGA/FrameBuffer2.vhd EN work/FrameBuffer 1305649279FL /home/omar/LineFPGA/FreqDiv.vhd 2011/05/14.11:25:43 O.40dEN work/FreqDiv 1305649291 FL /home/omar/LineFPGA/FreqDiv.vhd \PB ieee/std_logic_1164 1296775758 PB ieee/NUMERIC_STD 1296775759 \PB ieee/STD_LOGIC_UNSIGNED 1296775760AR work/FreqDiv/Behavioral 1305649292 \FL /home/omar/LineFPGA/FreqDiv.vhd EN work/FreqDiv 1305649291FL /home/omar/LineFPGA/Pointer.vhd 2011/05/14.11:27:10 O.40dEN work/Pointer 1305649289 FL /home/omar/LineFPGA/Pointer.vhd \PB ieee/std_logic_1164 1296775758 PB ieee/NUMERIC_STD 1296775759 \PB ieee/STD_LOGIC_UNSIGNED 1296775760AR work/Pointer/Behavioral 1305649290 \FL /home/omar/LineFPGA/Pointer.vhd EN work/Pointer 1305649289FL /home/omar/LineFPGA/SevenSegment.vhd 2011/05/13.21:52:07 O.40dEN work/SevenSegment 1305649287 FL /home/omar/LineFPGA/SevenSegment.vhd \PB ieee/std_logic_1164 1296775758 PB ieee/NUMERIC_STD 1296775759 \PB ieee/STD_LOGIC_UNSIGNED 1296775760AR work/SevenSegment/Behavioral 1305649288 \FL /home/omar/LineFPGA/SevenSegment.vhd EN work/SevenSegment 1305649287FL /home/omar/LineFPGA/Synchronizer.vhd 2010/12/08.00:33:42 O.40dEN work/Synchronizer 1305649281 FL /home/omar/LineFPGA/Synchronizer.vhd \PB ieee/std_logic_1164 1296775758 PB ieee/NUMERIC_STD 1296775759 \PB ieee/STD_LOGIC_UNSIGNED 1296775760AR work/Synchronizer/Behavioral 1305649282 \FL /home/omar/LineFPGA/Synchronizer.vhd EN work/Synchronizer 1305649281FL /home/omar/LineFPGA/VGA_Top.vhd 2011/05/16.21:12:58 O.40dEN work/VGA_Top 1305649293 FL /home/omar/LineFPGA/VGA_Top.vhd \PB ieee/std_logic_1164 1296775758AR work/VGA_Top/Behavioral 1305649294 \FL /home/omar/LineFPGA/VGA_Top.vhd EN work/VGA_Top 1305649293 CP FrameBuffer \CP Synchronizer CP Debouncer CP Bresenhamer CP SevenSegment CP Pointer \CP FreqDiv