Subversion Repositories mips_enhanced

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# Target Board: Xilinx Spartan-3A DSP 1800A Board                       ##
# Family: spartan3a                                                     ##
# Device: XC3DS1800A                                                    ##
# Package: FG676                                                        ##
# Speed Grade: -4                                                       ##
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# ==== Clock inputs (CLK) ====
NET "clk_in" LOC = "F13" | IOSTANDARD = LVCMOS33 ;
NET "clk_in" PERIOD = 8ns HIGH 50%;

#NET "clk_vga" LOC = "P26" | IOSTANDARD = LVCMOS33 ;
#NET "clk_vga" PERIOD = 40ns HIGH 50%;

NET erx_clk PERIOD = 40.000;
OFFSET = IN : 10.000 : BEFORE erx_clk;
NET etx_clk PERIOD = 40.000;
OFFSET = OUT : 20.000 : AFTER etx_clk;
OFFSET = IN : 10.000 : BEFORE etx_clk;

# Avoid false paths between main clock and SVGA clock
NET "clkm"     TNM_NET = "clkm";
NET "lclk_vga" TNM_NET = "lclk_vga";
TIMESPEC "TS_clkm_vga" = FROM "clkm" TO "lclk_vga" TIG;
TIMESPEC "TS_vga_clkm" = FROM "lclk_vga" TO "clkm" TIG;
#NET "lock"  TIG;

# Avoid false paths between main clock and DDR clock
NET "clkm"  TNM_NET = "clkm";
NET "clkml" TNM_NET = "clkml";
TIMESPEC "TS_clkm_clkml" = FROM "clkm" TO "clkml" TIG;
TIMESPEC "TS_clkml_clkm" = FROM "clkml" TO "clkm" TIG;

# ==== Pushbuttons ====
NET reset       LOC = J17 | IOSTANDARD = LVTTL | PULLDOWN;
NET dsubre      LOC = J15 | IOSTANDARD = LVTTL | PULLDOWN;
#NET BTN_3      LOC = J13 | IOSTANDARD = LVTTL | PULLDOWN;
#NET BTN_4      LOC = J10 | IOSTANDARD = LVTTL | PULLDOWN;

# ==== Discrete LEDs ====
NET led(0)      LOC = P18 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8;
NET led(1)      LOC = P25 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8;
NET led(2)      LOC = N19 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8;
#NET led(3)     LOC = K22 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8;
#NET led(4)     LOC = H20 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8;
#NET led(5)     LOC = G21 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8;
#NET led(6)     LOC = D24 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8;
NET errorn      LOC = D25 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 | PULLUP;

# ==== DIP Switches ====
#NET sw(0)      LOC = A7  | IOSTANDARD = LVTTL | PULLUP;
#NET sw(1)      LOC = G16 | IOSTANDARD = LVTTL | PULLUP;
#NET sw(2)      LOC = E9  | IOSTANDARD = LVTTL | PULLUP;
#NET sw(3)      LOC = D16 | IOSTANDARD = LVTTL | PULLUP;
#NET sw(4)      LOC = D19 | IOSTANDARD = LVTTL | PULLUP;
#NET sw(5)      LOC = B24 | IOSTANDARD = LVTTL | PULLUP;
#NET sw(6)      LOC = A5  | IOSTANDARD = LVTTL | PULLUP;
#NET sw(7)      LOC = A23 | IOSTANDARD = LVTTL | PULLUP;

# ==== DDR2 SDRAM (32-bit data buss) ====
NET ddr_clk(0)  LOC = N1  | IOSTANDARD = SSTL18_I;
NET ddr_clk(1)  LOC = N5  | IOSTANDARD = SSTL18_I;
NET ddr_clkb(0) LOC = N2  | IOSTANDARD = SSTL18_I;
NET ddr_clkb(1) LOC = N4  | IOSTANDARD = SSTL18_I;
NET ddr_clk_fb_out LOC = T10  | IOSTANDARD = SSTL18_I;
NET ddr_clk_fb  LOC = T9  | IOSTANDARD = SSTL18_I;
NET ddr_cas     LOC = L10 | IOSTANDARD = SSTL18_I;
NET ddr_ras     LOC = H1  | IOSTANDARD = SSTL18_I;
NET ddr_we      LOC = L9  | IOSTANDARD = SSTL18_I;
NET ddr_cke     LOC = L7  | IOSTANDARD = SSTL18_I;
NET ddr_csb     LOC = H2  | IOSTANDARD = SSTL18_I;
NET ddr_odt     LOC = G3  | IOSTANDARD = SSTL18_I;
NET ddr_dm(0)   LOC = V2  | IOSTANDARD = SSTL18_I;
NET ddr_dm(1)   LOC = V1  | IOSTANDARD = SSTL18_I;
NET ddr_dm(2)   LOC = R2  | IOSTANDARD = SSTL18_I;
NET ddr_dm(3)   LOC = M6  | IOSTANDARD = SSTL18_I;
NET ddr_dqs(0)  LOC = V7  | IOSTANDARD = DIFF_SSTL18_II;
NET ddr_dqs(1)  LOC = T5  | IOSTANDARD = DIFF_SSTL18_II;
NET ddr_dqs(2)  LOC = W3  | IOSTANDARD = DIFF_SSTL18_II;
NET ddr_dqs(3)  LOC = R3  | IOSTANDARD = DIFF_SSTL18_II;
NET ddr_dqsn(0) LOC = V6  | IOSTANDARD = DIFF_SSTL18_II;
NET ddr_dqsn(1) LOC = U4  | IOSTANDARD = DIFF_SSTL18_II;
NET ddr_dqsn(2) LOC = W4  | IOSTANDARD = DIFF_SSTL18_II;
NET ddr_dqsn(3) LOC = R4  | IOSTANDARD = DIFF_SSTL18_II;
NET ddr_ad(0)   LOC = J5  | IOSTANDARD = SSTL18_I;
NET ddr_ad(1)   LOC = M9  | IOSTANDARD = SSTL18_I;
NET ddr_ad(2)   LOC = M10 | IOSTANDARD = SSTL18_I;
NET ddr_ad(3)   LOC = K4  | IOSTANDARD = SSTL18_I;
NET ddr_ad(4)   LOC = K5  | IOSTANDARD = SSTL18_I;
NET ddr_ad(5)   LOC = K2  | IOSTANDARD = SSTL18_I;
NET ddr_ad(6)   LOC = K3  | IOSTANDARD = SSTL18_I;
NET ddr_ad(7)   LOC = L3  | IOSTANDARD = SSTL18_I;
NET ddr_ad(8)   LOC = L4  | IOSTANDARD = SSTL18_I;
NET ddr_ad(9)   LOC = M7  | IOSTANDARD = SSTL18_I;
NET ddr_ad(10)  LOC = M8  | IOSTANDARD = SSTL18_I;
NET ddr_ad(11)  LOC = M3  | IOSTANDARD = SSTL18_I;
NET ddr_ad(12)  LOC = M4  | IOSTANDARD = SSTL18_I;
NET ddr_ba(0)   LOC = K6  | IOSTANDARD = SSTL18_I;
NET ddr_ba(1)   LOC = J4  | IOSTANDARD = SSTL18_I;
NET ddr_dq(0)   LOC = U9  | IOSTANDARD = SSTL18_I;
NET ddr_dq(1)   LOC = V8  | IOSTANDARD = SSTL18_I;
NET ddr_dq(2)   LOC = AB1 | IOSTANDARD = SSTL18_I;
NET ddr_dq(3)   LOC = AC1 | IOSTANDARD = SSTL18_I;
NET ddr_dq(4)   LOC = Y5  | IOSTANDARD = SSTL18_I;
NET ddr_dq(5)   LOC = Y6  | IOSTANDARD = SSTL18_I;
NET ddr_dq(6)   LOC = U7  | IOSTANDARD = SSTL18_I;
NET ddr_dq(7)   LOC = U8  | IOSTANDARD = SSTL18_I;
NET ddr_dq(8)   LOC = AA2 | IOSTANDARD = SSTL18_I;
NET ddr_dq(9)   LOC = AA3 | IOSTANDARD = SSTL18_I;
NET ddr_dq(10)  LOC = Y1  | IOSTANDARD = SSTL18_I;
NET ddr_dq(11)  LOC = Y2  | IOSTANDARD = SSTL18_I;
NET ddr_dq(12)  LOC = T7  | IOSTANDARD = SSTL18_I;
NET ddr_dq(13)  LOC = U6  | IOSTANDARD = SSTL18_I;
NET ddr_dq(14)  LOC = U5  | IOSTANDARD = SSTL18_I;
NET ddr_dq(15)  LOC = V5  | IOSTANDARD = SSTL18_I;
NET ddr_dq(16)  LOC = R8  | IOSTANDARD = SSTL18_I;
NET ddr_dq(17)  LOC = R7  | IOSTANDARD = SSTL18_I;
NET ddr_dq(18)  LOC = U1  | IOSTANDARD = SSTL18_I;
NET ddr_dq(19)  LOC = U2  | IOSTANDARD = SSTL18_I;
NET ddr_dq(20)  LOC = P8  | IOSTANDARD = SSTL18_I;
NET ddr_dq(21)  LOC = P9  | IOSTANDARD = SSTL18_I;
NET ddr_dq(22)  LOC = R5  | IOSTANDARD = SSTL18_I;
NET ddr_dq(23)  LOC = R6  | IOSTANDARD = SSTL18_I;
NET ddr_dq(24)  LOC = P7  | IOSTANDARD = SSTL18_I;
NET ddr_dq(25)  LOC = P6  | IOSTANDARD = SSTL18_I;
NET ddr_dq(26)  LOC = T3  | IOSTANDARD = SSTL18_I;
NET ddr_dq(27)  LOC = T4  | IOSTANDARD = SSTL18_I;
NET ddr_dq(28)  LOC = N9  | IOSTANDARD = SSTL18_I;
NET ddr_dq(29)  LOC = P10 | IOSTANDARD = SSTL18_I;
NET ddr_dq(30)  LOC = P4  | IOSTANDARD = SSTL18_I;
NET ddr_dq(31)  LOC = P3  | IOSTANDARD = SSTL18_I;

# ==== Ethernet PHY ====
NET reset_o2    LOC = G4  | IOSTANDARD = LVCMOS18;
NET erx_clk     LOC = P1  | IOSTANDARD = LVCMOS18;
NET etx_clk     LOC = P2  | IOSTANDARD = LVCMOS18;
NET erx_crs     LOC = G1  | IOSTANDARD = LVCMOS18;
NET erx_dv      LOC = D1  | IOSTANDARD = LVCMOS18;
NET erx_col     LOC = Y3  | IOSTANDARD = LVCMOS18;
NET erx_er      LOC = J3  | IOSTANDARD = LVCMOS18;
NET erxd(0)     LOC = C2  | IOSTANDARD = LVCMOS18;
NET erxd(1)     LOC = G2  | IOSTANDARD = LVCMOS18;
NET erxd(2)     LOC = G5  | IOSTANDARD = LVCMOS18;
NET erxd(3)     LOC = D2  | IOSTANDARD = LVCMOS18;
#NET erxd(4)    LOC = AB3 | IOSTANDARD = LVCMOS18;
#NET erxd(5)    LOC = AA4 | IOSTANDARD = LVCMOS18;
#NET erxd(6)    LOC = AB4 | IOSTANDARD = LVCMOS18;
#NET erxd(7)    LOC = Y4  | IOSTANDARD = LVCMOS18;
NET etx_en      LOC = D3  | IOSTANDARD = LVCMOS18;
NET etx_er      LOC = E4  | IOSTANDARD = LVCMOS18;
NET emdc        LOC = F4  | IOSTANDARD = LVCMOS18;
NET emdio       LOC = F5  | IOSTANDARD = LVCMOS18;
NET etxd(0)     LOC = J8  | IOSTANDARD = LVCMOS18;
NET etxd(1)     LOC = J9  | IOSTANDARD = LVCMOS18;
NET etxd(2)     LOC = B2  | IOSTANDARD = LVCMOS18;
NET etxd(3)     LOC = B1  | IOSTANDARD = LVCMOS18;
#NET etxd(4)    LOC = G6  | IOSTANDARD = LVCMOS18;
#NET etxd(5)    LOC = H7  | IOSTANDARD = LVCMOS18;
#NET etxd(6)    LOC = K9  | IOSTANDARD = LVCMOS18;
#NET etxd(7)    LOC = K8  | IOSTANDARD = LVCMOS18;
#
#NET GTX_CLK    LOC = E3  | IOSTANDARD = LVCMOS18;
#NET INT        LOC = J1  | IOSTANDARD = LVCMOS18;
#NET MCLK       LOC = N6  | IOSTANDARD = LVCMOS18;

# ==== VGA Serial Port ====
NET vid_hsync   LOC = K26 | IOSTANDARD = LVCMOS33;
NET vid_vsync   LOC = K25 | IOSTANDARD = LVCMOS33;
NET vid_r(0)    LOC = L20 | IOSTANDARD = LVCMOS33;
NET vid_r(1)    LOC = K20 | IOSTANDARD = LVCMOS33;
NET vid_r(2)    LOC = F25 | IOSTANDARD = LVCMOS33;
NET vid_r(3)    LOC = F24 | IOSTANDARD = LVCMOS33;
NET vid_g(0)    LOC = M19 | IOSTANDARD = LVCMOS33;
NET vid_g(1)    LOC = M18 | IOSTANDARD = LVCMOS33;
NET vid_g(2)    LOC = J23 | IOSTANDARD = LVCMOS33;
NET vid_g(3)    LOC = J22 | IOSTANDARD = LVCMOS33;
NET vid_b(0)    LOC = L22 | IOSTANDARD = LVCMOS33;
NET vid_b(1)    LOC = K21 | IOSTANDARD = LVCMOS33;
NET vid_b(2)    LOC = G23 | IOSTANDARD = LVCMOS33;
NET vid_b(3)    LOC = G24 | IOSTANDARD = LVCMOS33;

# ==== Debug UART (AHB) RS232 ====
NET dsurx       LOC = N21 | IOSTANDARD = LVTTL;
NET dsutx       LOC = P22 | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;

# ==== Flash Memory ====
NET reset_o1    LOC = N24  | IOSTANDARD = LVCMOS33;
NET address(23) LOC = C25  | IOSTANDARD = LVCMOS33;
NET address(22) LOC = C26  | IOSTANDARD = LVCMOS33;
NET address(21) LOC = H21  | IOSTANDARD = LVCMOS33;
NET address(20) LOC = J21  | IOSTANDARD = LVCMOS33;
NET address(19) LOC = J25  | IOSTANDARD = LVCMOS33;
NET address(18) LOC = J26  | IOSTANDARD = LVCMOS33;
NET address(17) LOC = M20  | IOSTANDARD = LVCMOS33;
NET address(16) LOC = N20  | IOSTANDARD = LVCMOS33;
NET address(15) LOC = N17  | IOSTANDARD = LVCMOS33;
NET address(14) LOC = N18  | IOSTANDARD = LVCMOS33;
NET address(13) LOC = M23  | IOSTANDARD = LVCMOS33;
NET address(12) LOC = L24  | IOSTANDARD = LVCMOS33;
NET address(11) LOC = M25  | IOSTANDARD = LVCMOS33;
NET address(10) LOC = M26  | IOSTANDARD = LVCMOS33;
NET address(9)  LOC = R26  | IOSTANDARD = LVCMOS33;
NET address(8)  LOC = R25  | IOSTANDARD = LVCMOS33;
NET address(7)  LOC = R17  | IOSTANDARD = LVCMOS33;
NET address(6)  LOC = R18  | IOSTANDARD = LVCMOS33;
NET address(5)  LOC = T24  | IOSTANDARD = LVCMOS33;
NET address(4)  LOC = T23  | IOSTANDARD = LVCMOS33;
NET address(3)  LOC = R22  | IOSTANDARD = LVCMOS33;
NET address(2)  LOC = R21  | IOSTANDARD = LVCMOS33;
NET address(1)  LOC = AC24 | IOSTANDARD = LVCMOS33;
NET address(0)  LOC = AC23 | IOSTANDARD = LVCMOS33;

NET data(7)     LOC = AE10 | IOSTANDARD = LVCMOS33;
NET data(6)     LOC = AF10 | IOSTANDARD = LVCMOS33;
NET data(5)     LOC = AF12 | IOSTANDARD = LVCMOS33;
NET data(4)     LOC = AE12 | IOSTANDARD = LVCMOS33;
NET data(3)     LOC = Y15  | IOSTANDARD = LVCMOS33;
NET data(2)     LOC = AF18 | IOSTANDARD = LVCMOS33;
NET data(1)     LOC = AE18 | IOSTANDARD = LVCMOS33;
NET data(0)     LOC = AF24 | IOSTANDARD = LVCMOS33;
NET oen         LOC = AE26 | IOSTANDARD = LVCMOS33;
NET writen      LOC = Y20  | IOSTANDARD = LVCMOS33;
NET romsn       LOC = AE25 | IOSTANDARD = LVCMOS33;

## This is to force the SPI ROM to not be selected(drive high)
NET spi         LOC = AA7 | IOSTANDARD = LVCMOS33 | PULLUP;