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<h3 style="font-family: helvetica,arial,sans-serif; text-align: justify;"><small>Welcome
to the GRLIB IP Library<br>
</small></h3>
<div style="text-align: justify;"><small><span style="font-family: helvetica,arial,sans-serif;">The GRLIB IP Library
is an integrated set of reusable IP cores, designed for </span><span style="font-style: italic; font-family: helvetica,arial,sans-serif;">system-on-chip</span><span style="font-family: helvetica,arial,sans-serif;">
(SOC) development. The IP cores are centered around the common on-chip
bus, and use a coherent method for simulation and synthesis. The
library is vendor independent, with support for different CAD tools and
target technologies. A unique plug&play method is used to configure
and connect the IP cores without the need to modify any global
resources. </span></small><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><br style="font-family: helvetica,arial,sans-serif;">
<br style="font-family: helvetica,arial,sans-serif;">
</div>
<small><span style="font-family: helvetica,arial,sans-serif;">The
library includes cores for AMBA AHB/APB control, the LEON3 SPARC
processor, 32-bit PC133 SDRAM controller, 32-bit PCI bridge with DMA,
10/100/1000 Mbit ethernet MAC, ATA controller, 16/32/64-bits DDR controller, USB-2.0 Debug
link, TAP controller, CAN-2.0 core, 8/16/32-bit PROM and SRAM
controller, SVGA frame buffer, generic
UART, modular timer unit, interrupt controller, and a 32-bit GPIO port.
Memory and pad generators are available for Virage, Xilinx, UMC, Atmel,
Altera, Lattice, and Actel.<br>
</span></small>
<h3><small><span style="font-family: helvetica,arial,sans-serif;">Documentation</span></small></h3>
<small><span style="font-family: helvetica,arial,sans-serif;"></span></small>
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<td valign="top"><b><font face="Helvetica, Arial, sans-serif"><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><a href="doc/grlib.pdf">GRLIB User's Manual<br>
</a></small></font></b></td>
</tr><tr>
<td valign="top"><b><font face="Helvetica, Arial, sans-serif"><small><a href="doc/grip.pdf">GRLIB IP core User's Manual</a><a href="doc/area.html"><br>
</a></small></font></b></td>
</tr><tr>
<td valign="top"><b><font face="Helvetica, Arial, sans-serif"><small><a href="designs/leon3-gr-xc3s-1500/doc/leon3-gr-xc3s-1500.pdf">LEON3 GR-XC3S-1500 Template design manual<br>
</a></small></font></b></td>
</tr><tr>
<td valign="top"><b><font face="Helvetica, Arial, sans-serif"><small><a href="designs/leon3-ge-hpe-mini-lattice/doc/leon3-ge-hpe-lattice.pdf">LEON3 GE-Hpe-Mini-Lattice Template design manual</a><a href="designs/leon3-gr-xc3s-1500/doc/leon3-gr-xc3s-1500.pdf"><br>
</a></small></font></b></td>
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<small><span style="font-family: helvetica,arial,sans-serif;"><a href="doc/grlib/grlib_overview.html"></a></span></small><h3><small><span style="font-family: helvetica,arial,sans-serif;">Designs</span></small></h3><small><span style="font-family: helvetica,arial,sans-serif;">GRLIB contains <a href="designs/leon3mp/index.html">LEON3 template designs</a> and bitfiles for the following FPGA boards</span></small><br>
<h4><small><small><span style="font-family: helvetica,arial,sans-serif;">Xilinx<br>
</span></small></small></h4>
<ul>
<li><small><span style="font-family: helvetica,arial,sans-serif;">Pender/Gaisler <a href="http://www.pender.ch/products_xc3s.shtml">GR-XC3S1500 board</a></span></small><small><span style="font-family: helvetica,arial,sans-serif;"> (<a href="designs/leon3-gr-xc3s-1500/index.html">details</a>)</span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">Pender/Gaisler <a href="http://www.pender.ch/products_pci_xc2v.shtml">GR-PCI-XC2V3000 board</a> (<a href="designs/leon3-gr-pci-xc2v3000/index.html">details</a>)<a href="http://www.pender.ch/products_pci_xc2v.shtml"><br>
</a></span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">Pender/Gaisler <a href="http://www.pender.ch/products_cpci_xc2v.shtml">GR-CPCI-XC2V6000 board</a> (<a href="designs/leon3-gr-cpci-xc2v6000/index.html">details</a>)</span></small></li>
<li><small><span style="font-family: helvetica,arial,sans-serif;">Pender/Gaisler GR-CPCI-XC4V board<br>
</span></small></li>
<li><small><span style="font-family: helvetica,arial,sans-serif;">Nuhorizons <a href="http://www.nuhorizons.com/xilinx/boards/spartan-3/SP3-1500-2000Board/index.asp">Spartan3-1500 board</a> (<a href="designs/leon3-nuhorizons-3s1500/index.html">details</a>)<a href="http://www.nuhorizons.com/xilinx/boards/spartan-3/SP3-1500-2000Board/index.asp"><br>
</a></span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">Avnet <a href="http://www.em.avnet.com/evk/home/0,4534,CID%253D7816%2526CCD%253DUSA%2526SID%253DNoNav%2526DID%253DDF2%2526LID%253DNoNav%25255F%2526BID%253DDF2%2526CTP%253DEVK,00.html">Spartan3-1500 board</a> (<a href="designs/leon3-avnet-3s1500/index.html">details</a>)</span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;"> Avnet <a href="http://www.em.avnet.com/evk/home/0,1719,RID%253D0%2526CID%253D16863%2526CCD%253DUSA%2526SID%253D32214%2526DID%253DDF2%2526SRT%253D1%2526LID%253D32232%2526PRT%253D0%2526PVW%253D%2526BID%253DDF2%2526CTP%253DEVK,00.html">Virtex4 Evaluation board</a></span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">Memec <a href="http://www.ee.ucla.edu/%7Eherwin/ocdma/Insight/V2MB_User_Guide_1_4.PDF">Virxtex-II V2MB1000 board<br>
</a></span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">Digilent <a href="http://www.digilentinc.com/Products/Detail.cfm?Prod=XUPV2P&Nav1=Products&Nav2=Programmable">Virtex2pro XUP board</a></span></small></li>
<li><small><span style="font-family: helvetica,arial,sans-serif;">Digilent <a href="http://www.digilentinc.com/Products/Detail.cfm?Prod=S3E1600&Nav1=Products&Nav2=Programmable">Spartan3e-1600 Development board</a></span></small></li>
<li><small><span style="font-family: helvetica,arial,sans-serif;">Digilent <a href="http://www.digilentinc.com/Products/Detail.cfm?Prod=S3BOARD&Nav1=Products&Nav2=Programmable">Spartan3-1000 Starter board</a><br>
</span></small></li>
<li><small><span style="font-family: helvetica,arial,sans-serif;">Xilinx <a href="http://www.xilinx.com/products/boards/ml401/index.htm">ML401Virtex4 Development board</a></span></small></li>
</ul>
<h5><small><span style="font-family: helvetica,arial,sans-serif;">Actel<br>
</span></small></h5>
<ul>
<li><small><span style="font-family: helvetica,arial,sans-serif;">Pender/Gaisler <a href="http://www.pender.ch/products_ax2000.shtml">GR-CPCI-AX board</a> (<a href="designs/leon3-gr-cpci-ax/index.html">details</a>)</span></small></li>
</ul>
<h5><small><span style="font-family: helvetica,arial,sans-serif;">Altera</span></small></h5>
<h5><small><span style="font-family: helvetica,arial,sans-serif;"></span></small></h5>
<ul>
<li><small><span style="font-family: helvetica,arial,sans-serif;">Gleichmann <a href="http://www.ger-fae.com/hpe_compact.html">HPE_compact board with Altera Stratix I+II modules</a></span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;">Gleichmann <a href="http://www.ger-fae.com/Hpe_mini_ac2.html">HPE_mini Altera Cyclone II board</a></span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">Altera <a href="http://www.altera.com/products/devkits/altera/kit-nios_1C20.html">Cylone Development board</a><br>
</span></small></li>
<li><small><span style="font-family: helvetica,arial,sans-serif;">Altera <a href="http://www.altera.com/products/devkits/altera/kit-niosii-2S60.html">Stratix-II Development board</a></span></small></li>
</ul>
<h5><small><span style="font-family: helvetica,arial,sans-serif;">Lattice</span></small></h5>
<small><span style="font-family: helvetica,arial,sans-serif;"></span></small>
<ul>
<li><small><span style="font-family: helvetica,arial,sans-serif;">Gleichmann <a href="http://www.ger-fae.com/hpe_mini_lec.html">Hpe_mini Lattice ECP board</a></span></small></li>
</ul>
<br>
<small><span style="font-family: helvetica,arial,sans-serif;">The following template designs are also provided:<br>
</span></small>
<small><span style="font-family: helvetica,arial,sans-serif;"> </span></small>
<ul><li><small><span style="font-family: helvetica,arial,sans-serif;">PCI test bench with 5 PCI initiator/targets<br>
</span></small></li>
<li><small><span style="font-family: helvetica,arial,sans-serif;">Netcard - Simple
example of a PCI-based network card (10/100 Mbit ethernet)<br>
</span></small></li>
</ul>
<small><span style="font-family: helvetica,arial,sans-serif;"><br>
</span></small><small><span style="font-family: helvetica,arial,sans-serif;"><a href="http://www.gaisler.se/bin/linux/bcc-linux-1.0.1.tar.bz2"></a></span></small>
<div style="text-align: justify;"><small><span style="font-family: helvetica,arial,sans-serif;"></span></small></div>
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