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https://opencores.org/ocsvn/socgen/socgen/trunk
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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [doc/] [sch/] [mt45w8mw12_def.sch] - Rev 135
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v 20100214 1
C 2100 300 1 0 0 in_port_vector.sym
{
T 2100 300 5 10 1 1 0 6 1 1
refdes=addr[ADDR_BITS-1:0]
}
C 2100 700 1 0 0 in_port.sym
{
T 2100 700 5 10 1 1 0 6 1 1
refdes=we_n
}
C 2100 1100 1 0 0 in_port.sym
{
T 2100 1100 5 10 1 1 0 6 1 1
refdes=ub_n
}
C 2100 1500 1 0 0 in_port.sym
{
T 2100 1500 5 10 1 1 0 6 1 1
refdes=oe_n
}
C 2100 1900 1 0 0 in_port.sym
{
T 2100 1900 5 10 1 1 0 6 1 1
refdes=lb_n
}
C 2100 2300 1 0 0 in_port.sym
{
T 2100 2300 5 10 1 1 0 6 1 1
refdes=cre
}
C 2100 2700 1 0 0 in_port.sym
{
T 2100 2700 5 10 1 1 0 6 1 1
refdes=clk
}
C 2100 3100 1 0 0 in_port.sym
{
T 2100 3100 5 10 1 1 0 6 1 1
refdes=ce_n
}
C 2100 3500 1 0 0 in_port.sym
{
T 2100 3500 5 10 1 1 0 6 1 1
refdes=adv_n
}
C 4900 300 1 0 0 out_port.sym
{
T 5900 300 5 10 1 1 0 0 1 1
refdes=o_wait
}
C 4900 700 1 0 0 io_port_vector.sym
{
T 5900 700 5 10 1 1 0 0 1 1
refdes=dq[DQ_BITS-1:0]
}