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[/] [z80control/] [trunk/] [CII_Starter_USB_API_v1/] [HW/] [CII_Starter_USB_API.map.rpt] - Rev 12
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Analysis & Synthesis report for CII_Starter_USB_APISun Oct 11 12:23:17 2009Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition---------------------; Table of Contents ;---------------------1. Legal Notice2. Analysis & Synthesis Summary3. Analysis & Synthesis Settings4. Analysis & Synthesis Source Files Read5. Analysis & Synthesis Resource Usage Summary6. Analysis & Synthesis Resource Utilization by Entity7. Analysis & Synthesis RAM Summary8. State Machine - |CII_Starter_USB_API|I2C_AV_Config:u10|mSetup_ST9. State Machine - |CII_Starter_USB_API|CMD_Decode:u5|mSR_ST10. State Machine - |CII_Starter_USB_API|CMD_Decode:u5|mSDR_ST11. State Machine - |CII_Starter_USB_API|CMD_Decode:u5|mPS2_ST12. State Machine - |CII_Starter_USB_API|CMD_Decode:u5|mFL_ST13. State Machine - |CII_Starter_USB_API|ps2_keyboard:u4|m1_state14. State Machine - |CII_Starter_USB_API|Multi_Sdram:u3|Sdram_Multiplexer:u0|ST15. State Machine - |CII_Starter_USB_API|Multi_Flash:u2|Flash_Controller:u1|ST16. State Machine - |CII_Starter_USB_API|Multi_Flash:u2|Flash_Multiplexer:u0|ST17. Registers Removed During Synthesis18. Removed Registers Triggering Further Register Optimizations19. General Register Statistics20. Inverted Register Statistics21. Gate-level Retiming22. Multiplexer Restructuring Statistics (Restructuring Performed)23. Source assignments for VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated24. Source assignments for VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram125. Parameter Settings for User Entity Instance: Multi_Flash:u2|Flash_Controller:u126. Parameter Settings for User Entity Instance: Multi_Sdram:u3|Sdram_Controller:u127. Parameter Settings for User Entity Instance: Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component28. Parameter Settings for User Entity Instance: Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control129. Parameter Settings for User Entity Instance: Multi_Sdram:u3|Sdram_Controller:u1|command:command130. Parameter Settings for User Entity Instance: Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path131. Parameter Settings for User Entity Instance: ps2_keyboard:u432. Parameter Settings for User Entity Instance: CMD_Decode:u533. Parameter Settings for User Entity Instance: VGA_Audio_PLL:p1|altpll:altpll_component34. Parameter Settings for User Entity Instance: VGA_Controller:u835. Parameter Settings for User Entity Instance: VGA_OSD_RAM:u936. Parameter Settings for User Entity Instance: VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component37. Parameter Settings for User Entity Instance: I2C_AV_Config:u1038. Parameter Settings for User Entity Instance: AUDIO_DAC:u1139. altpll Parameter Settings by Entity Instance40. altsyncram Parameter Settings by Entity Instance41. Port Connectivity Checks: "AUDIO_DAC:u11"42. Port Connectivity Checks: "I2C_AV_Config:u10|I2C_Controller:u0"43. Port Connectivity Checks: "VGA_OSD_RAM:u9|Img_RAM:u0"44. Port Connectivity Checks: "VGA_OSD_RAM:u9"45. Port Connectivity Checks: "VGA_Controller:u8"46. Port Connectivity Checks: "Multi_Sram:u6"47. Port Connectivity Checks: "CMD_Decode:u5"48. Port Connectivity Checks: "ps2_keyboard:u4"49. Port Connectivity Checks: "Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1"50. Port Connectivity Checks: "Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1"51. Port Connectivity Checks: "Multi_Sdram:u3|Sdram_Controller:u1"52. Port Connectivity Checks: "Multi_Sdram:u3"53. Port Connectivity Checks: "Multi_Flash:u2"54. Port Connectivity Checks: "SEG7_LUT_4:u0"55. Port Connectivity Checks: "CLK_LOCK:p0|CLK_LOCK_altclkctrl_tb8:CLK_LOCK_altclkctrl_tb8_component"56. Analysis & Synthesis Messages----------------; Legal Notice ;----------------Copyright (C) 1991-2009 Altera CorporationYour use of Altera Corporation's design tools, logic functionsand other software and tools, and its AMPP partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Altera Program LicenseSubscription Agreement, Altera MegaCore Function LicenseAgreement, or other applicable license agreement, including,without limitation, that your use is for the sole purpose ofprogramming logic devices manufactured by Altera and sold byAltera or its authorized distributors. Please refer to theapplicable agreement for further details.+-----------------------------------------------------------------------------------+; Analysis & Synthesis Summary ;+------------------------------------+----------------------------------------------+; Analysis & Synthesis Status ; Successful - Sun Oct 11 12:23:17 2009 ;; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;; Revision Name ; CII_Starter_USB_API ;; Top-level Entity Name ; CII_Starter_USB_API ;; Family ; Cyclone II ;; Total logic elements ; 2,322 ;; Total combinational functions ; 1,923 ;; Dedicated logic registers ; 1,033 ;; Total registers ; 1033 ;; Total pins ; 283 ;; Total virtual pins ; 0 ;; Total memory bits ; 208,000 ;; Embedded Multiplier 9-bit elements ; 0 ;; Total PLLs ; 2 ;+------------------------------------+----------------------------------------------++----------------------------------------------------------------------------------------------------------+; Analysis & Synthesis Settings ;+--------------------------------------------------------------+---------------------+---------------------+; Option ; Setting ; Default Value ;+--------------------------------------------------------------+---------------------+---------------------+; Device ; EP2C20F484C7 ; ;; Top-level entity name ; CII_Starter_USB_API ; CII_Starter_USB_API ;; Family name ; Cyclone II ; Stratix ;; Optimization Technique ; Speed ; Balanced ;; Perform WYSIWYG Primitive Resynthesis ; On ; Off ;; Use smart compilation ; Off ; Off ;; Restructure Multiplexers ; Auto ; Auto ;; Create Debugging Nodes for IP Cores ; Off ; Off ;; Preserve fewer node names ; On ; On ;; Disable OpenCore Plus hardware evaluation ; Off ; Off ;; Verilog Version ; Verilog_2001 ; Verilog_2001 ;; VHDL Version ; VHDL93 ; VHDL93 ;; State Machine Processing ; Auto ; Auto ;; Safe State Machine ; Off ; Off ;; Extract Verilog State Machines ; On ; On ;; Extract VHDL State Machines ; On ; On ;; Ignore Verilog initial constructs ; Off ; Off ;; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;; Add Pass-Through Logic to Inferred RAMs ; On ; On ;; Parallel Synthesis ; Off ; Off ;; DSP Block Balancing ; Auto ; Auto ;; Maximum DSP Block Usage ; -1 ; -1 ;; NOT Gate Push-Back ; On ; On ;; Power-Up Don't Care ; On ; On ;; Remove Redundant Logic Cells ; Off ; Off ;; Remove Duplicate Registers ; On ; On ;; Ignore CARRY Buffers ; Off ; Off ;; Ignore CASCADE Buffers ; Off ; Off ;; Ignore GLOBAL Buffers ; Off ; Off ;; Ignore ROW GLOBAL Buffers ; Off ; Off ;; Ignore LCELL Buffers ; Off ; Off ;; Ignore SOFT Buffers ; On ; On ;; Limit AHDL Integers to 32 Bits ; Off ; Off ;; Carry Chain Length ; 70 ; 70 ;; Auto Carry Chains ; On ; On ;; Auto Open-Drain Pins ; On ; On ;; Auto ROM Replacement ; On ; On ;; Auto RAM Replacement ; On ; On ;; Auto Shift Register Replacement ; Auto ; Auto ;; Auto Clock Enable Replacement ; On ; On ;; Strict RAM Replacement ; Off ; Off ;; Allow Synchronous Control Signals ; On ; On ;; Force Use of Synchronous Clear Signals ; Off ; Off ;; Auto RAM to Logic Cell Conversion ; Off ; Off ;; Auto Resource Sharing ; Off ; Off ;; Allow Any RAM Size For Recognition ; Off ; Off ;; Allow Any ROM Size For Recognition ; Off ; Off ;; Allow Any Shift Register Size For Recognition ; Off ; Off ;; Use LogicLock Constraints during Resource Balancing ; On ; On ;; Maximum Number of M4K/M9K Memory Blocks ; -1 ; -1 ;; Ignore translate_off and synthesis_off directives ; Off ; Off ;; Timing-Driven Synthesis ; Off ; Off ;; Show Parameter Settings Tables in Synthesis Report ; On ; On ;; Ignore Maximum Fan-Out Assignments ; Off ; Off ;; Synchronization Register Chain Length ; 2 ; 2 ;; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;; HDL message level ; Level2 ; Level2 ;; Suppress Register Optimization Related Messages ; Off ; Off ;; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;; Clock MUX Protection ; On ; On ;; Auto Gated Clock Conversion ; Off ; Off ;; Block Design Naming ; Auto ; Auto ;; SDC constraint protection ; Off ; Off ;; Synthesis Effort ; Auto ; Auto ;; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;; Analysis & Synthesis Message Level ; Medium ; Medium ;+--------------------------------------------------------------+---------------------+---------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Analysis & Synthesis Source Files Read ;+----------------------------------+-----------------+----------------------------------------+---------------------------------------------------------------------------------------------------------+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;+----------------------------------+-----------------+----------------------------------------+---------------------------------------------------------------------------------------------------------+; VGA_Controller/Img_RAM.v ; yes ; User Verilog HDL File ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/VGA_Controller/Img_RAM.v ;; VGA_Controller/VGA_OSD_RAM.v ; yes ; User Verilog HDL File ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/VGA_Controller/VGA_OSD_RAM.v ;; VGA_Controller/VGA_Controller.v ; yes ; User Verilog HDL File ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/VGA_Controller/VGA_Controller.v ;; Multi_Sdram/command.v ; yes ; User Verilog HDL File ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/Multi_Sdram/command.v ;; Multi_Sdram/control_interface.v ; yes ; User Verilog HDL File ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/Multi_Sdram/control_interface.v ;; Multi_Sdram/Multi_Sdram.v ; yes ; User Verilog HDL File ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/Multi_Sdram/Multi_Sdram.v ;; Multi_Sdram/PLL1.v ; yes ; User Verilog HDL File ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/Multi_Sdram/PLL1.v ;; Multi_Sdram/sdr_data_path.v ; yes ; User Verilog HDL File ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/Multi_Sdram/sdr_data_path.v ;; Multi_Sdram/Sdram_Controller.v ; yes ; User Verilog HDL File ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/Multi_Sdram/Sdram_Controller.v ;; Multi_Sdram/Sdram_Multiplexer.v ; yes ; User Verilog HDL File ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/Multi_Sdram/Sdram_Multiplexer.v ;; Multi_Flash/Flash_Controller.v ; yes ; User Verilog HDL File ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/Multi_Flash/Flash_Controller.v ;; Multi_Flash/Flash_Multiplexer.v ; yes ; User Verilog HDL File ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/Multi_Flash/Flash_Multiplexer.v ;; Multi_Flash/Multi_Flash.v ; yes ; User Verilog HDL File ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/Multi_Flash/Multi_Flash.v ;; AUDIO_DAC.v ; yes ; User Verilog HDL File ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/AUDIO_DAC.v ;; CLK_LOCK.v ; yes ; User Verilog HDL File ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/CLK_LOCK.v ;; CMD_Decode.v ; yes ; User Verilog HDL File ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/CMD_Decode.v ;; CII_Starter_USB_API.v ; yes ; User Verilog HDL File ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/CII_Starter_USB_API.v ;; Flash_Command.h ; yes ; User File ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/Flash_Command.h ;; I2C_AV_Config.v ; yes ; User Verilog HDL File ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/I2C_AV_Config.v ;; I2C_Controller.v ; yes ; User Verilog HDL File ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/I2C_Controller.v ;; Multi_Sram.v ; yes ; User Verilog HDL File ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/Multi_Sram.v ;; ps2_keyboard.v ; yes ; User Verilog HDL File ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/ps2_keyboard.v ;; Reset_Delay.v ; yes ; User Verilog HDL File ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/Reset_Delay.v ;; RS232_Command.h ; yes ; User File ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/RS232_Command.h ;; SEG7_LUT.v ; yes ; User Verilog HDL File ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/SEG7_LUT.v ;; USB_JTAG.v ; yes ; User Verilog HDL File ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/USB_JTAG.v ;; VGA_Audio_PLL.v ; yes ; User Verilog HDL File ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/VGA_Audio_PLL.v ;; SEG7_LUT_4.v ; yes ; User Verilog HDL File ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/SEG7_LUT_4.v ;; Multi_Sdram/Sdram_Params.h ; yes ; Auto-Found Unspecified File ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/Multi_Sdram/Sdram_Params.h ;; VGA_Controller/VGA_Param.h ; yes ; Auto-Found Unspecified File ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/VGA_Controller/VGA_Param.h ;; altpll.tdf ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/altpll.tdf ;; aglobal90.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/aglobal90.inc ;; stratix_pll.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/stratix_pll.inc ;; stratixii_pll.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/stratixii_pll.inc ;; cycloneii_pll.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/cycloneii_pll.inc ;; altsyncram.tdf ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/altsyncram.tdf ;; stratix_ram_block.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/stratix_ram_block.inc ;; lpm_mux.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/lpm_mux.inc ;; lpm_decode.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/lpm_decode.inc ;; a_rdenreg.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/a_rdenreg.inc ;; altrom.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/altrom.inc ;; altram.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/altram.inc ;; altdpram.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/altdpram.inc ;; altqpram.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/altqpram.inc ;; db/altsyncram_f7o1.tdf ; yes ; Auto-Generated Megafunction ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/db/altsyncram_f7o1.tdf ;; db/altsyncram_e132.tdf ; yes ; Auto-Generated Megafunction ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/db/altsyncram_e132.tdf ;; Img_DATA.hex ; yes ; Auto-Found Memory Initialization File ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/Img_DATA.hex ;; db/decode_qpa.tdf ; yes ; Auto-Generated Megafunction ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/db/decode_qpa.tdf ;; db/mux_akb.tdf ; yes ; Auto-Generated Megafunction ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/db/mux_akb.tdf ;; db/mux_3kb.tdf ; yes ; Auto-Generated Megafunction ; C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/db/mux_3kb.tdf ;+----------------------------------+-----------------+----------------------------------------+---------------------------------------------------------------------------------------------------------++--------------------------------------------------------+; Analysis & Synthesis Resource Usage Summary ;+---------------------------------------------+----------+; Resource ; Usage ;+---------------------------------------------+----------+; Estimated Total logic elements ; 2,322 ;; ; ;; Total combinational functions ; 1923 ;; Logic element usage by number of LUT inputs ; ;; -- 4 input functions ; 1079 ;; -- 3 input functions ; 357 ;; -- <=2 input functions ; 487 ;; ; ;; Logic elements by mode ; ;; -- normal mode ; 1570 ;; -- arithmetic mode ; 353 ;; ; ;; Total registers ; 1033 ;; -- Dedicated logic registers ; 1033 ;; -- I/O registers ; 0 ;; ; ;; I/O pins ; 283 ;; Total memory bits ; 208000 ;; Total PLLs ; 2 ;; Maximum fan-out node ; CLOCK_50 ;; Maximum fan-out ; 562 ;; Total fan-out ; 10659 ;; Average fan-out ; 3.24 ;+---------------------------------------------+----------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Analysis & Synthesis Resource Utilization by Entity ;+-------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;+-------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+; |CII_Starter_USB_API ; 1923 (5) ; 1033 (0) ; 208000 ; 0 ; 0 ; 0 ; 283 ; 0 ; |CII_Starter_USB_API ; work ;; |AUDIO_DAC:u11| ; 166 (166) ; 95 (95) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|AUDIO_DAC:u11 ; work ;; |CLK_LOCK:p0| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|CLK_LOCK:p0 ; work ;; |CLK_LOCK_altclkctrl_tb8:CLK_LOCK_altclkctrl_tb8_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|CLK_LOCK:p0|CLK_LOCK_altclkctrl_tb8:CLK_LOCK_altclkctrl_tb8_component ; work ;; |CMD_Decode:u5| ; 179 (179) ; 316 (316) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|CMD_Decode:u5 ; work ;; |I2C_AV_Config:u10| ; 85 (44) ; 57 (35) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|I2C_AV_Config:u10 ; work ;; |I2C_Controller:u0| ; 41 (41) ; 22 (22) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|I2C_AV_Config:u10|I2C_Controller:u0 ; work ;; |Multi_Flash:u2| ; 170 (0) ; 112 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|Multi_Flash:u2 ; work ;; |Flash_Controller:u1| ; 112 (112) ; 99 (99) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|Multi_Flash:u2|Flash_Controller:u1 ; work ;; |Flash_Multiplexer:u0| ; 58 (58) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|Multi_Flash:u2|Flash_Multiplexer:u0 ; work ;; |Multi_Sdram:u3| ; 238 (0) ; 220 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|Multi_Sdram:u3 ; work ;; |Sdram_Controller:u1| ; 189 (62) ; 215 (73) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|Multi_Sdram:u3|Sdram_Controller:u1 ; work ;; |PLL1:sdram_pll1| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1 ; work ;; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component ; work ;; |command:command1| ; 62 (62) ; 48 (48) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|Multi_Sdram:u3|Sdram_Controller:u1|command:command1 ; work ;; |control_interface:control1| ; 65 (65) ; 62 (62) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1 ; work ;; |sdr_data_path:data_path1| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1 ; work ;; |Sdram_Multiplexer:u0| ; 49 (49) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|Multi_Sdram:u3|Sdram_Multiplexer:u0 ; work ;; |Multi_Sram:u6| ; 38 (38) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|Multi_Sram:u6 ; work ;; |Reset_Delay:d0| ; 28 (28) ; 21 (21) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|Reset_Delay:d0 ; work ;; |SEG7_LUT_4:u0| ; 28 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|SEG7_LUT_4:u0 ; work ;; |SEG7_LUT:u0| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|SEG7_LUT_4:u0|SEG7_LUT:u0 ; work ;; |SEG7_LUT:u1| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|SEG7_LUT_4:u0|SEG7_LUT:u1 ; work ;; |SEG7_LUT:u2| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|SEG7_LUT_4:u0|SEG7_LUT:u2 ; work ;; |SEG7_LUT:u3| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|SEG7_LUT_4:u0|SEG7_LUT:u3 ; work ;; |USB_JTAG:u1| ; 17 (3) ; 37 (13) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|USB_JTAG:u1 ; work ;; |JTAG_REC:u0| ; 5 (5) ; 19 (19) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|USB_JTAG:u1|JTAG_REC:u0 ; work ;; |JTAG_TRANS:u1| ; 9 (9) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|USB_JTAG:u1|JTAG_TRANS:u1 ; work ;; |VGA_Audio_PLL:p1| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|VGA_Audio_PLL:p1 ; work ;; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|VGA_Audio_PLL:p1|altpll:altpll_component ; work ;; |VGA_Controller:u8| ; 247 (247) ; 73 (73) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|VGA_Controller:u8 ; work ;; |VGA_OSD_RAM:u9| ; 458 (82) ; 43 (31) ; 208000 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|VGA_OSD_RAM:u9 ; work ;; |Img_RAM:u0| ; 376 (0) ; 12 (0) ; 208000 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|VGA_OSD_RAM:u9|Img_RAM:u0 ; work ;; |altsyncram:altsyncram_component| ; 376 (0) ; 12 (0) ; 208000 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component ; work ;; |altsyncram_f7o1:auto_generated| ; 376 (0) ; 12 (0) ; 208000 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated ; work ;; |altsyncram_e132:altsyncram1| ; 376 (0) ; 12 (12) ; 208000 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1 ; work ;; |decode_qpa:decode_a| ; 65 (65) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a ; work ;; |mux_akb:mux5| ; 311 (311) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|mux_akb:mux5 ; work ;; |ps2_keyboard:u4| ; 264 (264) ; 59 (59) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CII_Starter_USB_API|ps2_keyboard:u4 ; work ;+-------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Analysis & Synthesis RAM Summary ;+---------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+--------+--------------+; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;+---------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+--------+--------------+; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ALTSYNCRAM ; M4K ; True Dual Port ; 26000 ; 8 ; 208000 ; 1 ; 208000 ; Img_DATA.hex ;+---------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+--------+--------------+Encoding Type: One-Hot+------------------------------------------------------------------+; State Machine - |CII_Starter_USB_API|I2C_AV_Config:u10|mSetup_ST ;+--------------+--------------+--------------+---------------------+; Name ; mSetup_ST.00 ; mSetup_ST.10 ; mSetup_ST.01 ;+--------------+--------------+--------------+---------------------+; mSetup_ST.00 ; 0 ; 0 ; 0 ;; mSetup_ST.01 ; 1 ; 0 ; 1 ;; mSetup_ST.10 ; 1 ; 1 ; 0 ;+--------------+--------------+--------------+---------------------+Encoding Type: One-Hot+------------------------------------------------------------------------------------------+; State Machine - |CII_Starter_USB_API|CMD_Decode:u5|mSR_ST ;+------------+------------+------------+------------+------------+------------+------------+; Name ; mSR_ST.101 ; mSR_ST.100 ; mSR_ST.011 ; mSR_ST.010 ; mSR_ST.001 ; mSR_ST.000 ;+------------+------------+------------+------------+------------+------------+------------+; mSR_ST.000 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;; mSR_ST.001 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;; mSR_ST.010 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;; mSR_ST.011 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;; mSR_ST.100 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;; mSR_ST.101 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;+------------+------------+------------+------------+------------+------------+------------+Encoding Type: One-Hot+-------------------------------------------------------------------------------------------------+; State Machine - |CII_Starter_USB_API|CMD_Decode:u5|mSDR_ST ;+-------------+-------------+-------------+-------------+-------------+-------------+-------------+; Name ; mSDR_ST.101 ; mSDR_ST.100 ; mSDR_ST.011 ; mSDR_ST.010 ; mSDR_ST.001 ; mSDR_ST.000 ;+-------------+-------------+-------------+-------------+-------------+-------------+-------------+; mSDR_ST.000 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;; mSDR_ST.001 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;; mSDR_ST.010 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;; mSDR_ST.011 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;; mSDR_ST.100 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;; mSDR_ST.101 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;+-------------+-------------+-------------+-------------+-------------+-------------+-------------+Encoding Type: One-Hot+------------------------------------------------------------+; State Machine - |CII_Starter_USB_API|CMD_Decode:u5|mPS2_ST ;+-------------+----------------------------------------------+; Name ; mPS2_ST.001 ;+-------------+----------------------------------------------+; mPS2_ST.000 ; 0 ;; mPS2_ST.001 ; 1 ;+-------------+----------------------------------------------+Encoding Type: One-Hot+--------------------------------------------------------------------------------------------------------------------+; State Machine - |CII_Starter_USB_API|CMD_Decode:u5|mFL_ST ;+------------+------------+------------+------------+------------+------------+------------+------------+------------+; Name ; mFL_ST.111 ; mFL_ST.110 ; mFL_ST.101 ; mFL_ST.100 ; mFL_ST.011 ; mFL_ST.010 ; mFL_ST.001 ; mFL_ST.000 ;+------------+------------+------------+------------+------------+------------+------------+------------+------------+; mFL_ST.000 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;; mFL_ST.001 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;; mFL_ST.010 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;; mFL_ST.011 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;; mFL_ST.100 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;; mFL_ST.101 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;; mFL_ST.110 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;; mFL_ST.111 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;+------------+------------+------------+------------+------------+------------+------------+------------+------------+Encoding Type: One-Hot+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; State Machine - |CII_Starter_USB_API|ps2_keyboard:u4|m1_state ;+--------------------------------------+-----------------------------------+------------------------------------+----------------------------+---------------------------------+---------------------------------+-----------------------------------+--------------------------------------+------------------------------+----------------------------------+----------------------+----------------------+----------------------------+---------------------------+----------------------+----------------------+; Name ; m1_state.m1_rx_rising_edge_marker ; m1_state.m1_rx_falling_edge_marker ; m1_state.m1_tx_reset_timer ; m1_state.m1_tx_first_wait_clk_l ; m1_state.m1_tx_first_wait_clk_h ; m1_state.m1_tx_rising_edge_marker ; m1_state.m1_tx_error_no_keyboard_ack ; m1_state.m1_tx_done_recovery ; m1_state.m1_tx_wait_keyboard_ack ; m1_state.m1_tx_clk_l ; m1_state.m1_tx_clk_h ; m1_state.m1_tx_force_clk_l ; m1_state.m1_tx_wait_clk_h ; m1_state.m1_rx_clk_l ; m1_state.m1_rx_clk_h ;+--------------------------------------+-----------------------------------+------------------------------------+----------------------------+---------------------------------+---------------------------------+-----------------------------------+--------------------------------------+------------------------------+----------------------------------+----------------------+----------------------+----------------------------+---------------------------+----------------------+----------------------+; m1_state.m1_rx_clk_h ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;; m1_state.m1_rx_clk_l ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;; m1_state.m1_tx_wait_clk_h ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;; m1_state.m1_tx_force_clk_l ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;; m1_state.m1_tx_clk_h ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;; m1_state.m1_tx_clk_l ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;; m1_state.m1_tx_wait_keyboard_ack ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;; m1_state.m1_tx_done_recovery ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;; m1_state.m1_tx_error_no_keyboard_ack ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;; m1_state.m1_tx_rising_edge_marker ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;; m1_state.m1_tx_first_wait_clk_h ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;; m1_state.m1_tx_first_wait_clk_l ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;; m1_state.m1_tx_reset_timer ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;; m1_state.m1_rx_falling_edge_marker ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;; m1_state.m1_rx_rising_edge_marker ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;+--------------------------------------+-----------------------------------+------------------------------------+----------------------------+---------------------------------+---------------------------------+-----------------------------------+--------------------------------------+------------------------------+----------------------------------+----------------------+----------------------+----------------------------+---------------------------+----------------------+----------------------+Encoding Type: One-Hot+-----------------------------------------------------------------------------+; State Machine - |CII_Starter_USB_API|Multi_Sdram:u3|Sdram_Multiplexer:u0|ST ;+-------+-------+-------+-------+---------------------------------------------+; Name ; ST.11 ; ST.10 ; ST.01 ; ST.00 ;+-------+-------+-------+-------+---------------------------------------------+; ST.00 ; 0 ; 0 ; 0 ; 0 ;; ST.01 ; 0 ; 0 ; 1 ; 1 ;; ST.10 ; 0 ; 1 ; 0 ; 1 ;; ST.11 ; 1 ; 0 ; 0 ; 1 ;+-------+-------+-------+-------+---------------------------------------------+Encoding Type: One-Hot+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; State Machine - |CII_Starter_USB_API|Multi_Flash:u2|Flash_Controller:u1|ST ;+---------------+----------+---------+---------------+---------------+---------------+-----------+-----------+-----------+-------+-------+-------+-------+-------+---------+; Name ; ST.RESET ; ST.READ ; ST.P6_CHP_ERA ; ST.P6_SEC_ERA ; ST.P6_BLK_ERA ; ST.P4_PRG ; ST.P3_DEV ; ST.P3_PRG ; ST.P5 ; ST.P4 ; ST.P3 ; ST.P2 ; ST.P1 ; ST.IDEL ;+---------------+----------+---------+---------------+---------------+---------------+-----------+-----------+-----------+-------+-------+-------+-------+-------+---------+; ST.IDEL ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;; ST.P1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;; ST.P2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;; ST.P3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;; ST.P4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;; ST.P5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;; ST.P3_PRG ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;; ST.P3_DEV ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;; ST.P4_PRG ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;; ST.P6_BLK_ERA ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;; ST.P6_SEC_ERA ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;; ST.P6_CHP_ERA ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;; ST.READ ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;; ST.RESET ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;+---------------+----------+---------+---------------+---------------+---------------+-----------+-----------+-----------+-------+-------+-------+-------+-------+---------+Encoding Type: One-Hot+-----------------------------------------------------------------------------+; State Machine - |CII_Starter_USB_API|Multi_Flash:u2|Flash_Multiplexer:u0|ST ;+-------+-------+-------+-------+---------------------------------------------+; Name ; ST.11 ; ST.10 ; ST.01 ; ST.00 ;+-------+-------+-------+-------+---------------------------------------------+; ST.00 ; 0 ; 0 ; 0 ; 0 ;; ST.01 ; 0 ; 0 ; 1 ; 1 ;; ST.10 ; 0 ; 1 ; 0 ; 1 ;; ST.11 ; 1 ; 0 ; 0 ; 1 ;+-------+-------+-------+-------+---------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------+; Registers Removed During Synthesis ;+-------------------------------------------------------------------------+-------------------------------------------------------------------------+; Register name ; Reason for Removal ;+-------------------------------------------------------------------------+-------------------------------------------------------------------------+; AUDIO_DAC:u11|SDRAM_Out_Tmp[0..15] ; Stuck at GND due to stuck port data_in ;; AUDIO_DAC:u11|SDRAM_Out[0..15] ; Stuck at GND due to stuck port data_in ;; AUDIO_DAC:u11|SRAM_Out_Tmp[0..15] ; Stuck at GND due to stuck port data_in ;; AUDIO_DAC:u11|SRAM_Out[0..15] ; Stuck at GND due to stuck port data_in ;; CMD_Decode:u5|oFL_CMD[1] ; Stuck at GND due to stuck port data_in ;; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[22] ; Stuck at GND due to stuck port data_in ;; Multi_Flash:u2|Flash_Controller:u1|CMD_Period[10..11,18,20..21] ; Stuck at GND due to stuck port data_in ;; I2C_AV_Config:u10|mI2C_DATA[22..23] ; Stuck at GND due to stuck port data_in ;; I2C_AV_Config:u10|mI2C_DATA[20..21] ; Stuck at VCC due to stuck port data_in ;; I2C_AV_Config:u10|mI2C_DATA[19] ; Stuck at GND due to stuck port data_in ;; I2C_AV_Config:u10|mI2C_DATA[18] ; Stuck at VCC due to stuck port data_in ;; I2C_AV_Config:u10|mI2C_DATA[8,13..17] ; Stuck at GND due to stuck port data_in ;; I2C_AV_Config:u10|I2C_Controller:u0|SD[22..23] ; Stuck at GND due to stuck port data_in ;; I2C_AV_Config:u10|I2C_Controller:u0|SD[20..21] ; Stuck at VCC due to stuck port data_in ;; I2C_AV_Config:u10|I2C_Controller:u0|SD[19] ; Stuck at GND due to stuck port data_in ;; I2C_AV_Config:u10|I2C_Controller:u0|SD[18] ; Stuck at VCC due to stuck port data_in ;; I2C_AV_Config:u10|I2C_Controller:u0|SD[8,13..17] ; Stuck at GND due to stuck port data_in ;; ps2_keyboard:u4|hold_released ; Stuck at GND due to stuck port data_in ;; Multi_Flash:u2|Flash_Controller:u1|r_CMD[1] ; Stuck at GND due to stuck port data_in ;; CMD_Decode:u5|mSR_WRn ; Merged with CMD_Decode:u5|mSDR_WRn ;; Multi_Sdram:u3|Sdram_Controller:u1|command:command1|CKE ; Merged with Multi_Sdram:u3|Sdram_Controller:u1|command:command1|CS_N[0] ;; Multi_Flash:u2|Flash_Controller:u1|WE_CLK_Delay[0] ; Merged with Multi_Flash:u2|Flash_Controller:u1|mCLK ;; Multi_Flash:u2|Flash_Controller:u1|pre_mCLK ; Merged with Multi_Flash:u2|Flash_Controller:u1|WE_CLK_Delay[1] ;; ps2_keyboard:u4|rx_ascii[7] ; Stuck at GND due to stuck port data_in ;; CMD_Decode:u5|oPS2_TXD_DATA[7] ; Stuck at GND due to stuck port data_in ;; Multi_Flash:u2|Flash_Controller:u1|CMD_Period[12..13,17] ; Stuck at GND due to stuck port data_in ;; I2C_AV_Config:u10|mI2C_DATA[5] ; Merged with I2C_AV_Config:u10|mI2C_DATA[6] ;; I2C_AV_Config:u10|mI2C_DATA[3] ; Merged with I2C_AV_Config:u10|mI2C_DATA[4] ;; I2C_AV_Config:u10|I2C_Controller:u0|SD[5] ; Merged with I2C_AV_Config:u10|I2C_Controller:u0|SD[6] ;; I2C_AV_Config:u10|I2C_Controller:u0|SD[3] ; Merged with I2C_AV_Config:u10|I2C_Controller:u0|SD[4] ;; VGA_OSD_RAM:u9|oRed[6..8] ; Merged with VGA_OSD_RAM:u9|oRed[9] ;; VGA_OSD_RAM:u9|oGreen[6..9] ; Merged with VGA_OSD_RAM:u9|oRed[9] ;; VGA_OSD_RAM:u9|oBlue[6..8] ; Merged with VGA_OSD_RAM:u9|oRed[9] ;; Multi_Flash:u2|Flash_Controller:u1|CMD_Period[3..8,14..16,19] ; Merged with Multi_Flash:u2|Flash_Controller:u1|CMD_Period[9] ;; Multi_Flash:u2|Flash_Controller:u1|CMD_Period[0] ; Merged with Multi_Flash:u2|Flash_Controller:u1|CMD_Period[1] ;; Multi_Sdram:u3|Sdram_Multiplexer:u0|mSDR_WR ; Stuck at GND due to stuck port data_in ;; ps2_keyboard:u4|m1_state.m1_tx_reset_timer ; Lost fanout ;; CMD_Decode:u5|mSR_ST~36 ; Lost fanout ;; CMD_Decode:u5|mSR_ST~37 ; Lost fanout ;; CMD_Decode:u5|mSR_ST~38 ; Lost fanout ;; CMD_Decode:u5|mSDR_ST~44 ; Lost fanout ;; CMD_Decode:u5|mSDR_ST~45 ; Lost fanout ;; CMD_Decode:u5|mSDR_ST~46 ; Lost fanout ;; CMD_Decode:u5|mPS2_ST~21 ; Lost fanout ;; CMD_Decode:u5|mPS2_ST~22 ; Lost fanout ;; CMD_Decode:u5|mFL_ST~54 ; Lost fanout ;; CMD_Decode:u5|mFL_ST~55 ; Lost fanout ;; CMD_Decode:u5|mFL_ST~56 ; Lost fanout ;; ps2_keyboard:u4|m1_state~20 ; Lost fanout ;; ps2_keyboard:u4|m1_state~21 ; Lost fanout ;; ps2_keyboard:u4|m1_state~22 ; Lost fanout ;; ps2_keyboard:u4|m1_state~23 ; Lost fanout ;; Multi_Sdram:u3|Sdram_Multiplexer:u0|ST~25 ; Lost fanout ;; Multi_Sdram:u3|Sdram_Multiplexer:u0|ST~26 ; Lost fanout ;; Multi_Flash:u2|Flash_Controller:u1|ST~66 ; Lost fanout ;; Multi_Flash:u2|Flash_Controller:u1|ST~67 ; Lost fanout ;; Multi_Flash:u2|Flash_Controller:u1|ST~68 ; Lost fanout ;; Multi_Flash:u2|Flash_Controller:u1|ST~69 ; Lost fanout ;; Multi_Flash:u2|Flash_Multiplexer:u0|ST~25 ; Lost fanout ;; Multi_Flash:u2|Flash_Multiplexer:u0|ST~26 ; Lost fanout ;; Multi_Flash:u2|Flash_Controller:u1|ST.P6_BLK_ERA ; Stuck at GND due to stuck port data_in ;; Multi_Flash:u2|Flash_Controller:u1|ST.P6_SEC_ERA ; Stuck at GND due to stuck port data_in ;; Multi_Flash:u2|Flash_Controller:u1|ST.RESET ; Stuck at GND due to stuck port data_in ;; ps2_keyboard:u4|m1_state.m1_tx_force_clk_l ; Stuck at GND due to stuck port data_in ;; ps2_keyboard:u4|m1_state.m1_tx_first_wait_clk_h ; Stuck at GND due to stuck port data_in ;; ps2_keyboard:u4|m1_state.m1_tx_first_wait_clk_l ; Stuck at GND due to stuck port data_in ;; Multi_Flash:u2|Flash_Controller:u1|Cont_DIV[3..10] ; Lost fanout ;; AUDIO_DAC:u11|BCK_DIV[3] ; Stuck at GND due to stuck port data_in ;; VGA_OSD_RAM:u9|oRed[9] ; Lost fanout ;; Total Number of Removed Registers = 172 ; ;+-------------------------------------------------------------------------+-------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------+; Removed Registers Triggering Further Register Optimizations ;+---------------------------------+---------------------------+----------------------------------------------------+; Register name ; Reason for Removal ; Registers Removed due to This Register ;+---------------------------------+---------------------------+----------------------------------------------------+; CMD_Decode:u5|oFL_CMD[1] ; Stuck at GND ; Multi_Flash:u2|Flash_Controller:u1|r_CMD[1], ;; ; due to stuck port data_in ; Multi_Flash:u2|Flash_Controller:u1|CMD_Period[12], ;; ; ; Multi_Flash:u2|Flash_Controller:u1|CMD_Period[13], ;; ; ; Multi_Flash:u2|Flash_Controller:u1|CMD_Period[17] ;; AUDIO_DAC:u11|SDRAM_Out_Tmp[14] ; Stuck at GND ; AUDIO_DAC:u11|SDRAM_Out[14] ;; ; due to stuck port data_in ; ;; AUDIO_DAC:u11|SDRAM_Out_Tmp[13] ; Stuck at GND ; AUDIO_DAC:u11|SDRAM_Out[13] ;; ; due to stuck port data_in ; ;; AUDIO_DAC:u11|SDRAM_Out_Tmp[12] ; Stuck at GND ; AUDIO_DAC:u11|SDRAM_Out[12] ;; ; due to stuck port data_in ; ;; AUDIO_DAC:u11|SDRAM_Out_Tmp[11] ; Stuck at GND ; AUDIO_DAC:u11|SDRAM_Out[11] ;; ; due to stuck port data_in ; ;; AUDIO_DAC:u11|SDRAM_Out_Tmp[10] ; Stuck at GND ; AUDIO_DAC:u11|SDRAM_Out[10] ;; ; due to stuck port data_in ; ;; AUDIO_DAC:u11|SDRAM_Out_Tmp[9] ; Stuck at GND ; AUDIO_DAC:u11|SDRAM_Out[9] ;; ; due to stuck port data_in ; ;; AUDIO_DAC:u11|SDRAM_Out_Tmp[8] ; Stuck at GND ; AUDIO_DAC:u11|SDRAM_Out[8] ;; ; due to stuck port data_in ; ;; AUDIO_DAC:u11|SDRAM_Out_Tmp[7] ; Stuck at GND ; AUDIO_DAC:u11|SDRAM_Out[7] ;; ; due to stuck port data_in ; ;; AUDIO_DAC:u11|SDRAM_Out_Tmp[6] ; Stuck at GND ; AUDIO_DAC:u11|SDRAM_Out[6] ;; ; due to stuck port data_in ; ;; AUDIO_DAC:u11|SDRAM_Out_Tmp[5] ; Stuck at GND ; AUDIO_DAC:u11|SDRAM_Out[5] ;; ; due to stuck port data_in ; ;; AUDIO_DAC:u11|SDRAM_Out_Tmp[4] ; Stuck at GND ; AUDIO_DAC:u11|SDRAM_Out[4] ;; ; due to stuck port data_in ; ;; AUDIO_DAC:u11|SDRAM_Out_Tmp[3] ; Stuck at GND ; AUDIO_DAC:u11|SDRAM_Out[3] ;; ; due to stuck port data_in ; ;; AUDIO_DAC:u11|SDRAM_Out_Tmp[2] ; Stuck at GND ; AUDIO_DAC:u11|SDRAM_Out[2] ;; ; due to stuck port data_in ; ;; AUDIO_DAC:u11|SDRAM_Out_Tmp[1] ; Stuck at GND ; AUDIO_DAC:u11|SDRAM_Out[1] ;; ; due to stuck port data_in ; ;; AUDIO_DAC:u11|SDRAM_Out_Tmp[0] ; Stuck at GND ; AUDIO_DAC:u11|SDRAM_Out[0] ;; ; due to stuck port data_in ; ;; AUDIO_DAC:u11|SRAM_Out_Tmp[15] ; Stuck at GND ; AUDIO_DAC:u11|SRAM_Out[15] ;; ; due to stuck port data_in ; ;; AUDIO_DAC:u11|SRAM_Out_Tmp[14] ; Stuck at GND ; AUDIO_DAC:u11|SRAM_Out[14] ;; ; due to stuck port data_in ; ;; AUDIO_DAC:u11|SRAM_Out_Tmp[13] ; Stuck at GND ; AUDIO_DAC:u11|SRAM_Out[13] ;; ; due to stuck port data_in ; ;; AUDIO_DAC:u11|SRAM_Out_Tmp[12] ; Stuck at GND ; AUDIO_DAC:u11|SRAM_Out[12] ;; ; due to stuck port data_in ; ;; AUDIO_DAC:u11|SRAM_Out_Tmp[11] ; Stuck at GND ; AUDIO_DAC:u11|SRAM_Out[11] ;; ; due to stuck port data_in ; ;; AUDIO_DAC:u11|SRAM_Out_Tmp[10] ; Stuck at GND ; AUDIO_DAC:u11|SRAM_Out[10] ;; ; due to stuck port data_in ; ;; AUDIO_DAC:u11|SRAM_Out_Tmp[9] ; Stuck at GND ; AUDIO_DAC:u11|SRAM_Out[9] ;; ; due to stuck port data_in ; ;; AUDIO_DAC:u11|SRAM_Out_Tmp[8] ; Stuck at GND ; AUDIO_DAC:u11|SRAM_Out[8] ;; ; due to stuck port data_in ; ;; AUDIO_DAC:u11|SRAM_Out_Tmp[7] ; Stuck at GND ; AUDIO_DAC:u11|SRAM_Out[7] ;; ; due to stuck port data_in ; ;; AUDIO_DAC:u11|SRAM_Out_Tmp[6] ; Stuck at GND ; AUDIO_DAC:u11|SRAM_Out[6] ;; ; due to stuck port data_in ; ;; AUDIO_DAC:u11|SRAM_Out_Tmp[5] ; Stuck at GND ; AUDIO_DAC:u11|SRAM_Out[5] ;; ; due to stuck port data_in ; ;; AUDIO_DAC:u11|SRAM_Out_Tmp[4] ; Stuck at GND ; AUDIO_DAC:u11|SRAM_Out[4] ;; ; due to stuck port data_in ; ;; AUDIO_DAC:u11|SRAM_Out_Tmp[3] ; Stuck at GND ; AUDIO_DAC:u11|SRAM_Out[3] ;; ; due to stuck port data_in ; ;; AUDIO_DAC:u11|SRAM_Out_Tmp[2] ; Stuck at GND ; AUDIO_DAC:u11|SRAM_Out[2] ;; ; due to stuck port data_in ; ;; AUDIO_DAC:u11|SRAM_Out_Tmp[1] ; Stuck at GND ; AUDIO_DAC:u11|SRAM_Out[1] ;; ; due to stuck port data_in ; ;; AUDIO_DAC:u11|SRAM_Out_Tmp[0] ; Stuck at GND ; AUDIO_DAC:u11|SRAM_Out[0] ;; ; due to stuck port data_in ; ;; AUDIO_DAC:u11|SDRAM_Out_Tmp[15] ; Stuck at GND ; AUDIO_DAC:u11|SDRAM_Out[15] ;; ; due to stuck port data_in ; ;; I2C_AV_Config:u10|mI2C_DATA[23] ; Stuck at GND ; I2C_AV_Config:u10|I2C_Controller:u0|SD[23] ;; ; due to stuck port data_in ; ;; I2C_AV_Config:u10|mI2C_DATA[22] ; Stuck at GND ; I2C_AV_Config:u10|I2C_Controller:u0|SD[22] ;; ; due to stuck port data_in ; ;; I2C_AV_Config:u10|mI2C_DATA[21] ; Stuck at VCC ; I2C_AV_Config:u10|I2C_Controller:u0|SD[21] ;; ; due to stuck port data_in ; ;; I2C_AV_Config:u10|mI2C_DATA[20] ; Stuck at VCC ; I2C_AV_Config:u10|I2C_Controller:u0|SD[20] ;; ; due to stuck port data_in ; ;; I2C_AV_Config:u10|mI2C_DATA[19] ; Stuck at GND ; I2C_AV_Config:u10|I2C_Controller:u0|SD[19] ;; ; due to stuck port data_in ; ;; I2C_AV_Config:u10|mI2C_DATA[18] ; Stuck at VCC ; I2C_AV_Config:u10|I2C_Controller:u0|SD[18] ;; ; due to stuck port data_in ; ;; I2C_AV_Config:u10|mI2C_DATA[17] ; Stuck at GND ; I2C_AV_Config:u10|I2C_Controller:u0|SD[17] ;; ; due to stuck port data_in ; ;; I2C_AV_Config:u10|mI2C_DATA[16] ; Stuck at GND ; I2C_AV_Config:u10|I2C_Controller:u0|SD[16] ;; ; due to stuck port data_in ; ;; I2C_AV_Config:u10|mI2C_DATA[15] ; Stuck at GND ; I2C_AV_Config:u10|I2C_Controller:u0|SD[15] ;; ; due to stuck port data_in ; ;; I2C_AV_Config:u10|mI2C_DATA[14] ; Stuck at GND ; I2C_AV_Config:u10|I2C_Controller:u0|SD[14] ;; ; due to stuck port data_in ; ;; I2C_AV_Config:u10|mI2C_DATA[13] ; Stuck at GND ; I2C_AV_Config:u10|I2C_Controller:u0|SD[13] ;; ; due to stuck port data_in ; ;; I2C_AV_Config:u10|mI2C_DATA[8] ; Stuck at GND ; I2C_AV_Config:u10|I2C_Controller:u0|SD[8] ;; ; due to stuck port data_in ; ;+---------------------------------+---------------------------+----------------------------------------------------++------------------------------------------------------+; General Register Statistics ;+----------------------------------------------+-------+; Statistic ; Value ;+----------------------------------------------+-------+; Total registers ; 1033 ;; Number of registers using Synchronous Clear ; 177 ;; Number of registers using Synchronous Load ; 34 ;; Number of registers using Asynchronous Clear ; 648 ;; Number of registers using Asynchronous Load ; 0 ;; Number of registers using Clock Enable ; 574 ;; Number of registers using Preset ; 0 ;+----------------------------------------------+-------++-------------------------------------------------------------+; Inverted Register Statistics ;+---------------------------------------------------+---------+; Inverted Register ; Fan out ;+---------------------------------------------------+---------+; I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[0] ; 18 ;; I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[2] ; 14 ;; I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[3] ; 18 ;; I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[1] ; 13 ;; I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[4] ; 10 ;; I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[5] ; 11 ;; I2C_AV_Config:u10|I2C_Controller:u0|SCLK ; 2 ;; I2C_AV_Config:u10|I2C_Controller:u0|END ; 5 ;; I2C_AV_Config:u10|I2C_Controller:u0|SDO ; 4 ;; Total number of inverted registers = 9 ; ;+---------------------------------------------------+---------++--------------------------------------------------------------------------------------------------------------------------------------------------+; Gate-level Retiming ;+---------------------------------------------+----------------------------------------------------------------------------------+-----------------+; Register Name ; Clock Name ; Created/Deleted ;+---------------------------------------------+----------------------------------------------------------------------------------+-----------------+; VGA_OSD_RAM:u9|oRed[9] ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; Deleted ;; ps2_keyboard:u4|q[8]~33 ; CLOCK_50 ; Created ;; ps2_keyboard:u4|q[8]~34 ; CLOCK_50 ; Created ;; Multi_Sdram:u3|Sdram_Controller:u1|ST[5]~45 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Created ;; VGA_OSD_RAM:u9|oRed[9]~23 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; Created ;; VGA_OSD_RAM:u9|oRed[9]~24 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; Created ;; VGA_OSD_RAM:u9|oRed[9]~25 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; Created ;; VGA_OSD_RAM:u9|oRed[9]~26 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; Created ;; VGA_OSD_RAM:u9|oRed[9]~27 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; Created ;; VGA_OSD_RAM:u9|oRed[9]~28 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; Created ;; VGA_OSD_RAM:u9|oRed[9]~29 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; Created ;; VGA_OSD_RAM:u9|oRed[9]~30 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; Created ;; VGA_OSD_RAM:u9|oRed[9]~31 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; Created ;; VGA_OSD_RAM:u9|oRed[9]~32 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; Created ;; VGA_OSD_RAM:u9|oRed[9]~33 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; Created ;; VGA_OSD_RAM:u9|oRed[9]~34 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; Created ;; VGA_OSD_RAM:u9|oRed[9]~35 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; Created ;; VGA_OSD_RAM:u9|oRed[9]~36 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; Created ;; VGA_OSD_RAM:u9|oRed[9]~37 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; Created ;; VGA_OSD_RAM:u9|oRed[9]~38 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; Created ;; VGA_OSD_RAM:u9|oRed[9]~39 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; Created ;; VGA_OSD_RAM:u9|oRed[9]~40 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; Created ;; VGA_OSD_RAM:u9|oRed[9]~41 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; Created ;; VGA_OSD_RAM:u9|oRed[9]~42 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; Created ;; VGA_OSD_RAM:u9|oRed[9]~43 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; Created ;; VGA_OSD_RAM:u9|oRed[9]~44 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; Created ;; VGA_OSD_RAM:u9|oRed[9]~45 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; Created ;; VGA_OSD_RAM:u9|oRed[9]~46 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; Created ;+---------------------------------------------+----------------------------------------------------------------------------------+-----------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Multiplexer Restructuring Statistics (Restructuring Performed) ;+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------+; 3:1 ; 11 bits ; 22 LEs ; 11 LEs ; 11 LEs ; Yes ; |CII_Starter_USB_API|VGA_Controller:u8|Cur_Color_B[6] ;; 3:1 ; 10 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |CII_Starter_USB_API|ps2_keyboard:u4|q[8] ;; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |CII_Starter_USB_API|ps2_keyboard:u4|bit_count[0] ;; 3:1 ; 7 bits ; 14 LEs ; 7 LEs ; 7 LEs ; Yes ; |CII_Starter_USB_API|ps2_keyboard:u4|rx_ascii[0] ;; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |CII_Starter_USB_API|Multi_Sdram:u3|Sdram_Controller:u1|command:command1|BA[0] ;; 3:1 ; 16 bits ; 32 LEs ; 32 LEs ; 0 LEs ; Yes ; |CII_Starter_USB_API|Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[4] ;; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |CII_Starter_USB_API|Multi_Sdram:u3|Sdram_Controller:u1|command:command1|command_delay[6] ;; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |CII_Starter_USB_API|Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[9] ;; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |CII_Starter_USB_API|Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[1] ;; 3:1 ; 22 bits ; 44 LEs ; 44 LEs ; 0 LEs ; Yes ; |CII_Starter_USB_API|Multi_Flash:u2|Flash_Controller:u1|r_ADDR[13] ;; 5:1 ; 4 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |CII_Starter_USB_API|Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rp_done ;; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; Yes ; |CII_Starter_USB_API|CMD_Decode:u5|oSR_TXD_DATA[6] ;; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; Yes ; |CII_Starter_USB_API|CMD_Decode:u5|oSDR_TXD_DATA[1] ;; 6:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |CII_Starter_USB_API|Multi_Sdram:u3|Sdram_Controller:u1|CMD[1] ;; 256:1 ; 3 bits ; 510 LEs ; 6 LEs ; 504 LEs ; Yes ; |CII_Starter_USB_API|CMD_Decode:u5|sel_SDR ;; 7:1 ; 9 bits ; 36 LEs ; 18 LEs ; 18 LEs ; Yes ; |CII_Starter_USB_API|Multi_Sdram:u3|Sdram_Controller:u1|ST[5] ;; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |CII_Starter_USB_API|Multi_Flash:u2|Flash_Controller:u1|ST~46 ;; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |CII_Starter_USB_API|CMD_Decode:u5|mPS2_ST~5 ;; 3:1 ; 18 bits ; 36 LEs ; 36 LEs ; 0 LEs ; No ; |CII_Starter_USB_API|Multi_Sram:u6|SRAM_ADDR[10] ;; 4:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |CII_Starter_USB_API|Multi_Flash:u2|Flash_Controller:u1|Selector12 ;; 5:1 ; 3 bits ; 9 LEs ; 9 LEs ; 0 LEs ; No ; |CII_Starter_USB_API|mVGA_R[8] ;; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |CII_Starter_USB_API|Multi_Flash:u2|Flash_Controller:u1|ST~54 ;; 5:1 ; 3 bits ; 9 LEs ; 6 LEs ; 3 LEs ; No ; |CII_Starter_USB_API|Multi_Flash:u2|Flash_Controller:u1|ST~51 ;+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------++-----------------------------------------------------------------------------------------------------------------+; Source assignments for VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated ;+---------------------------------+--------------------+------+---------------------------------------------------+; Assignment ; Value ; From ; To ;+---------------------------------+--------------------+------+---------------------------------------------------+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;+---------------------------------+--------------------+------+---------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1 ;+---------------------------------+--------------------+------+-------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+---------------------------------+--------------------+------+-------------------------------------------------------------------------------+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;+---------------------------------+--------------------+------+-------------------------------------------------------------------------------++---------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: Multi_Flash:u2|Flash_Controller:u1 ;+----------------+--------+-------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+--------+-------------------------------------------------------+; CMD_READ ; 000 ; Unsigned Binary ;; CMD_WRITE ; 001 ; Unsigned Binary ;; CMD_BLK_ERA ; 010 ; Unsigned Binary ;; CMD_SEC_ERA ; 011 ; Unsigned Binary ;; CMD_CHP_ERA ; 100 ; Unsigned Binary ;; CMD_ENTRY_ID ; 101 ; Unsigned Binary ;; CMD_RESET ; 110 ; Unsigned Binary ;; PER_READ ; 1 ; Signed Integer ;; PER_WRITE ; 5 ; Signed Integer ;; PER_BLK_ERA ; 160000 ; Signed Integer ;; PER_SEC_ERA ; 160000 ; Signed Integer ;; PER_CHP_ERA ; 640000 ; Signed Integer ;; PER_ENTRY_ID ; 4 ; Signed Integer ;; PER_RESET ; 1 ; Signed Integer ;; IDEL ; 0 ; Signed Integer ;; P1 ; 1 ; Signed Integer ;; P2 ; 2 ; Signed Integer ;; P3 ; 3 ; Signed Integer ;; P4 ; 4 ; Signed Integer ;; P5 ; 5 ; Signed Integer ;; P3_PRG ; 6 ; Signed Integer ;; P3_DEV ; 7 ; Signed Integer ;; P4_PRG ; 8 ; Signed Integer ;; P6_BLK_ERA ; 9 ; Signed Integer ;; P6_SEC_ERA ; 10 ; Signed Integer ;; P6_CHP_ERA ; 11 ; Signed Integer ;; READ ; 12 ; Signed Integer ;; RESET ; 13 ; Signed Integer ;; CLK_Divide ; 8 ; Signed Integer ;+----------------+--------+-------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: Multi_Sdram:u3|Sdram_Controller:u1 ;+----------------+-------+--------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------+; INIT_PER ; 24000 ; Signed Integer ;; REF_PER ; 1024 ; Signed Integer ;; SC_CL ; 3 ; Signed Integer ;; SC_RCD ; 3 ; Signed Integer ;; SC_RRD ; 7 ; Signed Integer ;; SC_PM ; 1 ; Signed Integer ;; SC_BL ; 1 ; Signed Integer ;; SDR_BL ; 111 ; Unsigned Binary ;; SDR_BT ; 0 ; Unsigned Binary ;; SDR_CL ; 011 ; Unsigned Binary ;+----------------+-------+--------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component ;+-------------------------------+-------------------+---------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------------------+-------------------+---------------------------------------------------------------------+; OPERATION_MODE ; NORMAL ; Untyped ;; PLL_TYPE ; FAST ; Untyped ;; QUALIFY_CONF_DONE ; OFF ; Untyped ;; COMPENSATE_CLOCK ; CLK0 ; Untyped ;; SCAN_CHAIN ; LONG ; Untyped ;; PRIMARY_CLOCK ; INCLK0 ; Untyped ;; INCLK0_INPUT_FREQUENCY ; 20000 ; Signed Integer ;; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ;; GATE_LOCK_SIGNAL ; NO ; Untyped ;; GATE_LOCK_COUNTER ; 0 ; Untyped ;; LOCK_HIGH ; 1 ; Untyped ;; LOCK_LOW ; 1 ; Untyped ;; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ;; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ;; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ;; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ;; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ;; SKIP_VCO ; OFF ; Untyped ;; SWITCH_OVER_COUNTER ; 0 ; Untyped ;; SWITCH_OVER_TYPE ; AUTO ; Untyped ;; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ;; BANDWIDTH ; 0 ; Untyped ;; BANDWIDTH_TYPE ; AUTO ; Untyped ;; SPREAD_FREQUENCY ; 0 ; Untyped ;; DOWN_SPREAD ; 0 ; Untyped ;; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ;; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ;; CLK9_MULTIPLY_BY ; 0 ; Untyped ;; CLK8_MULTIPLY_BY ; 0 ; Untyped ;; CLK7_MULTIPLY_BY ; 0 ; Untyped ;; CLK6_MULTIPLY_BY ; 0 ; Untyped ;; CLK5_MULTIPLY_BY ; 1 ; Untyped ;; CLK4_MULTIPLY_BY ; 1 ; Untyped ;; CLK3_MULTIPLY_BY ; 1 ; Untyped ;; CLK2_MULTIPLY_BY ; 1 ; Signed Integer ;; CLK1_MULTIPLY_BY ; 1 ; Untyped ;; CLK0_MULTIPLY_BY ; 1 ; Signed Integer ;; CLK9_DIVIDE_BY ; 0 ; Untyped ;; CLK8_DIVIDE_BY ; 0 ; Untyped ;; CLK7_DIVIDE_BY ; 0 ; Untyped ;; CLK6_DIVIDE_BY ; 0 ; Untyped ;; CLK5_DIVIDE_BY ; 1 ; Untyped ;; CLK4_DIVIDE_BY ; 1 ; Untyped ;; CLK3_DIVIDE_BY ; 1 ; Untyped ;; CLK2_DIVIDE_BY ; 1 ; Signed Integer ;; CLK1_DIVIDE_BY ; 1 ; Untyped ;; CLK0_DIVIDE_BY ; 1 ; Signed Integer ;; CLK9_PHASE_SHIFT ; 0 ; Untyped ;; CLK8_PHASE_SHIFT ; 0 ; Untyped ;; CLK7_PHASE_SHIFT ; 0 ; Untyped ;; CLK6_PHASE_SHIFT ; 0 ; Untyped ;; CLK5_PHASE_SHIFT ; 0 ; Untyped ;; CLK4_PHASE_SHIFT ; 0 ; Untyped ;; CLK3_PHASE_SHIFT ; 0 ; Untyped ;; CLK2_PHASE_SHIFT ; 0 ; Untyped ;; CLK1_PHASE_SHIFT ; 0 ; Untyped ;; CLK0_PHASE_SHIFT ; 0 ; Untyped ;; CLK5_TIME_DELAY ; 0 ; Untyped ;; CLK4_TIME_DELAY ; 0 ; Untyped ;; CLK3_TIME_DELAY ; 0 ; Untyped ;; CLK2_TIME_DELAY ; 0 ; Untyped ;; CLK1_TIME_DELAY ; 0 ; Untyped ;; CLK0_TIME_DELAY ; 0 ; Untyped ;; CLK9_DUTY_CYCLE ; 50 ; Untyped ;; CLK8_DUTY_CYCLE ; 50 ; Untyped ;; CLK7_DUTY_CYCLE ; 50 ; Untyped ;; CLK6_DUTY_CYCLE ; 50 ; Untyped ;; CLK5_DUTY_CYCLE ; 50 ; Untyped ;; CLK4_DUTY_CYCLE ; 50 ; Untyped ;; CLK3_DUTY_CYCLE ; 50 ; Untyped ;; CLK2_DUTY_CYCLE ; 50 ; Signed Integer ;; CLK1_DUTY_CYCLE ; 50 ; Untyped ;; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ;; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;; LOCK_WINDOW_UI ; 0.05 ; Untyped ;; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ;; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ;; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ;; DPA_MULTIPLY_BY ; 0 ; Untyped ;; DPA_DIVIDE_BY ; 1 ; Untyped ;; DPA_DIVIDER ; 0 ; Untyped ;; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ;; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ;; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ;; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ;; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ;; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ;; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ;; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ;; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ;; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ;; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ;; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ;; EXTCLK3_TIME_DELAY ; 0 ; Untyped ;; EXTCLK2_TIME_DELAY ; 0 ; Untyped ;; EXTCLK1_TIME_DELAY ; 0 ; Untyped ;; EXTCLK0_TIME_DELAY ; 0 ; Untyped ;; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ;; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ;; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ;; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ;; VCO_MULTIPLY_BY ; 0 ; Untyped ;; VCO_DIVIDE_BY ; 0 ; Untyped ;; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ;; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ;; VCO_MIN ; 0 ; Untyped ;; VCO_MAX ; 0 ; Untyped ;; VCO_CENTER ; 0 ; Untyped ;; PFD_MIN ; 0 ; Untyped ;; PFD_MAX ; 0 ; Untyped ;; M_INITIAL ; 0 ; Untyped ;; M ; 0 ; Untyped ;; N ; 1 ; Untyped ;; M2 ; 1 ; Untyped ;; N2 ; 1 ; Untyped ;; SS ; 1 ; Untyped ;; C0_HIGH ; 0 ; Untyped ;; C1_HIGH ; 0 ; Untyped ;; C2_HIGH ; 0 ; Untyped ;; C3_HIGH ; 0 ; Untyped ;; C4_HIGH ; 0 ; Untyped ;; C5_HIGH ; 0 ; Untyped ;; C6_HIGH ; 0 ; Untyped ;; C7_HIGH ; 0 ; Untyped ;; C8_HIGH ; 0 ; Untyped ;; C9_HIGH ; 0 ; Untyped ;; C0_LOW ; 0 ; Untyped ;; C1_LOW ; 0 ; Untyped ;; C2_LOW ; 0 ; Untyped ;; C3_LOW ; 0 ; Untyped ;; C4_LOW ; 0 ; Untyped ;; C5_LOW ; 0 ; Untyped ;; C6_LOW ; 0 ; Untyped ;; C7_LOW ; 0 ; Untyped ;; C8_LOW ; 0 ; Untyped ;; C9_LOW ; 0 ; Untyped ;; C0_INITIAL ; 0 ; Untyped ;; C1_INITIAL ; 0 ; Untyped ;; C2_INITIAL ; 0 ; Untyped ;; C3_INITIAL ; 0 ; Untyped ;; C4_INITIAL ; 0 ; Untyped ;; C5_INITIAL ; 0 ; Untyped ;; C6_INITIAL ; 0 ; Untyped ;; C7_INITIAL ; 0 ; Untyped ;; C8_INITIAL ; 0 ; Untyped ;; C9_INITIAL ; 0 ; Untyped ;; C0_MODE ; BYPASS ; Untyped ;; C1_MODE ; BYPASS ; Untyped ;; C2_MODE ; BYPASS ; Untyped ;; C3_MODE ; BYPASS ; Untyped ;; C4_MODE ; BYPASS ; Untyped ;; C5_MODE ; BYPASS ; Untyped ;; C6_MODE ; BYPASS ; Untyped ;; C7_MODE ; BYPASS ; Untyped ;; C8_MODE ; BYPASS ; Untyped ;; C9_MODE ; BYPASS ; Untyped ;; C0_PH ; 0 ; Untyped ;; C1_PH ; 0 ; Untyped ;; C2_PH ; 0 ; Untyped ;; C3_PH ; 0 ; Untyped ;; C4_PH ; 0 ; Untyped ;; C5_PH ; 0 ; Untyped ;; C6_PH ; 0 ; Untyped ;; C7_PH ; 0 ; Untyped ;; C8_PH ; 0 ; Untyped ;; C9_PH ; 0 ; Untyped ;; L0_HIGH ; 1 ; Untyped ;; L1_HIGH ; 1 ; Untyped ;; G0_HIGH ; 1 ; Untyped ;; G1_HIGH ; 1 ; Untyped ;; G2_HIGH ; 1 ; Untyped ;; G3_HIGH ; 1 ; Untyped ;; E0_HIGH ; 1 ; Untyped ;; E1_HIGH ; 1 ; Untyped ;; E2_HIGH ; 1 ; Untyped ;; E3_HIGH ; 1 ; Untyped ;; L0_LOW ; 1 ; Untyped ;; L1_LOW ; 1 ; Untyped ;; G0_LOW ; 1 ; Untyped ;; G1_LOW ; 1 ; Untyped ;; G2_LOW ; 1 ; Untyped ;; G3_LOW ; 1 ; Untyped ;; E0_LOW ; 1 ; Untyped ;; E1_LOW ; 1 ; Untyped ;; E2_LOW ; 1 ; Untyped ;; E3_LOW ; 1 ; Untyped ;; L0_INITIAL ; 1 ; Untyped ;; L1_INITIAL ; 1 ; Untyped ;; G0_INITIAL ; 1 ; Untyped ;; G1_INITIAL ; 1 ; Untyped ;; G2_INITIAL ; 1 ; Untyped ;; G3_INITIAL ; 1 ; Untyped ;; E0_INITIAL ; 1 ; Untyped ;; E1_INITIAL ; 1 ; Untyped ;; E2_INITIAL ; 1 ; Untyped ;; E3_INITIAL ; 1 ; Untyped ;; L0_MODE ; BYPASS ; Untyped ;; L1_MODE ; BYPASS ; Untyped ;; G0_MODE ; BYPASS ; Untyped ;; G1_MODE ; BYPASS ; Untyped ;; G2_MODE ; BYPASS ; Untyped ;; G3_MODE ; BYPASS ; Untyped ;; E0_MODE ; BYPASS ; Untyped ;; E1_MODE ; BYPASS ; Untyped ;; E2_MODE ; BYPASS ; Untyped ;; E3_MODE ; BYPASS ; Untyped ;; L0_PH ; 0 ; Untyped ;; L1_PH ; 0 ; Untyped ;; G0_PH ; 0 ; Untyped ;; G1_PH ; 0 ; Untyped ;; G2_PH ; 0 ; Untyped ;; G3_PH ; 0 ; Untyped ;; E0_PH ; 0 ; Untyped ;; E1_PH ; 0 ; Untyped ;; E2_PH ; 0 ; Untyped ;; E3_PH ; 0 ; Untyped ;; M_PH ; 0 ; Untyped ;; C1_USE_CASC_IN ; OFF ; Untyped ;; C2_USE_CASC_IN ; OFF ; Untyped ;; C3_USE_CASC_IN ; OFF ; Untyped ;; C4_USE_CASC_IN ; OFF ; Untyped ;; C5_USE_CASC_IN ; OFF ; Untyped ;; C6_USE_CASC_IN ; OFF ; Untyped ;; C7_USE_CASC_IN ; OFF ; Untyped ;; C8_USE_CASC_IN ; OFF ; Untyped ;; C9_USE_CASC_IN ; OFF ; Untyped ;; CLK0_COUNTER ; G0 ; Untyped ;; CLK1_COUNTER ; G0 ; Untyped ;; CLK2_COUNTER ; G0 ; Untyped ;; CLK3_COUNTER ; G0 ; Untyped ;; CLK4_COUNTER ; G0 ; Untyped ;; CLK5_COUNTER ; G0 ; Untyped ;; CLK6_COUNTER ; E0 ; Untyped ;; CLK7_COUNTER ; E1 ; Untyped ;; CLK8_COUNTER ; E2 ; Untyped ;; CLK9_COUNTER ; E3 ; Untyped ;; L0_TIME_DELAY ; 0 ; Untyped ;; L1_TIME_DELAY ; 0 ; Untyped ;; G0_TIME_DELAY ; 0 ; Untyped ;; G1_TIME_DELAY ; 0 ; Untyped ;; G2_TIME_DELAY ; 0 ; Untyped ;; G3_TIME_DELAY ; 0 ; Untyped ;; E0_TIME_DELAY ; 0 ; Untyped ;; E1_TIME_DELAY ; 0 ; Untyped ;; E2_TIME_DELAY ; 0 ; Untyped ;; E3_TIME_DELAY ; 0 ; Untyped ;; M_TIME_DELAY ; 0 ; Untyped ;; N_TIME_DELAY ; 0 ; Untyped ;; EXTCLK3_COUNTER ; E3 ; Untyped ;; EXTCLK2_COUNTER ; E2 ; Untyped ;; EXTCLK1_COUNTER ; E1 ; Untyped ;; EXTCLK0_COUNTER ; E0 ; Untyped ;; ENABLE0_COUNTER ; L0 ; Untyped ;; ENABLE1_COUNTER ; L0 ; Untyped ;; CHARGE_PUMP_CURRENT ; 2 ; Untyped ;; LOOP_FILTER_R ; 1.000000 ; Untyped ;; LOOP_FILTER_C ; 5 ; Untyped ;; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ;; LOOP_FILTER_R_BITS ; 9999 ; Untyped ;; LOOP_FILTER_C_BITS ; 9999 ; Untyped ;; VCO_POST_SCALE ; 0 ; Untyped ;; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ;; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ;; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ;; INTENDED_DEVICE_FAMILY ; Cyclone II ; Untyped ;; PORT_CLKENA0 ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLKENA1 ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLKENA2 ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLKENA3 ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLKENA4 ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLKENA5 ; PORT_CONNECTIVITY ; Untyped ;; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ;; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ;; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ;; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ;; PORT_EXTCLK0 ; PORT_CONNECTIVITY ; Untyped ;; PORT_EXTCLK1 ; PORT_CONNECTIVITY ; Untyped ;; PORT_EXTCLK2 ; PORT_CONNECTIVITY ; Untyped ;; PORT_EXTCLK3 ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLKBAD0 ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLKBAD1 ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLK0 ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLK1 ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLK2 ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLK3 ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLK4 ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLK5 ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLK6 ; PORT_UNUSED ; Untyped ;; PORT_CLK7 ; PORT_UNUSED ; Untyped ;; PORT_CLK8 ; PORT_UNUSED ; Untyped ;; PORT_CLK9 ; PORT_UNUSED ; Untyped ;; PORT_SCANDATA ; PORT_CONNECTIVITY ; Untyped ;; PORT_SCANDATAOUT ; PORT_CONNECTIVITY ; Untyped ;; PORT_SCANDONE ; PORT_CONNECTIVITY ; Untyped ;; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ;; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ;; PORT_ACTIVECLOCK ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLKLOSS ; PORT_CONNECTIVITY ; Untyped ;; PORT_INCLK1 ; PORT_CONNECTIVITY ; Untyped ;; PORT_INCLK0 ; PORT_CONNECTIVITY ; Untyped ;; PORT_FBIN ; PORT_CONNECTIVITY ; Untyped ;; PORT_PLLENA ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLKSWITCH ; PORT_CONNECTIVITY ; Untyped ;; PORT_ARESET ; PORT_CONNECTIVITY ; Untyped ;; PORT_PFDENA ; PORT_CONNECTIVITY ; Untyped ;; PORT_SCANCLK ; PORT_CONNECTIVITY ; Untyped ;; PORT_SCANACLR ; PORT_CONNECTIVITY ; Untyped ;; PORT_SCANREAD ; PORT_CONNECTIVITY ; Untyped ;; PORT_SCANWRITE ; PORT_CONNECTIVITY ; Untyped ;; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ;; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ;; PORT_LOCKED ; PORT_CONNECTIVITY ; Untyped ;; PORT_CONFIGUPDATE ; PORT_CONNECTIVITY ; Untyped ;; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ;; PORT_PHASEDONE ; PORT_CONNECTIVITY ; Untyped ;; PORT_PHASESTEP ; PORT_CONNECTIVITY ; Untyped ;; PORT_PHASEUPDOWN ; PORT_CONNECTIVITY ; Untyped ;; PORT_SCANCLKENA ; PORT_CONNECTIVITY ; Untyped ;; PORT_PHASECOUNTERSELECT ; PORT_CONNECTIVITY ; Untyped ;; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ;; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ;; M_TEST_SOURCE ; 5 ; Untyped ;; C0_TEST_SOURCE ; 5 ; Untyped ;; C1_TEST_SOURCE ; 5 ; Untyped ;; C2_TEST_SOURCE ; 5 ; Untyped ;; C3_TEST_SOURCE ; 5 ; Untyped ;; C4_TEST_SOURCE ; 5 ; Untyped ;; C5_TEST_SOURCE ; 5 ; Untyped ;; C6_TEST_SOURCE ; 5 ; Untyped ;; C7_TEST_SOURCE ; 5 ; Untyped ;; C8_TEST_SOURCE ; 5 ; Untyped ;; C9_TEST_SOURCE ; 5 ; Untyped ;; CBXI_PARAMETER ; NOTHING ; Untyped ;; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ;; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ;; WIDTH_CLOCK ; 6 ; Untyped ;; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ;; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ;; DEVICE_FAMILY ; Cyclone II ; Untyped ;; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ;; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ;; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;+-------------------------------+-------------------+---------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1 ;+----------------+-------+-----------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------+; INIT_PER ; 24000 ; Signed Integer ;; REF_PER ; 1024 ; Signed Integer ;; SC_CL ; 3 ; Signed Integer ;; SC_RCD ; 3 ; Signed Integer ;; SC_RRD ; 7 ; Signed Integer ;; SC_PM ; 1 ; Signed Integer ;; SC_BL ; 1 ; Signed Integer ;; SDR_BL ; 111 ; Unsigned Binary ;; SDR_BT ; 0 ; Unsigned Binary ;; SDR_CL ; 011 ; Unsigned Binary ;+----------------+-------+-----------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: Multi_Sdram:u3|Sdram_Controller:u1|command:command1 ;+----------------+-------+-------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------+; INIT_PER ; 24000 ; Signed Integer ;; REF_PER ; 1024 ; Signed Integer ;; SC_CL ; 3 ; Signed Integer ;; SC_RCD ; 3 ; Signed Integer ;; SC_RRD ; 7 ; Signed Integer ;; SC_PM ; 1 ; Signed Integer ;; SC_BL ; 1 ; Signed Integer ;; SDR_BL ; 111 ; Unsigned Binary ;; SDR_BT ; 0 ; Unsigned Binary ;; SDR_CL ; 011 ; Unsigned Binary ;+----------------+-------+-------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1 ;+----------------+-------+---------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------+; INIT_PER ; 24000 ; Signed Integer ;; REF_PER ; 1024 ; Signed Integer ;; SC_CL ; 3 ; Signed Integer ;; SC_RCD ; 3 ; Signed Integer ;; SC_RRD ; 7 ; Signed Integer ;; SC_PM ; 1 ; Signed Integer ;; SC_BL ; 1 ; Signed Integer ;; SDR_BL ; 111 ; Unsigned Binary ;; SDR_BT ; 0 ; Unsigned Binary ;; SDR_CL ; 011 ; Unsigned Binary ;+----------------+-------+---------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------+; Parameter Settings for User Entity Instance: ps2_keyboard:u4 ;+-----------------------------+-------+------------------------+; Parameter Name ; Value ; Type ;+-----------------------------+-------+------------------------+; TIMER_60USEC_VALUE_PP ; 2950 ; Signed Integer ;; TIMER_60USEC_BITS_PP ; 12 ; Signed Integer ;; TIMER_5USEC_VALUE_PP ; 186 ; Signed Integer ;; TIMER_5USEC_BITS_PP ; 8 ; Signed Integer ;; TRAP_SHIFT_KEYS_PP ; 0 ; Signed Integer ;; m1_rx_clk_h ; 1 ; Signed Integer ;; m1_rx_clk_l ; 0 ; Signed Integer ;; m1_rx_falling_edge_marker ; 13 ; Signed Integer ;; m1_rx_rising_edge_marker ; 14 ; Signed Integer ;; m1_tx_force_clk_l ; 3 ; Signed Integer ;; m1_tx_first_wait_clk_h ; 10 ; Signed Integer ;; m1_tx_first_wait_clk_l ; 11 ; Signed Integer ;; m1_tx_reset_timer ; 12 ; Signed Integer ;; m1_tx_wait_clk_h ; 2 ; Signed Integer ;; m1_tx_clk_h ; 4 ; Signed Integer ;; m1_tx_clk_l ; 5 ; Signed Integer ;; m1_tx_wait_keyboard_ack ; 6 ; Signed Integer ;; m1_tx_done_recovery ; 7 ; Signed Integer ;; m1_tx_error_no_keyboard_ack ; 8 ; Signed Integer ;; m1_tx_rising_edge_marker ; 9 ; Signed Integer ;; m2_rx_data_ready ; 1 ; Signed Integer ;; m2_rx_data_ready_ack ; 0 ; Signed Integer ;+-----------------------------+-------+------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------+; Parameter Settings for User Entity Instance: CMD_Decode:u5 ;+----------------+----------+--------------------------------+; Parameter Name ; Value ; Type ;+----------------+----------+--------------------------------+; SETUP ; 01100001 ; Unsigned Binary ;; ERASE ; 01110010 ; Unsigned Binary ;; WRITE ; 10000011 ; Unsigned Binary ;; READ ; 10010100 ; Unsigned Binary ;; LCD_DAT ; 10000011 ; Unsigned Binary ;; LCD_CMD ; 10010100 ; Unsigned Binary ;; LED ; 11110000 ; Unsigned Binary ;; SEG7 ; 11100001 ; Unsigned Binary ;; PS2 ; 11010010 ; Unsigned Binary ;; FLASH ; 11000011 ; Unsigned Binary ;; SDRAM ; 10110100 ; Unsigned Binary ;; SRAM ; 10100101 ; Unsigned Binary ;; LCD ; 10010110 ; Unsigned Binary ;; VGA ; 10000111 ; Unsigned Binary ;; SDRSEL ; 00011111 ; Unsigned Binary ;; FLSEL ; 00101110 ; Unsigned Binary ;; EXTIO ; 00111101 ; Unsigned Binary ;; SET_REG ; 01001100 ; Unsigned Binary ;; SRSEL ; 01011011 ; Unsigned Binary ;; OUTSEL ; 00110011 ; Unsigned Binary ;; NORMAL ; 10101010 ; Unsigned Binary ;; DISPLAY ; 11001100 ; Unsigned Binary ;; BURST ; 11111111 ; Unsigned Binary ;; CMD_READ ; 000 ; Unsigned Binary ;; CMD_WRITE ; 001 ; Unsigned Binary ;; CMD_BLK_ERA ; 010 ; Unsigned Binary ;; CMD_SEC_ERA ; 011 ; Unsigned Binary ;; CMD_CHP_ERA ; 100 ; Unsigned Binary ;; CMD_ENTRY_ID ; 101 ; Unsigned Binary ;; CMD_RESET ; 110 ; Unsigned Binary ;+----------------+----------+--------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: VGA_Audio_PLL:p1|altpll:altpll_component ;+-------------------------------+-------------------+-----------------------------------+; Parameter Name ; Value ; Type ;+-------------------------------+-------------------+-----------------------------------+; OPERATION_MODE ; NORMAL ; Untyped ;; PLL_TYPE ; FAST ; Untyped ;; QUALIFY_CONF_DONE ; OFF ; Untyped ;; COMPENSATE_CLOCK ; CLK0 ; Untyped ;; SCAN_CHAIN ; LONG ; Untyped ;; PRIMARY_CLOCK ; INCLK0 ; Untyped ;; INCLK0_INPUT_FREQUENCY ; 37037 ; Signed Integer ;; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ;; GATE_LOCK_SIGNAL ; NO ; Untyped ;; GATE_LOCK_COUNTER ; 0 ; Untyped ;; LOCK_HIGH ; 1 ; Untyped ;; LOCK_LOW ; 1 ; Untyped ;; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ;; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ;; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ;; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ;; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ;; SKIP_VCO ; OFF ; Untyped ;; SWITCH_OVER_COUNTER ; 0 ; Untyped ;; SWITCH_OVER_TYPE ; AUTO ; Untyped ;; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ;; BANDWIDTH ; 0 ; Untyped ;; BANDWIDTH_TYPE ; AUTO ; Untyped ;; SPREAD_FREQUENCY ; 0 ; Untyped ;; DOWN_SPREAD ; 0 ; Untyped ;; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ;; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ;; CLK9_MULTIPLY_BY ; 0 ; Untyped ;; CLK8_MULTIPLY_BY ; 0 ; Untyped ;; CLK7_MULTIPLY_BY ; 0 ; Untyped ;; CLK6_MULTIPLY_BY ; 0 ; Untyped ;; CLK5_MULTIPLY_BY ; 1 ; Untyped ;; CLK4_MULTIPLY_BY ; 1 ; Untyped ;; CLK3_MULTIPLY_BY ; 1 ; Untyped ;; CLK2_MULTIPLY_BY ; 1 ; Untyped ;; CLK1_MULTIPLY_BY ; 2 ; Signed Integer ;; CLK0_MULTIPLY_BY ; 14 ; Signed Integer ;; CLK9_DIVIDE_BY ; 0 ; Untyped ;; CLK8_DIVIDE_BY ; 0 ; Untyped ;; CLK7_DIVIDE_BY ; 0 ; Untyped ;; CLK6_DIVIDE_BY ; 0 ; Untyped ;; CLK5_DIVIDE_BY ; 1 ; Untyped ;; CLK4_DIVIDE_BY ; 1 ; Untyped ;; CLK3_DIVIDE_BY ; 1 ; Untyped ;; CLK2_DIVIDE_BY ; 1 ; Untyped ;; CLK1_DIVIDE_BY ; 3 ; Signed Integer ;; CLK0_DIVIDE_BY ; 15 ; Signed Integer ;; CLK9_PHASE_SHIFT ; 0 ; Untyped ;; CLK8_PHASE_SHIFT ; 0 ; Untyped ;; CLK7_PHASE_SHIFT ; 0 ; Untyped ;; CLK6_PHASE_SHIFT ; 0 ; Untyped ;; CLK5_PHASE_SHIFT ; 0 ; Untyped ;; CLK4_PHASE_SHIFT ; 0 ; Untyped ;; CLK3_PHASE_SHIFT ; 0 ; Untyped ;; CLK2_PHASE_SHIFT ; 0 ; Untyped ;; CLK1_PHASE_SHIFT ; 0 ; Untyped ;; CLK0_PHASE_SHIFT ; 0 ; Untyped ;; CLK5_TIME_DELAY ; 0 ; Untyped ;; CLK4_TIME_DELAY ; 0 ; Untyped ;; CLK3_TIME_DELAY ; 0 ; Untyped ;; CLK2_TIME_DELAY ; 0 ; Untyped ;; CLK1_TIME_DELAY ; 0 ; Untyped ;; CLK0_TIME_DELAY ; 0 ; Untyped ;; CLK9_DUTY_CYCLE ; 50 ; Untyped ;; CLK8_DUTY_CYCLE ; 50 ; Untyped ;; CLK7_DUTY_CYCLE ; 50 ; Untyped ;; CLK6_DUTY_CYCLE ; 50 ; Untyped ;; CLK5_DUTY_CYCLE ; 50 ; Untyped ;; CLK4_DUTY_CYCLE ; 50 ; Untyped ;; CLK3_DUTY_CYCLE ; 50 ; Untyped ;; CLK2_DUTY_CYCLE ; 50 ; Untyped ;; CLK1_DUTY_CYCLE ; 50 ; Signed Integer ;; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ;; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;; LOCK_WINDOW_UI ; 0.05 ; Untyped ;; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ;; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ;; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ;; DPA_MULTIPLY_BY ; 0 ; Untyped ;; DPA_DIVIDE_BY ; 1 ; Untyped ;; DPA_DIVIDER ; 0 ; Untyped ;; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ;; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ;; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ;; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ;; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ;; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ;; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ;; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ;; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ;; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ;; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ;; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ;; EXTCLK3_TIME_DELAY ; 0 ; Untyped ;; EXTCLK2_TIME_DELAY ; 0 ; Untyped ;; EXTCLK1_TIME_DELAY ; 0 ; Untyped ;; EXTCLK0_TIME_DELAY ; 0 ; Untyped ;; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ;; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ;; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ;; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ;; VCO_MULTIPLY_BY ; 0 ; Untyped ;; VCO_DIVIDE_BY ; 0 ; Untyped ;; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ;; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ;; VCO_MIN ; 0 ; Untyped ;; VCO_MAX ; 0 ; Untyped ;; VCO_CENTER ; 0 ; Untyped ;; PFD_MIN ; 0 ; Untyped ;; PFD_MAX ; 0 ; Untyped ;; M_INITIAL ; 0 ; Untyped ;; M ; 0 ; Untyped ;; N ; 1 ; Untyped ;; M2 ; 1 ; Untyped ;; N2 ; 1 ; Untyped ;; SS ; 1 ; Untyped ;; C0_HIGH ; 0 ; Untyped ;; C1_HIGH ; 0 ; Untyped ;; C2_HIGH ; 0 ; Untyped ;; C3_HIGH ; 0 ; Untyped ;; C4_HIGH ; 0 ; Untyped ;; C5_HIGH ; 0 ; Untyped ;; C6_HIGH ; 0 ; Untyped ;; C7_HIGH ; 0 ; Untyped ;; C8_HIGH ; 0 ; Untyped ;; C9_HIGH ; 0 ; Untyped ;; C0_LOW ; 0 ; Untyped ;; C1_LOW ; 0 ; Untyped ;; C2_LOW ; 0 ; Untyped ;; C3_LOW ; 0 ; Untyped ;; C4_LOW ; 0 ; Untyped ;; C5_LOW ; 0 ; Untyped ;; C6_LOW ; 0 ; Untyped ;; C7_LOW ; 0 ; Untyped ;; C8_LOW ; 0 ; Untyped ;; C9_LOW ; 0 ; Untyped ;; C0_INITIAL ; 0 ; Untyped ;; C1_INITIAL ; 0 ; Untyped ;; C2_INITIAL ; 0 ; Untyped ;; C3_INITIAL ; 0 ; Untyped ;; C4_INITIAL ; 0 ; Untyped ;; C5_INITIAL ; 0 ; Untyped ;; C6_INITIAL ; 0 ; Untyped ;; C7_INITIAL ; 0 ; Untyped ;; C8_INITIAL ; 0 ; Untyped ;; C9_INITIAL ; 0 ; Untyped ;; C0_MODE ; BYPASS ; Untyped ;; C1_MODE ; BYPASS ; Untyped ;; C2_MODE ; BYPASS ; Untyped ;; C3_MODE ; BYPASS ; Untyped ;; C4_MODE ; BYPASS ; Untyped ;; C5_MODE ; BYPASS ; Untyped ;; C6_MODE ; BYPASS ; Untyped ;; C7_MODE ; BYPASS ; Untyped ;; C8_MODE ; BYPASS ; Untyped ;; C9_MODE ; BYPASS ; Untyped ;; C0_PH ; 0 ; Untyped ;; C1_PH ; 0 ; Untyped ;; C2_PH ; 0 ; Untyped ;; C3_PH ; 0 ; Untyped ;; C4_PH ; 0 ; Untyped ;; C5_PH ; 0 ; Untyped ;; C6_PH ; 0 ; Untyped ;; C7_PH ; 0 ; Untyped ;; C8_PH ; 0 ; Untyped ;; C9_PH ; 0 ; Untyped ;; L0_HIGH ; 1 ; Untyped ;; L1_HIGH ; 1 ; Untyped ;; G0_HIGH ; 1 ; Untyped ;; G1_HIGH ; 1 ; Untyped ;; G2_HIGH ; 1 ; Untyped ;; G3_HIGH ; 1 ; Untyped ;; E0_HIGH ; 1 ; Untyped ;; E1_HIGH ; 1 ; Untyped ;; E2_HIGH ; 1 ; Untyped ;; E3_HIGH ; 1 ; Untyped ;; L0_LOW ; 1 ; Untyped ;; L1_LOW ; 1 ; Untyped ;; G0_LOW ; 1 ; Untyped ;; G1_LOW ; 1 ; Untyped ;; G2_LOW ; 1 ; Untyped ;; G3_LOW ; 1 ; Untyped ;; E0_LOW ; 1 ; Untyped ;; E1_LOW ; 1 ; Untyped ;; E2_LOW ; 1 ; Untyped ;; E3_LOW ; 1 ; Untyped ;; L0_INITIAL ; 1 ; Untyped ;; L1_INITIAL ; 1 ; Untyped ;; G0_INITIAL ; 1 ; Untyped ;; G1_INITIAL ; 1 ; Untyped ;; G2_INITIAL ; 1 ; Untyped ;; G3_INITIAL ; 1 ; Untyped ;; E0_INITIAL ; 1 ; Untyped ;; E1_INITIAL ; 1 ; Untyped ;; E2_INITIAL ; 1 ; Untyped ;; E3_INITIAL ; 1 ; Untyped ;; L0_MODE ; BYPASS ; Untyped ;; L1_MODE ; BYPASS ; Untyped ;; G0_MODE ; BYPASS ; Untyped ;; G1_MODE ; BYPASS ; Untyped ;; G2_MODE ; BYPASS ; Untyped ;; G3_MODE ; BYPASS ; Untyped ;; E0_MODE ; BYPASS ; Untyped ;; E1_MODE ; BYPASS ; Untyped ;; E2_MODE ; BYPASS ; Untyped ;; E3_MODE ; BYPASS ; Untyped ;; L0_PH ; 0 ; Untyped ;; L1_PH ; 0 ; Untyped ;; G0_PH ; 0 ; Untyped ;; G1_PH ; 0 ; Untyped ;; G2_PH ; 0 ; Untyped ;; G3_PH ; 0 ; Untyped ;; E0_PH ; 0 ; Untyped ;; E1_PH ; 0 ; Untyped ;; E2_PH ; 0 ; Untyped ;; E3_PH ; 0 ; Untyped ;; M_PH ; 0 ; Untyped ;; C1_USE_CASC_IN ; OFF ; Untyped ;; C2_USE_CASC_IN ; OFF ; Untyped ;; C3_USE_CASC_IN ; OFF ; Untyped ;; C4_USE_CASC_IN ; OFF ; Untyped ;; C5_USE_CASC_IN ; OFF ; Untyped ;; C6_USE_CASC_IN ; OFF ; Untyped ;; C7_USE_CASC_IN ; OFF ; Untyped ;; C8_USE_CASC_IN ; OFF ; Untyped ;; C9_USE_CASC_IN ; OFF ; Untyped ;; CLK0_COUNTER ; G0 ; Untyped ;; CLK1_COUNTER ; G0 ; Untyped ;; CLK2_COUNTER ; G0 ; Untyped ;; CLK3_COUNTER ; G0 ; Untyped ;; CLK4_COUNTER ; G0 ; Untyped ;; CLK5_COUNTER ; G0 ; Untyped ;; CLK6_COUNTER ; E0 ; Untyped ;; CLK7_COUNTER ; E1 ; Untyped ;; CLK8_COUNTER ; E2 ; Untyped ;; CLK9_COUNTER ; E3 ; Untyped ;; L0_TIME_DELAY ; 0 ; Untyped ;; L1_TIME_DELAY ; 0 ; Untyped ;; G0_TIME_DELAY ; 0 ; Untyped ;; G1_TIME_DELAY ; 0 ; Untyped ;; G2_TIME_DELAY ; 0 ; Untyped ;; G3_TIME_DELAY ; 0 ; Untyped ;; E0_TIME_DELAY ; 0 ; Untyped ;; E1_TIME_DELAY ; 0 ; Untyped ;; E2_TIME_DELAY ; 0 ; Untyped ;; E3_TIME_DELAY ; 0 ; Untyped ;; M_TIME_DELAY ; 0 ; Untyped ;; N_TIME_DELAY ; 0 ; Untyped ;; EXTCLK3_COUNTER ; E3 ; Untyped ;; EXTCLK2_COUNTER ; E2 ; Untyped ;; EXTCLK1_COUNTER ; E1 ; Untyped ;; EXTCLK0_COUNTER ; E0 ; Untyped ;; ENABLE0_COUNTER ; L0 ; Untyped ;; ENABLE1_COUNTER ; L0 ; Untyped ;; CHARGE_PUMP_CURRENT ; 2 ; Untyped ;; LOOP_FILTER_R ; 1.000000 ; Untyped ;; LOOP_FILTER_C ; 5 ; Untyped ;; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ;; LOOP_FILTER_R_BITS ; 9999 ; Untyped ;; LOOP_FILTER_C_BITS ; 9999 ; Untyped ;; VCO_POST_SCALE ; 0 ; Untyped ;; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ;; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ;; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ;; INTENDED_DEVICE_FAMILY ; Cyclone II ; Untyped ;; PORT_CLKENA0 ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLKENA1 ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLKENA2 ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLKENA3 ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLKENA4 ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLKENA5 ; PORT_CONNECTIVITY ; Untyped ;; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ;; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ;; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ;; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ;; PORT_EXTCLK0 ; PORT_CONNECTIVITY ; Untyped ;; PORT_EXTCLK1 ; PORT_CONNECTIVITY ; Untyped ;; PORT_EXTCLK2 ; PORT_CONNECTIVITY ; Untyped ;; PORT_EXTCLK3 ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLKBAD0 ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLKBAD1 ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLK0 ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLK1 ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLK2 ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLK3 ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLK4 ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLK5 ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLK6 ; PORT_UNUSED ; Untyped ;; PORT_CLK7 ; PORT_UNUSED ; Untyped ;; PORT_CLK8 ; PORT_UNUSED ; Untyped ;; PORT_CLK9 ; PORT_UNUSED ; Untyped ;; PORT_SCANDATA ; PORT_CONNECTIVITY ; Untyped ;; PORT_SCANDATAOUT ; PORT_CONNECTIVITY ; Untyped ;; PORT_SCANDONE ; PORT_CONNECTIVITY ; Untyped ;; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ;; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ;; PORT_ACTIVECLOCK ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLKLOSS ; PORT_CONNECTIVITY ; Untyped ;; PORT_INCLK1 ; PORT_CONNECTIVITY ; Untyped ;; PORT_INCLK0 ; PORT_CONNECTIVITY ; Untyped ;; PORT_FBIN ; PORT_CONNECTIVITY ; Untyped ;; PORT_PLLENA ; PORT_CONNECTIVITY ; Untyped ;; PORT_CLKSWITCH ; PORT_CONNECTIVITY ; Untyped ;; PORT_ARESET ; PORT_CONNECTIVITY ; Untyped ;; PORT_PFDENA ; PORT_CONNECTIVITY ; Untyped ;; PORT_SCANCLK ; PORT_CONNECTIVITY ; Untyped ;; PORT_SCANACLR ; PORT_CONNECTIVITY ; Untyped ;; PORT_SCANREAD ; PORT_CONNECTIVITY ; Untyped ;; PORT_SCANWRITE ; PORT_CONNECTIVITY ; Untyped ;; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ;; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ;; PORT_LOCKED ; PORT_CONNECTIVITY ; Untyped ;; PORT_CONFIGUPDATE ; PORT_CONNECTIVITY ; Untyped ;; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ;; PORT_PHASEDONE ; PORT_CONNECTIVITY ; Untyped ;; PORT_PHASESTEP ; PORT_CONNECTIVITY ; Untyped ;; PORT_PHASEUPDOWN ; PORT_CONNECTIVITY ; Untyped ;; PORT_SCANCLKENA ; PORT_CONNECTIVITY ; Untyped ;; PORT_PHASECOUNTERSELECT ; PORT_CONNECTIVITY ; Untyped ;; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ;; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ;; M_TEST_SOURCE ; 5 ; Untyped ;; C0_TEST_SOURCE ; 5 ; Untyped ;; C1_TEST_SOURCE ; 5 ; Untyped ;; C2_TEST_SOURCE ; 5 ; Untyped ;; C3_TEST_SOURCE ; 5 ; Untyped ;; C4_TEST_SOURCE ; 5 ; Untyped ;; C5_TEST_SOURCE ; 5 ; Untyped ;; C6_TEST_SOURCE ; 5 ; Untyped ;; C7_TEST_SOURCE ; 5 ; Untyped ;; C8_TEST_SOURCE ; 5 ; Untyped ;; C9_TEST_SOURCE ; 5 ; Untyped ;; CBXI_PARAMETER ; NOTHING ; Untyped ;; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ;; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ;; WIDTH_CLOCK ; 6 ; Untyped ;; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ;; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ;; DEVICE_FAMILY ; Cyclone II ; Untyped ;; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ;; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ;; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;+-------------------------------+-------------------+-----------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------+; Parameter Settings for User Entity Instance: VGA_Controller:u8 ;+----------------+-------+---------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------+; H_SYNC_CYC ; 96 ; Signed Integer ;; H_SYNC_BACK ; 48 ; Signed Integer ;; H_SYNC_ACT ; 640 ; Signed Integer ;; H_SYNC_FRONT ; 16 ; Signed Integer ;; H_SYNC_TOTAL ; 800 ; Signed Integer ;; V_SYNC_CYC ; 2 ; Signed Integer ;; V_SYNC_BACK ; 32 ; Signed Integer ;; V_SYNC_ACT ; 480 ; Signed Integer ;; V_SYNC_FRONT ; 11 ; Signed Integer ;; V_SYNC_TOTAL ; 525 ; Signed Integer ;; X_START ; 148 ; Signed Integer ;; Y_START ; 34 ; Signed Integer ;+----------------+-------+---------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------+; Parameter Settings for User Entity Instance: VGA_OSD_RAM:u9 ;+----------------+-------+------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------+; START_X ; 60 ; Signed Integer ;; START_Y ; 50 ; Signed Integer ;; END_X ; 580 ; Signed Integer ;; END_Y ; 450 ; Signed Integer ;+----------------+-------+------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component ;+------------------------------------+----------------------+--------------------------------------------+; Parameter Name ; Value ; Type ;+------------------------------------+----------------------+--------------------------------------------+; BYTE_SIZE_BLOCK ; 8 ; Untyped ;; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;; WIDTH_BYTEENA ; 1 ; Untyped ;; OPERATION_MODE ; DUAL_PORT ; Untyped ;; WIDTH_A ; 1 ; Signed Integer ;; WIDTHAD_A ; 18 ; Signed Integer ;; NUMWORDS_A ; 208000 ; Signed Integer ;; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;; ADDRESS_ACLR_A ; NONE ; Untyped ;; OUTDATA_ACLR_A ; NONE ; Untyped ;; WRCONTROL_ACLR_A ; NONE ; Untyped ;; INDATA_ACLR_A ; NONE ; Untyped ;; BYTEENA_ACLR_A ; NONE ; Untyped ;; WIDTH_B ; 8 ; Signed Integer ;; WIDTHAD_B ; 15 ; Signed Integer ;; NUMWORDS_B ; 26000 ; Signed Integer ;; INDATA_REG_B ; CLOCK1 ; Untyped ;; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;; ADDRESS_REG_B ; CLOCK1 ; Untyped ;; OUTDATA_REG_B ; CLOCK1 ; Untyped ;; BYTEENA_REG_B ; CLOCK1 ; Untyped ;; INDATA_ACLR_B ; NONE ; Untyped ;; WRCONTROL_ACLR_B ; NONE ; Untyped ;; ADDRESS_ACLR_B ; NONE ; Untyped ;; OUTDATA_ACLR_B ; NONE ; Untyped ;; RDCONTROL_ACLR_B ; NONE ; Untyped ;; BYTEENA_ACLR_B ; NONE ; Untyped ;; WIDTH_BYTEENA_A ; 1 ; Signed Integer ;; WIDTH_BYTEENA_B ; 1 ; Untyped ;; RAM_BLOCK_TYPE ; M4K ; Untyped ;; BYTE_SIZE ; 8 ; Untyped ;; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;; INIT_FILE ; Img_DATA.hex ; Untyped ;; INIT_FILE_LAYOUT ; PORT_B ; Untyped ;; MAXIMUM_DEPTH ; 0 ; Untyped ;; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ;; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ;; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ;; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;; ENABLE_ECC ; FALSE ; Untyped ;; DEVICE_FAMILY ; Cyclone II ; Untyped ;; CBXI_PARAMETER ; altsyncram_f7o1 ; Untyped ;+------------------------------------+----------------------+--------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------+; Parameter Settings for User Entity Instance: I2C_AV_Config:u10 ;+----------------+----------+------------------------------------+; Parameter Name ; Value ; Type ;+----------------+----------+------------------------------------+; CLK_Freq ; 50000000 ; Signed Integer ;; I2C_Freq ; 20000 ; Signed Integer ;; LUT_SIZE ; 11 ; Signed Integer ;; Dummy_DATA ; 0 ; Signed Integer ;; SET_LIN_L ; 1 ; Signed Integer ;; SET_LIN_R ; 2 ; Signed Integer ;; SET_HEAD_L ; 3 ; Signed Integer ;; SET_HEAD_R ; 4 ; Signed Integer ;; A_PATH_CTRL ; 5 ; Signed Integer ;; D_PATH_CTRL ; 6 ; Signed Integer ;; POWER_ON ; 7 ; Signed Integer ;; SET_FORMAT ; 8 ; Signed Integer ;; SAMPLE_CTRL ; 9 ; Signed Integer ;; SET_ACTIVE ; 10 ; Signed Integer ;+----------------+----------+------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------+; Parameter Settings for User Entity Instance: AUDIO_DAC:u11 ;+------------------+----------+------------------------------+; Parameter Name ; Value ; Type ;+------------------+----------+------------------------------+; REF_CLK ; 18432000 ; Signed Integer ;; SAMPLE_RATE ; 48000 ; Signed Integer ;; DATA_WIDTH ; 16 ; Signed Integer ;; CHANNEL_NUM ; 2 ; Signed Integer ;; SIN_SAMPLE_DATA ; 48 ; Signed Integer ;; FLASH_DATA_NUM ; 4194304 ; Signed Integer ;; SDRAM_DATA_NUM ; 4194304 ; Signed Integer ;; SRAM_DATA_NUM ; 262144 ; Signed Integer ;; FLASH_ADDR_WIDTH ; 22 ; Signed Integer ;; SDRAM_ADDR_WIDTH ; 22 ; Signed Integer ;; SRAM_ADDR_WIDTH ; 18 ; Signed Integer ;; FLASH_DATA_WIDTH ; 8 ; Signed Integer ;; SDRAM_DATA_WIDTH ; 16 ; Signed Integer ;; SRAM_DATA_WIDTH ; 16 ; Signed Integer ;; SIN_SANPLE ; 0 ; Signed Integer ;; FLASH_DATA ; 1 ; Signed Integer ;; SDRAM_DATA ; 2 ; Signed Integer ;; SRAM_DATA ; 3 ; Signed Integer ;+------------------+----------+------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------+; altpll Parameter Settings by Entity Instance ;+-------------------------------+----------------------------------------------------------------------------+; Name ; Value ;+-------------------------------+----------------------------------------------------------------------------+; Number of entity instances ; 2 ;; Entity Instance ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component ;; -- OPERATION_MODE ; NORMAL ;; -- PLL_TYPE ; FAST ;; -- PRIMARY_CLOCK ; INCLK0 ;; -- INCLK0_INPUT_FREQUENCY ; 20000 ;; -- INCLK1_INPUT_FREQUENCY ; 0 ;; -- VCO_MULTIPLY_BY ; 0 ;; -- VCO_DIVIDE_BY ; 0 ;; Entity Instance ; VGA_Audio_PLL:p1|altpll:altpll_component ;; -- OPERATION_MODE ; NORMAL ;; -- PLL_TYPE ; FAST ;; -- PRIMARY_CLOCK ; INCLK0 ;; -- INCLK0_INPUT_FREQUENCY ; 37037 ;; -- INCLK1_INPUT_FREQUENCY ; 0 ;; -- VCO_MULTIPLY_BY ; 0 ;; -- VCO_DIVIDE_BY ; 0 ;+-------------------------------+----------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------+; altsyncram Parameter Settings by Entity Instance ;+-------------------------------------------+-----------------------------------------------------------+; Name ; Value ;+-------------------------------------------+-----------------------------------------------------------+; Number of entity instances ; 1 ;; Entity Instance ; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component ;; -- OPERATION_MODE ; DUAL_PORT ;; -- WIDTH_A ; 1 ;; -- NUMWORDS_A ; 208000 ;; -- OUTDATA_REG_A ; UNREGISTERED ;; -- WIDTH_B ; 8 ;; -- NUMWORDS_B ; 26000 ;; -- ADDRESS_REG_B ; CLOCK1 ;; -- OUTDATA_REG_B ; CLOCK1 ;; -- RAM_BLOCK_TYPE ; M4K ;; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;+-------------------------------------------+-----------------------------------------------------------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "AUDIO_DAC:u11" ;+-------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+; oSDRAM_ADDR ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; iSDRAM_DATA ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; oSRAM_ADDR ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; iSRAM_DATA ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;+-------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "I2C_AV_Config:u10|I2C_Controller:u0" ;+------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+; W_R ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; SD_COUNTER ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; SDO ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;+------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "VGA_OSD_RAM:u9|Img_RAM:u0" ;+-----------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-----------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; wraddress ; Input ; Warning ; Input port expression (19 bits) is wider than the input port (18 bits) it drives. The 1 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;; rdaddress ; Input ; Warning ; Input port expression (16 bits) is wider than the input port (15 bits) it drives. The 1 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;+-----------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "VGA_OSD_RAM:u9" ;+--------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+--------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; iVGA_ADDR ; Input ; Warning ; Input port expression (20 bits) is wider than the input port (19 bits) it drives. The 1 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;; iON_R ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (10 bits) it drives. The 22 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;; iON_R[9..0] ; Input ; Info ; Stuck at VCC ;; iON_G ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (10 bits) it drives. The 22 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;; iON_G[9..0] ; Input ; Info ; Stuck at VCC ;; iON_B ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (10 bits) it drives. The 22 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;; iON_B[9..0] ; Input ; Info ; Stuck at VCC ;; iOFF_R ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (10 bits) it drives. The 22 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;; iOFF_R[9..0] ; Input ; Info ; Stuck at GND ;; iOFF_G ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (10 bits) it drives. The 22 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;; iOFF_G[9..0] ; Input ; Info ; Stuck at GND ;; iOFF_B ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (10 bits) it drives. The 22 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;; iOFF_B[8..0] ; Input ; Info ; Stuck at GND ;; iOFF_B[9] ; Input ; Info ; Stuck at VCC ;; iWR_DATA ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; iWR_ADDR ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; iWR_EN ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; iWR_CLK ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;+--------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "VGA_Controller:u8" ;+----------------------+--------+----------+----------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+----------------------+--------+----------+----------------------------------------------------------------------------------------------------------+; iCursor_RGB_EN[2..0] ; Input ; Info ; Stuck at VCC ;; oVGA_R[5..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;; oVGA_G[5..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;; oVGA_B[5..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;; oVGA_SYNC ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; oVGA_BLANK ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; oVGA_CLOCK ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;+----------------------+--------+----------+----------------------------------------------------------------------------------------------------------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "Multi_Sram:u6" ;+-----------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-----------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; iAS1_ADDR ; Input ; Warning ; Input port expression (19 bits) is wider than the input port (18 bits) it drives. The 1 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;; iAS1_WE_N ; Input ; Info ; Stuck at VCC ;; iAS1_OE_N ; Input ; Info ; Stuck at GND ;; iSelect ; Input ; Warning ; Input port expression (3 bits) is wider than the input port (2 bits) it drives. The 1 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;; iAS1_DATA ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; oAS2_DATA ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; iAS2_DATA ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; iAS2_ADDR ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; iAS2_WE_N ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; iAS2_OE_N ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; oAS3_DATA ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; iAS3_DATA ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; iAS3_ADDR ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; iAS3_WE_N ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; iAS3_OE_N ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;+-----------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "CMD_Decode:u5" ;+-------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+; oLED_GREEN ; Output ; Warning ; Output or bidir port (9 bits) is wider than the port expression (8 bits) it drives; bit(s) "oLED_GREEN[8..8]" have no fanouts ;; oLED_RED ; Output ; Warning ; Output or bidir port (18 bits) is wider than the port expression (10 bits) it drives; bit(s) "oLED_RED[17..10]" have no fanouts ;; oSDR_Select ; Output ; Warning ; Output or bidir port (2 bits) is smaller than the port expression (3 bits) it drives. The 1 most-significant bit(s) in the port expression will be connected to GND. ;; oFL_Select ; Output ; Warning ; Output or bidir port (2 bits) is smaller than the port expression (3 bits) it drives. The 1 most-significant bit(s) in the port expression will be connected to GND. ;; oSR_Select ; Output ; Warning ; Output or bidir port (2 bits) is smaller than the port expression (3 bits) it drives. The 1 most-significant bit(s) in the port expression will be connected to GND. ;+-------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ps2_keyboard:u4" ;+--------------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+--------------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+; ps2_clk_en_o_ ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; ps2_data_en_o_ ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; rx_extended ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; rx_released ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; rx_shift_key_on ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; rx_scan_code ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; tx_data ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; tx_write ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; tx_write_ack_o ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; tx_error_no_keyboard_ack ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; translate ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;+--------------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------++----------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1" ;+------+--------+----------+-------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------+--------+----------+-------------------------------------------------------------------------------------+; DQM ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;+------+--------+----------+-------------------------------------------------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1" ;+----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+; CMD ; Input ; Warning ; Input port expression (2 bits) is smaller than the input port (3 bits) it drives. Extra input bit(s) "CMD[2..2]" will be connected to GND. ;; INIT_ACK ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;+----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "Multi_Sdram:u3|Sdram_Controller:u1" ;+--------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+--------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------+; ADDR[22] ; Input ; Info ; Stuck at GND ;; IN_REQ ; Output ; Info ; Explicitly unconnected ;; OUT_VALID ; Output ; Info ; Explicitly unconnected ;; DM ; Input ; Info ; Stuck at GND ;; LENGTH[7..1] ; Input ; Info ; Stuck at GND ;; LENGTH[0] ; Input ; Info ; Stuck at VCC ;; CS_N ; Output ; Warning ; Output or bidir port (2 bits) is wider than the port expression (1 bits) it drives; bit(s) "CS_N[1..1]" have no fanouts ;; ACT ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;+--------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "Multi_Sdram:u3" ;+-----------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-----------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; oAS1_DATA ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;; iAS1_DATA ; Input ; Info ; Stuck at GND ;; iAS1_ADDR ; Input ; Info ; Stuck at GND ;; iAS1_WR_n ; Input ; Info ; Stuck at GND ;; oAS2_DATA ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;; iAS2_DATA ; Input ; Info ; Stuck at GND ;; iAS2_ADDR ; Input ; Info ; Stuck at GND ;; iAS2_WR_n ; Input ; Info ; Stuck at GND ;; oAS3_DATA ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;; iAS3_DATA ; Input ; Info ; Stuck at GND ;; iAS3_ADDR ; Input ; Info ; Stuck at GND ;; iAS3_WR_n ; Input ; Info ; Stuck at GND ;; iSelect ; Input ; Warning ; Input port expression (3 bits) is wider than the input port (2 bits) it drives. The 1 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;+-----------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "Multi_Flash:u2" ;+-----------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-----------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; oAS2_DATA ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;; oAS3_DATA ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;; iSelect ; Input ; Warning ; Input port expression (3 bits) is wider than the input port (2 bits) it drives. The 1 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;+-----------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "SEG7_LUT_4:u0" ;+------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; iDIG ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (16 bits) it drives. The 16 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;+------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "CLK_LOCK:p0|CLK_LOCK_altclkctrl_tb8:CLK_LOCK_altclkctrl_tb8_component" ;+-------------+-------+----------+------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------+-------+----------+------------------------------------------------------------------+; ena ; Input ; Info ; Stuck at VCC ;; inclk[3..1] ; Input ; Info ; Stuck at GND ;; clkselect ; Input ; Info ; Stuck at GND ;+-------------+-------+----------+------------------------------------------------------------------++-------------------------------+; Analysis & Synthesis Messages ;+-------------------------------+Info: *******************************************************************Info: Running Quartus II Analysis & SynthesisInfo: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web EditionInfo: Processing started: Sun Oct 11 12:22:15 2009Info: Command: quartus_map --read_settings_files=on --write_settings_files=off CII_Starter_USB_API -c CII_Starter_USB_APIInfo: Found 1 design units, including 1 entities, in source file VGA_Controller/Img_RAM.vInfo: Found entity 1: Img_RAMInfo: Found 1 design units, including 1 entities, in source file VGA_Controller/VGA_OSD_RAM.vInfo: Found entity 1: VGA_OSD_RAMInfo: Found 1 design units, including 1 entities, in source file VGA_Controller/VGA_Controller.vInfo: Found entity 1: VGA_ControllerInfo: Found 1 design units, including 1 entities, in source file Multi_Sdram/command.vInfo: Found entity 1: commandInfo: Found 1 design units, including 1 entities, in source file Multi_Sdram/control_interface.vInfo: Found entity 1: control_interfaceInfo: Found 1 design units, including 1 entities, in source file Multi_Sdram/Multi_Sdram.vInfo: Found entity 1: Multi_SdramInfo: Found 1 design units, including 1 entities, in source file Multi_Sdram/PLL1.vInfo: Found entity 1: PLL1Info: Found 1 design units, including 1 entities, in source file Multi_Sdram/sdr_data_path.vInfo: Found entity 1: sdr_data_pathInfo: Found 1 design units, including 1 entities, in source file Multi_Sdram/Sdram_Controller.vInfo: Found entity 1: Sdram_ControllerInfo: Found 1 design units, including 1 entities, in source file Multi_Sdram/Sdram_Multiplexer.vInfo: Found entity 1: Sdram_MultiplexerInfo: Found 1 design units, including 1 entities, in source file Multi_Flash/Flash_Controller.vInfo: Found entity 1: Flash_ControllerInfo: Found 1 design units, including 1 entities, in source file Multi_Flash/Flash_Multiplexer.vInfo: Found entity 1: Flash_MultiplexerInfo: Found 1 design units, including 1 entities, in source file Multi_Flash/Multi_Flash.vInfo: Found entity 1: Multi_FlashInfo: Found 1 design units, including 1 entities, in source file AUDIO_DAC.vInfo: Found entity 1: AUDIO_DACInfo: Found 2 design units, including 2 entities, in source file CLK_LOCK.vInfo: Found entity 1: CLK_LOCK_altclkctrl_tb8Info: Found entity 2: CLK_LOCKInfo: Found 1 design units, including 1 entities, in source file CMD_Decode.vInfo: Found entity 1: CMD_DecodeInfo: Found 1 design units, including 1 entities, in source file CII_Starter_USB_API.vInfo: Found entity 1: CII_Starter_USB_APIInfo: Found 1 design units, including 1 entities, in source file I2C_AV_Config.vInfo: Found entity 1: I2C_AV_ConfigInfo: Found 1 design units, including 1 entities, in source file I2C_Controller.vInfo: Found entity 1: I2C_ControllerInfo: Found 1 design units, including 1 entities, in source file Multi_Sram.vInfo: Found entity 1: Multi_SramInfo: Found 1 design units, including 1 entities, in source file ps2_keyboard.vInfo: Found entity 1: ps2_keyboardInfo: Found 1 design units, including 1 entities, in source file Reset_Delay.vInfo: Found entity 1: Reset_DelayInfo: Found 1 design units, including 1 entities, in source file RS232_Controller.vInfo: Found entity 1: RS232_ControllerInfo: Found 1 design units, including 1 entities, in source file SEG7_LUT.vInfo: Found entity 1: SEG7_LUTInfo: Found 1 design units, including 1 entities, in source file SRAM_16Bit_512K.vInfo: Found entity 1: SRAM_16Bit_512KInfo: Found 3 design units, including 3 entities, in source file USB_JTAG.vInfo: Found entity 1: USB_JTAGInfo: Found entity 2: JTAG_RECInfo: Found entity 3: JTAG_TRANSInfo: Found 1 design units, including 1 entities, in source file VGA_Audio_PLL.vInfo: Found entity 1: VGA_Audio_PLLInfo: Found 1 design units, including 1 entities, in source file SEG7_LUT_4.vInfo: Found entity 1: SEG7_LUT_4Info: Found 1 design units, including 1 entities, in source file VGA_Controller/VGA_Pattern.vInfo: Found entity 1: VGA_PatternInfo: Elaborating entity "CII_Starter_USB_API" for the top level hierarchyWarning (10034): Output port "UART_TXD" at CII_Starter_USB_API.v(116) has no driverWarning (10034): Output port "SD_CLK" at CII_Starter_USB_API.v(150) has no driverInfo: Elaborating entity "CLK_LOCK" for hierarchy "CLK_LOCK:p0"Info: Elaborating entity "CLK_LOCK_altclkctrl_tb8" for hierarchy "CLK_LOCK:p0|CLK_LOCK_altclkctrl_tb8:CLK_LOCK_altclkctrl_tb8_component"Info: Elaborating entity "Reset_Delay" for hierarchy "Reset_Delay:d0"Warning (10230): Verilog HDL assignment warning at Reset_Delay.v(22): truncated value with size 32 to match size of target (20)Info: Elaborating entity "SEG7_LUT_4" for hierarchy "SEG7_LUT_4:u0"Info: Elaborating entity "SEG7_LUT" for hierarchy "SEG7_LUT_4:u0|SEG7_LUT:u0"Info: Elaborating entity "USB_JTAG" for hierarchy "USB_JTAG:u1"Info: Elaborating entity "JTAG_REC" for hierarchy "USB_JTAG:u1|JTAG_REC:u0"Warning (10230): Verilog HDL assignment warning at USB_JTAG.v(93): truncated value with size 32 to match size of target (3)Info: Elaborating entity "JTAG_TRANS" for hierarchy "USB_JTAG:u1|JTAG_TRANS:u1"Warning (10230): Verilog HDL assignment warning at USB_JTAG.v(128): truncated value with size 32 to match size of target (3)Info: Elaborating entity "Multi_Flash" for hierarchy "Multi_Flash:u2"Info: Elaborating entity "Flash_Multiplexer" for hierarchy "Multi_Flash:u2|Flash_Multiplexer:u0"Info: Elaborating entity "Flash_Controller" for hierarchy "Multi_Flash:u2|Flash_Controller:u1"Warning (10230): Verilog HDL assignment warning at Flash_Controller.v(95): truncated value with size 32 to match size of target (11)Warning (10230): Verilog HDL assignment warning at Flash_Controller.v(144): truncated value with size 32 to match size of target (11)Warning (10230): Verilog HDL assignment warning at Flash_Controller.v(239): truncated value with size 32 to match size of target (22)Warning (10230): Verilog HDL assignment warning at Flash_Controller.v(251): truncated value with size 32 to match size of target (22)Warning (10230): Verilog HDL assignment warning at Flash_Controller.v(252): truncated value with size 32 to match size of target (22)Warning (10230): Verilog HDL assignment warning at Flash_Controller.v(253): truncated value with size 32 to match size of target (22)Warning (10230): Verilog HDL assignment warning at Flash_Controller.v(254): truncated value with size 32 to match size of target (22)Warning (10230): Verilog HDL assignment warning at Flash_Controller.v(255): truncated value with size 32 to match size of target (22)Warning (10230): Verilog HDL assignment warning at Flash_Controller.v(256): truncated value with size 32 to match size of target (22)Warning (10230): Verilog HDL assignment warning at Flash_Controller.v(257): truncated value with size 32 to match size of target (22)Info: Elaborating entity "Multi_Sdram" for hierarchy "Multi_Sdram:u3"Info: Elaborating entity "Sdram_Multiplexer" for hierarchy "Multi_Sdram:u3|Sdram_Multiplexer:u0"Info: Elaborating entity "Sdram_Controller" for hierarchy "Multi_Sdram:u3|Sdram_Controller:u1"Warning (10230): Verilog HDL assignment warning at Sdram_Controller.v(237): truncated value with size 32 to match size of target (9)Info: Elaborating entity "PLL1" for hierarchy "Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1"Info: Elaborating entity "altpll" for hierarchy "Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component"Info: Elaborated megafunction instantiation "Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component"Info: Instantiated megafunction "Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component" with the following parameter:Info: Parameter "clk0_duty_cycle" = "50"Info: Parameter "lpm_type" = "altpll"Info: Parameter "clk0_multiply_by" = "1"Info: Parameter "inclk0_input_frequency" = "20000"Info: Parameter "clk0_divide_by" = "1"Info: Parameter "pll_type" = "FAST"Info: Parameter "clk2_phase_shift" = "0"Info: Parameter "intended_device_family" = "Cyclone II"Info: Parameter "clk2_divide_by" = "1"Info: Parameter "operation_mode" = "NORMAL"Info: Parameter "clk2_duty_cycle" = "50"Info: Parameter "compensate_clock" = "CLK0"Info: Parameter "clk0_phase_shift" = "0"Info: Parameter "clk2_multiply_by" = "1"Info: Elaborating entity "control_interface" for hierarchy "Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1"Warning (10230): Verilog HDL assignment warning at control_interface.v(132): truncated value with size 32 to match size of target (16)Warning (10230): Verilog HDL assignment warning at control_interface.v(137): truncated value with size 32 to match size of target (16)Warning (10230): Verilog HDL assignment warning at control_interface.v(162): truncated value with size 32 to match size of target (16)Info: Elaborating entity "command" for hierarchy "Multi_Sdram:u3|Sdram_Controller:u1|command:command1"Warning (10240): Verilog HDL Always Construct warning at command.v(251): inferring latch(es) for variable "oe_shift", which holds its previous value in one or more paths through the always constructWarning (10240): Verilog HDL Always Construct warning at command.v(251): inferring latch(es) for variable "oe1", which holds its previous value in one or more paths through the always constructWarning (10240): Verilog HDL Always Construct warning at command.v(251): inferring latch(es) for variable "oe2", which holds its previous value in one or more paths through the always constructInfo: Elaborating entity "sdr_data_path" for hierarchy "Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1"Warning (10036): Verilog HDL or VHDL warning at sdr_data_path.v(36): object "DM1" assigned a value but never readInfo: Elaborating entity "ps2_keyboard" for hierarchy "ps2_keyboard:u4"Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(321): truncated value with size 32 to match size of target (1)Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(332): truncated value with size 32 to match size of target (1)Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(333): truncated value with size 32 to match size of target (1)Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(338): truncated value with size 32 to match size of target (1)Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(339): truncated value with size 32 to match size of target (1)Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(341): truncated value with size 32 to match size of target (1)Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(359): truncated value with size 32 to match size of target (4)Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(388): truncated value with size 32 to match size of target (12)Warning (10230): Verilog HDL assignment warning at ps2_keyboard.v(396): truncated value with size 32 to match size of target (8)Info: Elaborating entity "CMD_Decode" for hierarchy "CMD_Decode:u5"Warning (10036): Verilog HDL or VHDL warning at CMD_Decode.v(93): object "sel_PS2" assigned a value but never readWarning (10230): Verilog HDL assignment warning at CMD_Decode.v(261): truncated value with size 24 to match size of target (18)Warning (10230): Verilog HDL assignment warning at CMD_Decode.v(262): truncated value with size 16 to match size of target (9)Warning (10230): Verilog HDL assignment warning at CMD_Decode.v(319): truncated value with size 24 to match size of target (22)Warning (10230): Verilog HDL assignment warning at CMD_Decode.v(320): truncated value with size 16 to match size of target (8)Warning (10230): Verilog HDL assignment warning at CMD_Decode.v(445): truncated value with size 24 to match size of target (22)Warning (10230): Verilog HDL assignment warning at CMD_Decode.v(529): truncated value with size 24 to match size of target (18)Info: Elaborating entity "Multi_Sram" for hierarchy "Multi_Sram:u6"Info: Elaborating entity "VGA_Audio_PLL" for hierarchy "VGA_Audio_PLL:p1"Info: Elaborating entity "altpll" for hierarchy "VGA_Audio_PLL:p1|altpll:altpll_component"Info: Elaborated megafunction instantiation "VGA_Audio_PLL:p1|altpll:altpll_component"Info: Instantiated megafunction "VGA_Audio_PLL:p1|altpll:altpll_component" with the following parameter:Info: Parameter "clk0_divide_by" = "15"Info: Parameter "clk0_duty_cycle" = "50"Info: Parameter "clk0_multiply_by" = "14"Info: Parameter "clk0_phase_shift" = "0"Info: Parameter "clk1_divide_by" = "3"Info: Parameter "clk1_duty_cycle" = "50"Info: Parameter "clk1_multiply_by" = "2"Info: Parameter "clk1_phase_shift" = "0"Info: Parameter "compensate_clock" = "CLK0"Info: Parameter "inclk0_input_frequency" = "37037"Info: Parameter "intended_device_family" = "Cyclone II"Info: Parameter "lpm_type" = "altpll"Info: Parameter "operation_mode" = "NORMAL"Info: Parameter "pll_type" = "FAST"Info: Elaborating entity "VGA_Controller" for hierarchy "VGA_Controller:u8"Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(86): truncated value with size 32 to match size of target (10)Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(89): truncated value with size 32 to match size of target (10)Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(92): truncated value with size 32 to match size of target (10)Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(110): truncated value with size 32 to match size of target (10)Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(111): truncated value with size 32 to match size of target (10)Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(112): truncated value with size 32 to match size of target (20)Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(171): truncated value with size 32 to match size of target (10)Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(197): truncated value with size 32 to match size of target (10)Info: Elaborating entity "VGA_OSD_RAM" for hierarchy "VGA_OSD_RAM:u9"Warning (10230): Verilog HDL assignment warning at VGA_OSD_RAM.v(68): truncated value with size 32 to match size of target (19)Info: Elaborating entity "Img_RAM" for hierarchy "VGA_OSD_RAM:u9|Img_RAM:u0"Info: Elaborating entity "altsyncram" for hierarchy "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component"Info: Elaborated megafunction instantiation "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component"Info: Instantiated megafunction "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component" with the following parameter:Info: Parameter "address_reg_b" = "CLOCK1"Info: Parameter "clock_enable_input_a" = "BYPASS"Info: Parameter "clock_enable_input_b" = "BYPASS"Info: Parameter "clock_enable_output_b" = "BYPASS"Info: Parameter "init_file" = "Img_DATA.hex"Info: Parameter "init_file_layout" = "PORT_B"Info: Parameter "intended_device_family" = "Cyclone II"Info: Parameter "lpm_type" = "altsyncram"Info: Parameter "numwords_a" = "208000"Info: Parameter "numwords_b" = "26000"Info: Parameter "operation_mode" = "DUAL_PORT"Info: Parameter "outdata_aclr_b" = "NONE"Info: Parameter "outdata_reg_b" = "CLOCK1"Info: Parameter "power_up_uninitialized" = "FALSE"Info: Parameter "ram_block_type" = "M4K"Info: Parameter "widthad_a" = "18"Info: Parameter "widthad_b" = "15"Info: Parameter "width_a" = "1"Info: Parameter "width_b" = "8"Info: Parameter "width_byteena_a" = "1"Info: Found 1 design units, including 1 entities, in source file db/altsyncram_f7o1.tdfInfo: Found entity 1: altsyncram_f7o1Info: Elaborating entity "altsyncram_f7o1" for hierarchy "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated"Info: Found 1 design units, including 1 entities, in source file db/altsyncram_e132.tdfInfo: Found entity 1: altsyncram_e132Info: Elaborating entity "altsyncram_e132" for hierarchy "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1"Warning: Variable or input pin "clocken1" is defined but never usedWarning: Byte addressed memory initialization file "Img_DATA.hex" was read in the word-addressed formatInfo: Found 1 design units, including 1 entities, in source file db/decode_qpa.tdfInfo: Found entity 1: decode_qpaInfo: Elaborating entity "decode_qpa" for hierarchy "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode3"Info: Elaborating entity "decode_qpa" for hierarchy "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a"Info: Found 1 design units, including 1 entities, in source file db/mux_akb.tdfInfo: Found entity 1: mux_akbInfo: Elaborating entity "mux_akb" for hierarchy "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|mux_akb:mux5"Info: Found 1 design units, including 1 entities, in source file db/mux_3kb.tdfInfo: Found entity 1: mux_3kbInfo: Elaborating entity "mux_3kb" for hierarchy "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|mux_3kb:mux6"Info: Elaborating entity "I2C_AV_Config" for hierarchy "I2C_AV_Config:u10"Warning (10230): Verilog HDL assignment warning at I2C_AV_Config.v(65): truncated value with size 32 to match size of target (16)Warning (10230): Verilog HDL assignment warning at I2C_AV_Config.v(113): truncated value with size 32 to match size of target (4)Info: Elaborating entity "I2C_Controller" for hierarchy "I2C_AV_Config:u10|I2C_Controller:u0"Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(49): truncated value with size 32 to match size of target (1)Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(48): truncated value with size 32 to match size of target (1)Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(61): truncated value with size 32 to match size of target (6)Info: Elaborating entity "AUDIO_DAC" for hierarchy "AUDIO_DAC:u11"Warning (10230): Verilog HDL assignment warning at AUDIO_DAC.v(104): truncated value with size 32 to match size of target (4)Warning (10230): Verilog HDL assignment warning at AUDIO_DAC.v(129): truncated value with size 32 to match size of target (9)Warning (10230): Verilog HDL assignment warning at AUDIO_DAC.v(137): truncated value with size 32 to match size of target (8)Warning (10230): Verilog HDL assignment warning at AUDIO_DAC.v(145): truncated value with size 32 to match size of target (7)Warning (10230): Verilog HDL assignment warning at AUDIO_DAC.v(158): truncated value with size 32 to match size of target (6)Warning (10230): Verilog HDL assignment warning at AUDIO_DAC.v(172): truncated value with size 32 to match size of target (22)Warning (10230): Verilog HDL assignment warning at AUDIO_DAC.v(208): truncated value with size 32 to match size of target (22)Warning (10230): Verilog HDL assignment warning at AUDIO_DAC.v(239): truncated value with size 32 to match size of target (18)Warning (10230): Verilog HDL assignment warning at AUDIO_DAC.v(268): truncated value with size 32 to match size of target (4)Warning: Net is missing source, defaulting to GNDWarning (12110): Net "mSR_Select[2]" is missing source, defaulting to GNDWarning: Net is missing source, defaulting to GNDWarning (12110): Net "mSR_Select[2]" is missing source, defaulting to GNDWarning: Net is missing source, defaulting to GNDWarning (12110): Net "mSDR_Select[2]" is missing source, defaulting to GNDWarning (12110): Net "mSR_Select[2]" is missing source, defaulting to GNDWarning: Net is missing source, defaulting to GNDWarning (12110): Net "mSDR_Select[2]" is missing source, defaulting to GNDWarning (12110): Net "mFL_Select[2]" is missing source, defaulting to GNDWarning (12110): Net "mSR_Select[2]" is missing source, defaulting to GNDWarning: Net is missing source, defaulting to GNDWarning (12110): Net "mSDR_Select[2]" is missing source, defaulting to GNDWarning (12110): Net "mFL_Select[2]" is missing source, defaulting to GNDWarning (12110): Net "mSR_Select[2]" is missing source, defaulting to GNDWarning: Net is missing source, defaulting to GNDWarning (12110): Net "mSDR_Select[2]" is missing source, defaulting to GNDWarning (12110): Net "mFL_Select[2]" is missing source, defaulting to GNDWarning (12110): Net "mSR_Select[2]" is missing source, defaulting to GNDWarning: Net is missing source, defaulting to GNDWarning (12110): Net "mSDR_Select[2]" is missing source, defaulting to GNDWarning (12110): Net "mFL_Select[2]" is missing source, defaulting to GNDWarning (12110): Net "mSR_Select[2]" is missing source, defaulting to GNDWarning: Net is missing source, defaulting to GNDWarning (12110): Net "mSDR_Select[2]" is missing source, defaulting to GNDWarning (12110): Net "mFL_Select[2]" is missing source, defaulting to GNDWarning (12110): Net "mSR_Select[2]" is missing source, defaulting to GNDWarning: 13 hierarchies have connectivity warnings - see the Connectivity Checks report folderInfo: Resynthesizing 0 WYSIWYG logic cells and I/Os using "speed" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouchedWarning: The following nodes have both tri-state and non-tri-state driversWarning: Inserted always-enabled tri-state buffer between "AUD_BCLK" and its non-tri-state driver.Warning: The following bidir pins have no driversWarning: Bidir "SD_DAT3" has no driverWarning: Bidir "SD_CMD" has no driverInfo: Registers with preset signals will power-up highInfo: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-BackInfo: Performing gate-level register retimingInfo: Not allowed to move 384 registersInfo: Not allowed to move at least 5 registers because they are in a sequence of registers directly fed by input pinsInfo: Not allowed to move at least 47 registers because they feed output pins directlyInfo: Not allowed to move at least 166 registers because they are fed by registers in a different clock domainInfo: Not allowed to move at least 161 registers because they feed registers in a different clock domainInfo: Not allowed to move at least 5 registers because they feed clock or asynchronous control signals of other registersInfo: Quartus II software applied gate-level register retiming to 3 clock domainsInfo: Quartus II software applied gate-level register retiming to clock "CLOCK_50": created 2 new registers, removed 0 registers, left 446 registers untouchedInfo: Quartus II software applied gate-level register retiming to clock "Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0": created 1 new registers, removed 0 registers, left 144 registers untouchedInfo: Quartus II software applied gate-level register retiming to clock "VGA_Audio_PLL:p1|altpll:altpll_component|_clk0": created 24 new registers, removed 1 registers, left 35 registers untouchedWarning: TRI or OPNDRN buffers permanently enabledWarning: Node "AUD_BCLK~synth"Warning: Output pins are stuck at VCC or GNDWarning (13410): Pin "UART_TXD" is stuck at GNDWarning (13410): Pin "FL_RST_N" is stuck at VCCWarning (13410): Pin "SRAM_UB_N" is stuck at GNDWarning (13410): Pin "SRAM_LB_N" is stuck at GNDWarning (13410): Pin "SRAM_CE_N" is stuck at GNDWarning (13410): Pin "SD_CLK" is stuck at GNDInfo: 33 registers lost all their fanouts during netlist optimizations. The first 33 are displayed below.Info: Register "ps2_keyboard:u4|m1_state.m1_tx_reset_timer" lost all its fanouts during netlist optimizations.Info: Register "CMD_Decode:u5|mSR_ST~36" lost all its fanouts during netlist optimizations.Info: Register "CMD_Decode:u5|mSR_ST~37" lost all its fanouts during netlist optimizations.Info: Register "CMD_Decode:u5|mSR_ST~38" lost all its fanouts during netlist optimizations.Info: Register "CMD_Decode:u5|mSDR_ST~44" lost all its fanouts during netlist optimizations.Info: Register "CMD_Decode:u5|mSDR_ST~45" lost all its fanouts during netlist optimizations.Info: Register "CMD_Decode:u5|mSDR_ST~46" lost all its fanouts during netlist optimizations.Info: Register "CMD_Decode:u5|mPS2_ST~21" lost all its fanouts during netlist optimizations.Info: Register "CMD_Decode:u5|mPS2_ST~22" lost all its fanouts during netlist optimizations.Info: Register "CMD_Decode:u5|mFL_ST~54" lost all its fanouts during netlist optimizations.Info: Register "CMD_Decode:u5|mFL_ST~55" lost all its fanouts during netlist optimizations.Info: Register "CMD_Decode:u5|mFL_ST~56" lost all its fanouts during netlist optimizations.Info: Register "ps2_keyboard:u4|m1_state~20" lost all its fanouts during netlist optimizations.Info: Register "ps2_keyboard:u4|m1_state~21" lost all its fanouts during netlist optimizations.Info: Register "ps2_keyboard:u4|m1_state~22" lost all its fanouts during netlist optimizations.Info: Register "ps2_keyboard:u4|m1_state~23" lost all its fanouts during netlist optimizations.Info: Register "Multi_Sdram:u3|Sdram_Multiplexer:u0|ST~25" lost all its fanouts during netlist optimizations.Info: Register "Multi_Sdram:u3|Sdram_Multiplexer:u0|ST~26" lost all its fanouts during netlist optimizations.Info: Register "Multi_Flash:u2|Flash_Controller:u1|ST~66" lost all its fanouts during netlist optimizations.Info: Register "Multi_Flash:u2|Flash_Controller:u1|ST~67" lost all its fanouts during netlist optimizations.Info: Register "Multi_Flash:u2|Flash_Controller:u1|ST~68" lost all its fanouts during netlist optimizations.Info: Register "Multi_Flash:u2|Flash_Controller:u1|ST~69" lost all its fanouts during netlist optimizations.Info: Register "Multi_Flash:u2|Flash_Multiplexer:u0|ST~25" lost all its fanouts during netlist optimizations.Info: Register "Multi_Flash:u2|Flash_Multiplexer:u0|ST~26" lost all its fanouts during netlist optimizations.Info: Register "Multi_Flash:u2|Flash_Controller:u1|Cont_DIV[3]" lost all its fanouts during netlist optimizations.Info: Register "Multi_Flash:u2|Flash_Controller:u1|Cont_DIV[4]" lost all its fanouts during netlist optimizations.Info: Register "Multi_Flash:u2|Flash_Controller:u1|Cont_DIV[5]" lost all its fanouts during netlist optimizations.Info: Register "Multi_Flash:u2|Flash_Controller:u1|Cont_DIV[6]" lost all its fanouts during netlist optimizations.Info: Register "Multi_Flash:u2|Flash_Controller:u1|Cont_DIV[7]" lost all its fanouts during netlist optimizations.Info: Register "Multi_Flash:u2|Flash_Controller:u1|Cont_DIV[8]" lost all its fanouts during netlist optimizations.Info: Register "Multi_Flash:u2|Flash_Controller:u1|Cont_DIV[9]" lost all its fanouts during netlist optimizations.Info: Register "Multi_Flash:u2|Flash_Controller:u1|Cont_DIV[10]" lost all its fanouts during netlist optimizations.Info: Register "VGA_OSD_RAM:u9|oRed[9]" lost all its fanouts during netlist optimizations.Warning: Design contains 17 input pin(s) that do not drive logicWarning (15610): No output dependent on input pin "CLOCK_24[0]"Warning (15610): No output dependent on input pin "CLOCK_24[1]"Warning (15610): No output dependent on input pin "CLOCK_27[1]"Warning (15610): No output dependent on input pin "EXT_CLOCK"Warning (15610): No output dependent on input pin "KEY[1]"Warning (15610): No output dependent on input pin "KEY[2]"Warning (15610): No output dependent on input pin "KEY[3]"Warning (15610): No output dependent on input pin "SW[2]"Warning (15610): No output dependent on input pin "SW[3]"Warning (15610): No output dependent on input pin "SW[4]"Warning (15610): No output dependent on input pin "SW[5]"Warning (15610): No output dependent on input pin "SW[6]"Warning (15610): No output dependent on input pin "SW[7]"Warning (15610): No output dependent on input pin "SW[8]"Warning (15610): No output dependent on input pin "SW[9]"Warning (15610): No output dependent on input pin "UART_RXD"Warning (15610): No output dependent on input pin "AUD_ADCDAT"Info: Implemented 2691 device resources after synthesis - the final resource count might be differentInfo: Implemented 27 input pinsInfo: Implemented 139 output pinsInfo: Implemented 117 bidirectional pinsInfo: Implemented 2354 logic cellsInfo: Implemented 51 RAM segmentsInfo: Implemented 2 ClockLock PLLsWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a37" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a38" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a36" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a39" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a33" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a34" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a32" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a35" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a41" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a40" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a43" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a42" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a47" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a45" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a46" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a44" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a50" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a48" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a49" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a5" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a6" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a4" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a7" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a1" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a2" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a0" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a3" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a12" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a8" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a14" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a10" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a13" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a9" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a15" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a11" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a21" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a22" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a20" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a23" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a17" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a18" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a16" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a19" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a27" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a25" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a26" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a24" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a31" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a29" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a30" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a28" has a port clk1 that is stuck at GNDInfo: Quartus II Analysis & Synthesis was successful. 0 errors, 175 warningsInfo: Peak virtual memory: 212 megabytesInfo: Processing ended: Sun Oct 11 12:23:17 2009Info: Elapsed time: 00:01:02Info: Total CPU time (on all processors): 00:00:55