Subversion Repositories 1g_ethernet_dpi

//------------------------------------------------------------------------------
// Title      : Verilog Support Level Module
// File       : tri_mode_ethernet_mac_0_support.v
// Author     : Xilinx Inc.
// -----------------------------------------------------------------------------
// (c) Copyright 2013 Xilinx, Inc. All rights reserved.
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// -----------------------------------------------------------------------------
// Description: This module holds the support level for the Tri-Mode
//              Ethernet MAC IP.  It contains potentially shareable FPGA
//              resources such as clocking, reset and IDELAYCTRL logic.
//              This can be used as-is in a single core design, or adapted
//              for use with multi-core implementations.
//------------------------------------------------------------------------------
 
 
`timescale 1 ps/1 ps
 
 
//------------------------------------------------------------------------------
// The entity declaration for the block support level
//------------------------------------------------------------------------------
module tri_mode_ethernet_mac_0_support
   (
      input                gtx_clk,
      output               gtx_clk_out,
      output               gtx_clk90_out,
      // Reference clock for IDELAYCTRL's
      input                refclk,
 
       // asynchronous reset
      input                glbl_rstn,
      input                rx_axi_rstn,
      input                tx_axi_rstn,
 
      // Receiver Interface
      //--------------------------
      output               rx_enable,
 
      output      [27:0]   rx_statistics_vector,
      output               rx_statistics_valid,
 
      output               rx_mac_aclk,
      output               rx_reset,
      output      [7:0]    rx_axis_mac_tdata,
      output               rx_axis_mac_tvalid,
      output               rx_axis_mac_tlast,
      output               rx_axis_mac_tuser,
 
 
      // Transmitter Interface
      //-----------------------------
      output               tx_enable,
 
      input       [7:0]    tx_ifg_delay,
      output      [31:0]   tx_statistics_vector,
      output               tx_statistics_valid,
 
      output               tx_mac_aclk,
      output               tx_reset,
      input       [7:0]    tx_axis_mac_tdata,
      input                tx_axis_mac_tvalid,
      input                tx_axis_mac_tlast,
      input                tx_axis_mac_tuser,
      output               tx_axis_mac_tready,
 
      // MAC Control Interface
      //----------------------
      input                pause_req,
      input       [15:0]   pause_val,
 
      output               speedis100,
      output               speedis10100,
 
      // RGMII Interface
      //----------------
      output      [3:0]    rgmii_txd,
      output               rgmii_tx_ctl,
      output               rgmii_txc,
      input       [3:0]    rgmii_rxd,
      input                rgmii_rx_ctl,
      input                rgmii_rxc,
      output               inband_link_status,
      output      [1:0]    inband_clock_speed,
      output               inband_duplex_status,
 
 
      // MDIO Interface
      //---------------
      inout                mdio,
      output               mdc,
 
      // AXI-Lite Interface
      //---------------
      input                s_axi_aclk,
      input                s_axi_resetn,
 
      input       [11:0] s_axi_awaddr,
      input                s_axi_awvalid,
      output               s_axi_awready,
 
      input       [31:0]   s_axi_wdata,
      input                s_axi_wvalid,
      output               s_axi_wready,
 
      output      [1:0]    s_axi_bresp,
      output               s_axi_bvalid,
      input                s_axi_bready,
 
      input       [11:0] s_axi_araddr,
      input                s_axi_arvalid,
      output               s_axi_arready,
 
      output      [31:0]   s_axi_rdata,
      output      [1:0]    s_axi_rresp,
      output               s_axi_rvalid,
      input                s_axi_rready,
 
      output               mac_irq
 
      );
 
  //----------------------------------------------------------------------------
  // Shareable logic
  //----------------------------------------------------------------------------
      wire                        mmcm_out_gtx_clk;
      wire                        mmcm_out_gtx_clk90;
 
      assign gtx_clk_out   = mmcm_out_gtx_clk;
      assign gtx_clk90_out = mmcm_out_gtx_clk90;
 
  // Instantiate the sharable clocking logic
  tri_mode_ethernet_mac_0_support_clocking tri_mode_ethernet_mac_support_clocking_i
  (
      .clk_in1               (gtx_clk),
      .clk_out1              (mmcm_out_gtx_clk),
      .clk_out2              (mmcm_out_gtx_clk90),
      .reset                 (gtx_mmcm_rst),
      .locked                (gtx_mmcm_locked)
 );
 
  // Instantiate the sharable reset logic
  tri_mode_ethernet_mac_0_support_resets  tri_mode_ethernet_mac_support_resets_i (
      .glbl_rstn             (glbl_rstn),
      .refclk                (refclk),
 
      .idelayctrl_ready      (idelayctrl_ready),
 
      .idelayctrl_reset_out  (idelayctrl_reset),
      .gtx_clk               (gtx_clk),
      .gtx_dcm_locked        (gtx_mmcm_locked),
      .gtx_mmcm_rst_out      (gtx_mmcm_rst)
   );
 
   // An IDELAYCTRL primitive needs to be instantiated for the Fixed Tap Delay
   // mode of the IDELAY.
   IDELAYCTRL  #(
      .SIM_DEVICE ("7SERIES")
   )
   tri_mode_ethernet_mac_idelayctrl_common_i (
      .RDY                  (idelayctrl_ready),
      .REFCLK               (refclk),
      .RST                  (idelayctrl_reset)
   );
 
 
   //---------------------------------------------------------------------------
   // Instantiate the TEMAC core
   //---------------------------------------------------------------------------
   tri_mode_ethernet_mac_0 tri_mode_ethernet_mac_i (
      .gtx_clk                     (mmcm_out_gtx_clk),
      .gtx_clk90                   (mmcm_out_gtx_clk90),
       // asynchronous reset
      .glbl_rstn                   (glbl_rstn),
      .rx_axi_rstn                 (rx_axi_rstn),
      .tx_axi_rstn                 (tx_axi_rstn),
 
      // Receiver Interface
      //--------------------------
      .rx_enable                   (rx_enable),
 
      .rx_statistics_vector        (rx_statistics_vector),
      .rx_statistics_valid         (rx_statistics_valid),
 
      .rx_mac_aclk                 (rx_mac_aclk),
      .rx_reset                    (rx_reset),
      .rx_axis_mac_tdata           (rx_axis_mac_tdata),
      .rx_axis_mac_tvalid          (rx_axis_mac_tvalid),
      .rx_axis_mac_tlast           (rx_axis_mac_tlast),
      .rx_axis_mac_tuser           (rx_axis_mac_tuser),
      // Transmitter Interface
      //-----------------------------
      .tx_enable                   (tx_enable),
 
      .tx_ifg_delay                (tx_ifg_delay),
      .tx_statistics_vector        (tx_statistics_vector),
      .tx_statistics_valid         (tx_statistics_valid),
 
      .tx_mac_aclk                 (tx_mac_aclk),
      .tx_reset                    (tx_reset),
      .tx_axis_mac_tdata           (tx_axis_mac_tdata),
      .tx_axis_mac_tvalid          (tx_axis_mac_tvalid),
      .tx_axis_mac_tlast           (tx_axis_mac_tlast),
      .tx_axis_mac_tuser           (tx_axis_mac_tuser),
      .tx_axis_mac_tready          (tx_axis_mac_tready),
 
      // MAC Control Interface
      //----------------------
      .pause_req                   (pause_req),
      .pause_val                   (pause_val),
 
      .speedis100                  (speedis100),
      .speedis10100                (speedis10100),
      // RGMII Interface
      //----------------
      .rgmii_txd                   (rgmii_txd),
      .rgmii_tx_ctl                (rgmii_tx_ctl),
      .rgmii_txc                   (rgmii_txc),
      .rgmii_rxd                   (rgmii_rxd),
      .rgmii_rx_ctl                (rgmii_rx_ctl),
      .rgmii_rxc                   (rgmii_rxc),
      .inband_link_status          (inband_link_status),
      .inband_clock_speed          (inband_clock_speed),
      .inband_duplex_status        (inband_duplex_status),
 
 
      // MDIO Interface
      //---------------
      .mdio                        (mdio),
      .mdc                         (mdc),
 
      // AXI-Lite Interface
      //---------------
      .s_axi_aclk                  (s_axi_aclk),
      .s_axi_resetn                (s_axi_resetn),
 
      .s_axi_awaddr                (s_axi_awaddr),
      .s_axi_awvalid               (s_axi_awvalid),
      .s_axi_awready               (s_axi_awready),
 
      .s_axi_wdata                 (s_axi_wdata),
      .s_axi_wvalid                (s_axi_wvalid),
      .s_axi_wready                (s_axi_wready),
 
      .s_axi_bresp                 (s_axi_bresp),
      .s_axi_bvalid                (s_axi_bvalid),
      .s_axi_bready                (s_axi_bready),
 
      .s_axi_araddr                (s_axi_araddr),
      .s_axi_arvalid               (s_axi_arvalid),
      .s_axi_arready               (s_axi_arready),
 
      .s_axi_rdata                 (s_axi_rdata),
      .s_axi_rresp                 (s_axi_rresp),
      .s_axi_rvalid                (s_axi_rvalid),
      .s_axi_rready                (s_axi_rready),
 
      .mac_irq                     (mac_irq)
 
    );
 
 
endmodule