URL
https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk
Subversion Repositories 6809_6309_compatible_core
[/] [6809_6309_compatible_core/] [trunk/] [sim/] [README.txt] - Rev 2
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MC6809/HD6309 compatible core.
Simulation can be done with icarus verilog.
$ iverilog tb.v ../rtl/verilog/*.v
$ vvp a.out
a dump file dump.vcd will be created. This file can be viewed with GTKWave.
Simulation with other tools is also possible.
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