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https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk
Subversion Repositories 6809_6309_compatible_core
[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [P6809_P6809.srf] - Rev 12
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#Build: Synplify Pro I-2013.09L , Build 064R, Nov 15 2013#install: C:\lscc\diamond\3.1_x64\synpbase#OS: Windows 7 6.1#Hostname: ALE-PC#Implementation: P6809$ Start of Compile#Sun Jul 06 07:46:25 2014Synopsys Verilog Compiler, version comp201309rc, Build 136R, built Nov 18 2013@N|Running in 64-bit modeCopyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\machxo2.v"@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\pmi_def.v"@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\vlog\umr_capim.v"@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\vlog\scemi_objects.v"@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\vlog\scemi_pipes.svh"@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\vlog\hypermods.v"@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v"@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v"@I:"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\defs.v"@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v"@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v"@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v"@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\bios2k.v"@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v"@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\fontrom.v"@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\textmem4k.v"Verilog syntax check successful!File C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v changed - recompilingSelecting top level module CC3_top@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":604:7:604:12|Synthesizing module mul8x8@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":66:7:66:12|Synthesizing module logic8@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":89:7:89:12|Synthesizing module arith8@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":162:7:162:12|Synthesizing module shift8@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":202:7:202:10|Synthesizing module alu8@W: CG532 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":323:0:323:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored@W: CG133 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":239:12:239:13|No assignment to n8@W: CG133 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":239:20:239:21|No assignment to z8@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":133:7:133:13|Synthesizing module arith16@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":329:7:329:11|Synthesizing module alu16@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":412:23:412:29|No assignment to wire arith_h@W: CL169 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":518:0:518:5|Pruning register regq16[15:0]@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":15:7:15:9|Synthesizing module alu@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":191:7:191:13|Synthesizing module calc_ea@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":7:7:7:14|Synthesizing module regblock@W: CG532 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":177:0:177:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":9:7:9:17|Synthesizing module decode_regs@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":155:7:155:15|Synthesizing module decode_op@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":286:7:286:15|Synthesizing module decode_ea@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":312:7:312:16|Synthesizing module decode_alu@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":385:7:385:20|Synthesizing module test_condition@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":10:7:10:16|Synthesizing module MC6809_cpu@N: CG793 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":456:6:456:13|Ignoring system task $display@W: CG532 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":1125:0:1125:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":70:11:70:23|No assignment to wire alu8_o_result@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":71:11:71:20|No assignment to wire alu8_o_CCR@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_write_tfr -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_write_exg -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_write_dest -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_pp_active_reg[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_postbyte[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_mul_cnt -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_indirect_loaded -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_forced_mem_size -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Register bit k_mem_dest[1] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Register bit next_mem_state[1] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Register bit next_mem_state[2] is always 0, optimizing ...@W: CL279 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Pruning register bits 2 to 1 of next_mem_state[5:0]@W: CL260 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Pruning register bit 1 of k_mem_dest[1:0]@N: CG364 :"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI@N: CG364 :"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\machxo2.v":1291:7:1291:11|Synthesizing module DP8KC@N: CG364 :"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\bios2k.v":8:7:8:12|Synthesizing module bios2k@W: CL168 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\bios2k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\fontrom.v":8:7:8:13|Synthesizing module fontrom@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\textmem4k.v":8:7:8:15|Synthesizing module textmem4k@W: CL168 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\textmem4k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":2:7:2:13|Synthesizing module vgatext@N: CG793 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":133:4:133:11|Ignoring system task $display@N: CG512 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":167:6:167:11|System task $write is not supported yet@N: CG512 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":174:6:174:11|System task $write is not supported yet@W: CG532 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":184:0:184:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored@W: CG781 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":94:9:94:9|Undriven input DataInA on instance chars, tying to 0@W: CL271 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Pruning bits 3 to 1 of redr[3:0] -- not in use ...@W: CL271 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Pruning bits 3 to 1 of greenr[3:0] -- not in use ...@W: CL271 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Pruning bits 3 to 1 of bluer[3:0] -- not in use ...@N: CL177 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Sharing sequential element redr.@N: CL177 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Sharing sequential element greenr.@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":10:7:10:13|Synthesizing module CC3_top@W: CG133 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":37:14:37:21|No assignment to clk_div2@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":42:25:42:35|No assignment to wire cpu1_addr_o@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":43:40:43:51|No assignment to wire cpu1_data_in@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":43:54:43:66|No assignment to wire cpu1_data_out@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":44:23:44:29|No assignment to wire cpu1_we@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":44:32:44:38|No assignment to wire cpu1_oe@W: CL156 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":43:54:43:66|*Input cpu1_data_out[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.@W: CL156 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":42:25:42:35|*Input cpu1_addr_o[10:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.@W: CL156 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":146:25:146:30|*Input cpu_we to expression [or] has undriven bits that are tied to 0 -- simulation mismatch possible.@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[0] is always 1, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[1] is always 1, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[2] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[3] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[4] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[5] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[6] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[0] is always 1, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[1] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[2] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[3] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[4] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[5] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[6] is always 0, optimizing ...@W: CL279 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Pruning register bits 5 to 3 of next_push_state[5:0]@W: CL159 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":22:12:22:20|Input debug_clk is unused@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":389:18:389:20|Input port bits 7 to 4 of CCR[7:0] are unused@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":314:18:314:26|Input port bits 5 to 4 of postbyte0[7:0] are unused@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":287:18:287:27|Input port bits 6 to 5 of eapostbyte[7:0] are unused@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":333:18:333:20|Input port bits 7 to 4 of CCR[7:0] are unused@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":206:18:206:20|Input port bits 3 to 2 of CCR[7:0] are unused@W: CL159 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":203:12:203:17|Input clk_in is unused@W: CL159 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":164:18:164:21|Input b_in is unused@W: CL279 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":614:0:614:5|Pruning register bits 15 to 13 of pipe0[15:0]@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":614:0:614:5|Register bit pipe0[12] is always 0, optimizing ...@W: CL260 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":614:0:614:5|Pruning register bit 12 of pipe0[12:0]@ENDAt c_ver Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 87MB peak: 99MB)Process took 0h:00m:02s realtime, 0h:00m:02s cputime# Sun Jul 06 07:46:27 2014###########################################################]Premap ReportSynopsys Lattice Technology Pre-mapping, Version maplat, Build 800R, Built Nov 18 2013 10:58:25Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.Product Version I-2013.09LMapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)@L: C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\P6809_P6809_scck.rptPrinting clock summary report in "C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\P6809_P6809_scck.rpt" file@N: MF248 |Running in 64-bit mode.@N: MF666 |Clock conversion enabledDesign Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 119MB)syn_allowed_resources : blockrams=26 set on top level netlist CC3_topClock Summary**************Start Requested Requested Clock ClockClock Frequency Period Type Group--------------------------------------------------------------------------------------------------------------------CC3_top|clk40_i 1.0 MHz 1000.000 inferred Inferred_clkgroup_0CC3_top|cpu_clk_derived_clock 1.0 MHz 1000.000 derived (from CC3_top|clk40_i) Inferred_clkgroup_0CC3_top|div_derived_clock 1.0 MHz 1000.000 derived (from CC3_top|clk40_i) Inferred_clkgroup_0====================================================================================================================@W: MT529 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\bios2k.v":74:10:74:21|Found inferred clock CC3_top|clk40_i which controls 95 sequential elements including bios.bios2k_0_0_1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.Pre-mapping successful!At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 82MB peak: 146MB)Process took 0h:00m:01s realtime, 0h:00m:01s cputime# Sun Jul 06 07:46:29 2014###########################################################]Map & Optimize ReportSynopsys Lattice Technology Mapper, Version maplat, Build 800R, Built Nov 18 2013 10:58:25Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.Product Version I-2013.09LMapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)@N: MF248 |Running in 64-bit mode.@N: MF666 |Clock conversion enabledDesign Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)Available hyper_sources - for debug and ip modelsNone FoundFinished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 146MB)@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SU[15:0]@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SS[15:0]@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst x_cnt[6:0]@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst y_cnt[6:0]@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst line_cnt[3:0]@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst vsync_cnt[10:0]@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst blink_cnt[5:0]@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst hsync_cnt[10:0]@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputsFinished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 168MB peak: 168MB)@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance cpu0.k_reg_nmi[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance cpu0.k_reg_firq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputsFinished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 164MB peak: 170MB)Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 163MB peak: 177MB)@N: FA113 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":616:12:617:75|Pipelining module pipe0_1[11:0]@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":614:0:614:5|Register pipe0[11:0] pushed in.@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":614:0:614:5|Register pipe1[15:0] pushed in.@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":39:0:39:5|Register rop_in[4:0] pushed in.@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":39:0:39:5|Register ra_in[15:0] pushed in.@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":518:0:518:5|Register reg_n_in pushed in.@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":39:0:39:5|Register rb_in[15:0] pushed in.@N: FX404 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":115:19:115:32|Found addmux in view:work.CC3_top(verilog) inst cpu0.regs.right[15:0] from cpu0.regs.pc_plus_1[15:0]@N: FX404 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":145:35:145:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.a16.q_out_1_i_m2[16:0] from cpu0.alu.alu16.a16.un17_q_out[16:0]@N: FX404 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":146:35:146:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.a16.q_out_2_i_m2[16:0] from cpu0.alu.alu16.a16.un28_q_out[16:0]@N: FX404 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":288:2:288:3|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.k_new_pc_2[15:0] from cpu0.un1_regs_o_pc[15:0]Starting Early Timing Optimization (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 165MB peak: 177MB)Finished Early Timing Optimization (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 165MB peak: 177MB)Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:10s; Memory used current: 164MB peak: 177MB)Finished preparing to map (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 164MB peak: 177MB)Finished technology mapping (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 242MB peak: 246MB)Pass CPU time Worst Slack Luts / Registers------------------------------------------------------------Pass CPU time Worst Slack Luts / Registers------------------------------------------------------------------------------------------------------------------------Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 182MB peak: 246MB)@N: FX164 |The option to pack flops in the IOB has not been specifiedFinished restoring hierarchy (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 183MB peak: 246MB)#### START OF CLOCK OPTIMIZATION REPORT #####[1 non-gated/non-generated clock tree(s) driving 505 clock pin(s) of sequential element(s)0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)301 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks=========================== Non-Gated/Non-Generated Clocks ============================Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance---------------------------------------------------------------------------------------@K:CKID0001 clk40_i port 505 cpu_clk=======================================================================================##### END OF CLOCK OPTIMIZATION REPORT ######]Writing Analyst data base C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\P6809_P6809.srmFinished Writing Netlist Databases (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 185MB peak: 246MB)Writing EDIF Netlist and constraint files@W: MT558 |Unable to locate source for clock CC3_top|div_derived_clock. Clock will not be forward annotated@W: MT558 |Unable to locate source for clock CC3_top|cpu_clk_derived_clock. Clock will not be forward annotatedI-2013.09L@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pFFinished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 189MB peak: 246MB)@W: MT420 |Found inferred clock CC3_top|clk40_i with period 1000.00ns. Please declare a user-defined clock on object "p:clk40_i"##### START OF TIMING REPORT #####[# Timing Report written on Sun Jul 06 07:46:48 2014#Top view: CC3_topRequested Frequency: 1.0 MHzWire load mode: topPaths requested: 5Constraint File(s):@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.Performance Summary*******************Worst slack in design: 979.573Requested Estimated Requested Estimated Clock ClockStarting Clock Frequency Frequency Period Period Slack Type Group------------------------------------------------------------------------------------------------------------------------CC3_top|clk40_i 1.0 MHz 49.0 MHz 1000.000 20.427 979.573 inferred Inferred_clkgroup_0========================================================================================================================Clock Relationships*******************Clocks | rise to rise | fall to fall | rise to fall | fall to rise--------------------------------------------------------------------------------------------------------------------------Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack--------------------------------------------------------------------------------------------------------------------------CC3_top|clk40_i CC3_top|clk40_i | 1000.000 979.573 | No paths - | No paths - | No paths -==========================================================================================================================Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.Interface Information*********************No IO constraint found====================================Detailed Report for Clock: CC3_top|clk40_i====================================Starting Points with Worst Slack********************************Starting ArrivalInstance Reference Type Pin Net Time SlackClock------------------------------------------------------------------------------------------------------cpu0.alu.rb_in[0] CC3_top|clk40_i FD1P3AX Q rb_in[0] 1.228 979.573cpu0.alu.rb_in[1] CC3_top|clk40_i FD1P3AX Q rb_in[1] 1.228 979.716cpu0.alu.rb_in[2] CC3_top|clk40_i FD1P3AX Q rb_in[2] 1.228 979.716cpu0.k_opcode[6] CC3_top|clk40_i FD1P3AX Q k_opcode[6] 1.347 979.827cpu0.k_opcode[7] CC3_top|clk40_i FD1P3AX Q k_opcode[7] 1.339 979.836cpu0.alu.rb_in[4] CC3_top|clk40_i FD1P3AX Q rb_in[4] 1.232 979.855cpu0.alu.rb_in[3] CC3_top|clk40_i FD1P3AX Q rb_in[3] 1.228 979.859cpu0.alu.rb_in_pipe_2 CC3_top|clk40_i FD1P3AX Q rb_in_pipe_2 1.268 979.883cpu0.k_opcode[3] CC3_top|clk40_i FD1P3AX Q k_opcode[3] 1.369 979.909cpu0.k_opcode[2] CC3_top|clk40_i FD1P3AX Q k_opcode[2] 1.368 979.911======================================================================================================Ending Points with Worst Slack******************************Starting RequiredInstance Reference Type Pin Net Time SlackClock----------------------------------------------------------------------------------------------cpu0.regs.SS[14] CC3_top|clk40_i FD1P3AX D SS_s[14] 999.894 979.573cpu0.regs.SS[15] CC3_top|clk40_i FD1P3AX D SS_s[15] 999.894 979.573cpu0.regs.SU[14] CC3_top|clk40_i FD1P3AX D SU_s[14] 999.894 979.573cpu0.regs.SU[15] CC3_top|clk40_i FD1P3AX D SU_s[15] 999.894 979.573cpu0.regs.SS[12] CC3_top|clk40_i FD1P3AX D SS_s[12] 999.894 979.716cpu0.regs.SS[13] CC3_top|clk40_i FD1P3AX D SS_s[13] 999.894 979.716cpu0.regs.SU[12] CC3_top|clk40_i FD1P3AX D SU_s[12] 999.894 979.716cpu0.regs.SU[13] CC3_top|clk40_i FD1P3AX D SU_s[13] 999.894 979.716cpu0.regs.SS[10] CC3_top|clk40_i FD1P3AX D SS_s[10] 999.894 979.859cpu0.regs.SS[11] CC3_top|clk40_i FD1P3AX D SS_s[11] 999.894 979.859==============================================================================================Worst Path Information***********************Path information for path number 1:Requested Period: 1000.000- Setup time: 0.106+ Clock delay at ending point: 0.000 (ideal)= Required time: 999.894- Propagation time: 20.321- Clock delay at starting point: 0.000 (ideal)= Slack (critical) : 979.573Number of logic level(s): 22Starting point: cpu0.alu.rb_in[0] / QEnding point: cpu0.regs.SS[15] / DThe start point is clocked by CC3_top|clk40_i [rising] on pin CKThe end point is clocked by CC3_top|clk40_i [rising] on pin CKInstance / Net Pin Pin Arrival No. ofName Type Name Dir Delay Time Fan Out(s)----------------------------------------------------------------------------------------------------------------cpu0.alu.rb_in[0] FD1P3AX Q Out 1.228 1.228 -rb_in[0] Net - - - - 9cpu0.alu.alu16.a16.un8_q_out_cry_0_0_RNO INV A In 0.000 1.228 -cpu0.alu.alu16.a16.un8_q_out_cry_0_0_RNO INV Z Out 0.568 1.796 -rb_in_i[0] Net - - - - 1cpu0.alu.alu16.a16.un8_q_out_cry_0_0 CCU2D A1 In 0.000 1.796 -cpu0.alu.alu16.a16.un8_q_out_cry_0_0 CCU2D COUT Out 1.545 3.340 -un8_q_out_cry_0 Net - - - - 1cpu0.alu.alu16.a16.un8_q_out_cry_1_0 CCU2D CIN In 0.000 3.340 -cpu0.alu.alu16.a16.un8_q_out_cry_1_0 CCU2D S1 Out 1.549 4.889 -un8_q_out[2] Net - - - - 1cpu0.alu.alu16.a16.q_out_2_i_m2_cry_1_0_RNO_0 ORCALUT4 A In 0.000 4.889 -cpu0.alu.alu16.a16.q_out_2_i_m2_cry_1_0_RNO_0 ORCALUT4 Z Out 1.017 5.906 -q_out_2_i_m2_cry_1_0_RNO_0 Net - - - - 1cpu0.alu.alu16.a16.q_out_2_i_m2_cry_1_0 CCU2D C1 In 0.000 5.906 -cpu0.alu.alu16.a16.q_out_2_i_m2_cry_1_0 CCU2D COUT Out 1.545 7.451 -q_out_2_i_m2_cry_2 Net - - - - 1cpu0.alu.alu16.a16.q_out_2_i_m2_cry_3_0 CCU2D CIN In 0.000 7.451 -cpu0.alu.alu16.a16.q_out_2_i_m2_cry_3_0 CCU2D COUT Out 0.143 7.593 -q_out_2_i_m2_cry_4 Net - - - - 1cpu0.alu.alu16.a16.q_out_2_i_m2_cry_5_0 CCU2D CIN In 0.000 7.593 -cpu0.alu.alu16.a16.q_out_2_i_m2_cry_5_0 CCU2D COUT Out 0.143 7.736 -q_out_2_i_m2_cry_6 Net - - - - 1cpu0.alu.alu16.a16.q_out_2_i_m2_cry_7_0 CCU2D CIN In 0.000 7.736 -cpu0.alu.alu16.a16.q_out_2_i_m2_cry_7_0 CCU2D S0 Out 1.549 9.285 -N_186 Net - - - - 1cpu0.alu.alu16.a16.q_out_3[7] ORCALUT4 B In 0.000 9.285 -cpu0.alu.alu16.a16.q_out_3[7] ORCALUT4 Z Out 1.153 10.438 -arith_q[7] Net - - - - 3cpu0.alu.alu16.q_out_1[7] ORCALUT4 A In 0.000 10.438 -cpu0.alu.alu16.q_out_1[7] ORCALUT4 Z Out 1.017 11.455 -N_63 Net - - - - 1cpu0.alu.alu16.q_out[7] PFUMX ALUT In 0.000 11.455 -cpu0.alu.alu16.q_out[7] PFUMX Z Out 0.286 11.741 -q16_out[7] Net - - - - 2cpu0.alu.q_out[7] ORCALUT4 B In 0.000 11.741 -cpu0.alu.q_out[7] ORCALUT4 Z Out 0.449 12.190 -alu_o_result[7] Net - - - - 1cpu0.alu.alu8.s8.datamux_o_dest[7] PFUMX ALUT In 0.000 12.190 -cpu0.alu.alu8.s8.datamux_o_dest[7] PFUMX Z Out 0.286 12.476 -datamux_o_dest[7] Net - - - - 2cpu0.regs.path_left_data_RNIVJGV[7] ORCALUT4 B In 0.000 12.476 -cpu0.regs.path_left_data_RNIVJGV[7] ORCALUT4 Z Out 1.273 13.749 -left_1[7] Net - - - - 9cpu0.regs.SS_16_0[7] ORCALUT4 B In 0.000 13.749 -cpu0.regs.SS_16_0[7] ORCALUT4 Z Out 1.017 14.766 -N_252 Net - - - - 1cpu0.regs.SS_16[7] ORCALUT4 A In 0.000 14.766 -cpu0.regs.SS_16[7] ORCALUT4 Z Out 1.017 15.782 -SS_16[7] Net - - - - 1cpu0.regs.SS_222_m3 ORCALUT4 B In 0.000 15.782 -cpu0.regs.SS_222_m3 ORCALUT4 Z Out 1.017 16.799 -SS_222_i1_mux Net - - - - 1cpu0.regs.SS_cry_0[6] CCU2D C1 In 0.000 16.799 -cpu0.regs.SS_cry_0[6] CCU2D COUT Out 1.545 18.344 -SS_cry[7] Net - - - - 1cpu0.regs.SS_cry_0[8] CCU2D CIN In 0.000 18.344 -cpu0.regs.SS_cry_0[8] CCU2D COUT Out 0.143 18.486 -SS_cry[9] Net - - - - 1cpu0.regs.SS_cry_0[10] CCU2D CIN In 0.000 18.486 -cpu0.regs.SS_cry_0[10] CCU2D COUT Out 0.143 18.629 -SS_cry[11] Net - - - - 1cpu0.regs.SS_cry_0[12] CCU2D CIN In 0.000 18.629 -cpu0.regs.SS_cry_0[12] CCU2D COUT Out 0.143 18.772 -SS_cry[13] Net - - - - 1cpu0.regs.SS_cry_0[14] CCU2D CIN In 0.000 18.772 -cpu0.regs.SS_cry_0[14] CCU2D S1 Out 1.549 20.321 -SS_s[15] Net - - - - 1cpu0.regs.SS[15] FD1P3AX D In 0.000 20.321 -================================================================================================================##### END OF TIMING REPORT #####]---------------------------------------Resource Usage ReportPart: lcmxo2_7000he-4Register bits: 489 of 6864 (7%)PIC Latch: 0I/O cells: 69Block Rams : 10 of 26 (38%)Details:BB: 8CCU2D: 183DP8KC: 10FD1P3AX: 438FD1P3DX: 6FD1S3AX: 33FD1S3IX: 2GSR: 1IB: 1INV: 12L6MUX21: 30OB: 60OFS1P3DX: 9OFS1P3IX: 1ORCALUT4: 2078PFUMX: 239PUR: 1VHI: 14VLO: 20false: 1true: 7Mapper successful!At Mapper Exit (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:17s; Memory used current: 58MB peak: 246MB)Process took 0h:00m:18s realtime, 0h:00m:17s cputime# Sun Jul 06 07:46:48 2014###########################################################]