URL
https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk
Subversion Repositories 6809_6309_compatible_core
[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [P6809_P6809.tw1] - Rev 10
Compare with Previous | Blame | View Log
Loading design for application trce from file P6809_P6809_map.ncd.Design name: CC3_topNCD version: 3.2Vendor: LATTICEDevice: LCMXO2-7000HEPackage: TQFP144Performance: 4Loading device for application trce from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.Package Status: Final Version 1.36Performance Hardware Data Status: Final) Version 23.4Setup and Hold Report--------------------------------------------------------------------------------Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101Thu Feb 6 15:35:22 2014Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.Copyright (c) 1995 AT&T Corp. All rights reserved.Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.Copyright (c) 2001 Agere Systems All rights reserved.Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.Report Information------------------Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o P6809_P6809.tw1 P6809_P6809_map.ncd P6809_P6809.prfDesign file: P6809_P6809_map.ncdPreference file: P6809_P6809.prfDevice,speed: LCMXO2-7000HE,4Report level: verbose report, limited to 1 item per preference--------------------------------------------------------------------------------BLOCK ASYNCPATHSBLOCK RESETPATHS--------------------------------------------------------------------------------================================================================================Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;4096 items scored, 198 timing errors detected.--------------------------------------------------------------------------------Error: The following path exceeds requirements by 0.564nsLogical Details: Cell type Pin type Cell/ASIC name (clock net +/-)Source: FF Q cpu0/alu/rb_in[0] (from cpu_clkgen +)Destination: FF Data in cpu0/regs/SU[15] (to cpu_clkgen +)Delay: 25.398ns (42.7% logic, 57.3% route), 21 logic levels.Constraint Details:25.398ns physical path delay cpu0/alu/SLICE_215 to cpu0/regs/SLICE_55 exceeds25.000ns delay constraint less0.166ns DIN_SET requirement (totaling 24.834ns) by 0.564nsPhysical Path Details:Data path cpu0/alu/SLICE_215 to cpu0/regs/SLICE_55:Name Fanout Delay (ns) Site ResourceREG_DEL --- 0.452 *SLICE_215.CLK to */SLICE_215.Q0 cpu0/alu/SLICE_215 (from cpu_clkgen)ROUTE 24 e 1.234 */SLICE_215.Q0 to */SLICE_199.A1 cpu0/alu/rb_in[0]CTOF_DEL --- 0.495 */SLICE_199.A1 to */SLICE_199.F1 cpu0/alu/alu16/SLICE_199ROUTE 1 e 1.234 */SLICE_199.F1 to *6/SLICE_99.A1 cpu0/alu/alu16/a16/rb_in_i[0]C1TOFCO_DE --- 0.889 *6/SLICE_99.A1 to */SLICE_99.FCO cpu0/alu/alu16/a16/SLICE_99ROUTE 1 e 0.001 */SLICE_99.FCO to */SLICE_98.FCI cpu0/alu/alu16/a16/un8_q_out_cry_0FCITOF0_DE --- 0.585 */SLICE_98.FCI to *6/SLICE_98.F0 cpu0/alu/alu16/a16/SLICE_98ROUTE 1 e 1.234 *6/SLICE_98.F0 to *SLICE_1214.A0 cpu0/alu/alu16/a16/un8_q_out[1]CTOF_DEL --- 0.495 *SLICE_1214.A0 to *SLICE_1214.F0 cpu0/alu/SLICE_1214ROUTE 1 e 1.234 *SLICE_1214.F0 to */SLICE_116.C0 cpu0/alu/alu16/a16/q_out_2_cry_1_0_RNOC0TOFCO_DE --- 1.023 */SLICE_116.C0 to *SLICE_116.FCO cpu0/alu/alu16/a16/SLICE_116ROUTE 1 e 0.001 *SLICE_116.FCO to *SLICE_115.FCI cpu0/alu/alu16/a16/q_out_2_cry_2FCITOFCO_D --- 0.162 *SLICE_115.FCI to *SLICE_115.FCO cpu0/alu/alu16/a16/SLICE_115ROUTE 1 e 0.001 *SLICE_115.FCO to *SLICE_114.FCI cpu0/alu/alu16/a16/q_out_2_cry_4FCITOFCO_D --- 0.162 *SLICE_114.FCI to *SLICE_114.FCO cpu0/alu/alu16/a16/SLICE_114ROUTE 1 e 0.001 *SLICE_114.FCO to *SLICE_113.FCI cpu0/alu/alu16/a16/q_out_2_cry_6FCITOFCO_D --- 0.162 *SLICE_113.FCI to *SLICE_113.FCO cpu0/alu/alu16/a16/SLICE_113ROUTE 1 e 0.001 *SLICE_113.FCO to *SLICE_112.FCI cpu0/alu/alu16/a16/q_out_2_cry_8FCITOFCO_D --- 0.162 *SLICE_112.FCI to *SLICE_112.FCO cpu0/alu/alu16/a16/SLICE_112ROUTE 1 e 0.001 *SLICE_112.FCO to *SLICE_111.FCI cpu0/alu/alu16/a16/q_out_2_cry_10FCITOF1_DE --- 0.643 *SLICE_111.FCI to */SLICE_111.F1 cpu0/alu/alu16/a16/SLICE_111ROUTE 1 e 1.234 */SLICE_111.F1 to *SLICE_1048.B0 cpu0/alu/alu16/a16/N_2375CTOF_DEL --- 0.495 *SLICE_1048.B0 to *SLICE_1048.F0 cpu0/alu/alu16/SLICE_1048ROUTE 1 e 0.480 *SLICE_1048.F0 to *SLICE_1048.A1 cpu0/alu/alu16/arith_q[12]CTOF_DEL --- 0.495 *SLICE_1048.A1 to *SLICE_1048.F1 cpu0/alu/alu16/SLICE_1048ROUTE 1 e 1.234 *SLICE_1048.F1 to *SLICE_1066.A1 cpu0/alu/alu16/N_2342CTOF_DEL --- 0.495 *SLICE_1066.A1 to *SLICE_1066.F1 cpu0/alu/alu16/SLICE_1066ROUTE 2 e 1.234 *SLICE_1066.F1 to *SLICE_1082.B0 cpu0/alu/q16_out[12]CTOF_DEL --- 0.495 *SLICE_1082.B0 to *SLICE_1082.F0 cpu0/alu/SLICE_1082ROUTE 2 e 1.234 *SLICE_1082.F0 to */SLICE_363.A0 cpu0/datamux_o_dest[12]CTOF_DEL --- 0.495 */SLICE_363.A0 to */SLICE_363.F0 cpu0/regs/SLICE_363ROUTE 6 e 1.234 */SLICE_363.F0 to *SLICE_1193.B0 cpu0/regs/left_1[12]CTOF_DEL --- 0.495 *SLICE_1193.B0 to *SLICE_1193.F0 cpu0/regs/SLICE_1193ROUTE 1 e 1.234 *SLICE_1193.F0 to */SLICE_951.A1 cpu0/regs/N_291CTOF_DEL --- 0.495 */SLICE_951.A1 to */SLICE_951.F1 cpu0/regs/SLICE_951ROUTE 1 e 0.480 */SLICE_951.F1 to */SLICE_951.B0 cpu0/regs/SU_16[12]CTOF_DEL --- 0.495 */SLICE_951.B0 to */SLICE_951.F0 cpu0/regs/SLICE_951ROUTE 1 e 1.234 */SLICE_951.F0 to *s/SLICE_56.C0 cpu0/regs/SU_219_i1_muxC0TOFCO_DE --- 1.023 *s/SLICE_56.C0 to */SLICE_56.FCO cpu0/regs/SLICE_56ROUTE 1 e 0.001 */SLICE_56.FCO to */SLICE_55.FCI cpu0/regs/SU_cry[13]FCITOF1_DE --- 0.643 */SLICE_55.FCI to *s/SLICE_55.F1 cpu0/regs/SLICE_55ROUTE 1 e 0.001 *s/SLICE_55.F1 to */SLICE_55.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)--------25.398 (42.7% logic, 57.3% route), 21 logic levels.Warning: 39.118MHz is the maximum frequency for this preference.Report Summary------------------------------------------------------------------------------------------Preference | Constraint| Actual|Levels----------------------------------------------------------------------------| | |FREQUENCY NET "cpu_clkgen" 40.000000 | | |MHz ; | 40.000 MHz| 39.118 MHz| 21 *| | |----------------------------------------------------------------------------1 preference(marked by "*" above) not met.----------------------------------------------------------------------------Critical Nets | Loads| Errors| % of total----------------------------------------------------------------------------cpu0/alu/alu16/N_2342 | 1| 178| 89.90%| | |cpu0/alu/q16_out[12] | 2| 178| 89.90%| | |cpu0/alu/alu16/a16/q_out_2_cry_10 | 1| 178| 89.90%| | |cpu0/alu/alu16/arith_q[12] | 1| 178| 89.90%| | |cpu0/alu/alu16/a16/N_2375 | 1| 178| 89.90%| | |cpu0/datamux_o_dest[12] | 2| 178| 89.90%| | |cpu0/regs/left_1[12] | 6| 178| 89.90%| | |cpu0/alu/alu16/a16/q_out_2_cry_8 | 1| 124| 62.63%| | |cpu0/alu/alu16/a16/un8_q_out_cry_4 | 1| 122| 61.62%| | |cpu0/alu/alu16/a16/un8_q_out_cry_2 | 1| 106| 53.54%| | |cpu0/alu/alu16/a16/un8_q_out_cry_6 | 1| 104| 52.53%| | |cpu0/regs/SS_cry[13] | 1| 99| 50.00%| | |cpu0/regs/SU_cry[13] | 1| 99| 50.00%| | |cpu0/regs/N_255 | 1| 89| 44.95%| | |cpu0/regs/N_291 | 1| 89| 44.95%| | |cpu0/regs/SS_235_i1_mux | 1| 89| 44.95%| | |cpu0/regs/SS_16[12] | 1| 89| 44.95%| | |cpu0/regs/SU_219_i1_mux | 1| 89| 44.95%| | |cpu0/regs/SU_16[12] | 1| 89| 44.95%| | |cpu0/alu/alu16/a16/q_out_2_cry_6 | 1| 78| 39.39%| | |cpu0/alu/alu16/a16/rb_in_i[0] | 1| 58| 29.29%| | |cpu0/alu/alu16/a16/un8_q_out_cry_0 | 1| 58| 29.29%| | |cpu0/alu/rb_in[0] | 24| 58| 29.29%| | |cpu0/regs/SS_s[15] | 1| 55| 27.78%| | |cpu0/regs/SU_s[15] | 1| 55| 27.78%| | |cpu0/alu/alu16/a16/un8_q_out_cry_8 | 1| 54| 27.27%| | |cpu0/alu/alu16/a16/q_out_2_cry_4 | 1| 46| 23.23%| | |cpu0/regs/SS_s[14] | 1| 44| 22.22%| | |cpu0/regs/SU_s[14] | 1| 44| 22.22%| | |cpu0/alu/alu16/a16/rb_in_i[1] | 1| 34| 17.17%| | |cpu0/alu/rb_in[1] | 24| 34| 17.17%| | |cpu0/alu/alu16/a16/rb_in_i[2] | 1| 32| 16.16%| | |cpu0/alu/rb_in[2] | 21| 32| 16.16%| | |cpu0/alu/alu16/a16/q_out_2_cry_9_0_RNO | 1| 30| 15.15%| | |cpu0/alu/alu16/a16/un8_q_out[9] | 1| 30| 15.15%| | |cpu0/alu/alu16/a16/q_out_2_cry_7_0_RNO | 1| 28| 14.14%| | |cpu0/alu/alu16/a16/un8_q_out[7] | 1| 28| 14.14%| | |cpu0/alu/alu16/a16/rb_in_i[4] | 1| 24| 12.12%| | |cpu0/alu/alu16/a16/rb_in_i[3] | 1| 24| 12.12%| | |cpu0/alu/alu16/a16/q_out_2_cry_9_0_RNO_0| 1| 24| 12.12%| | |cpu0/alu/alu16/a16/un8_q_out[10] | 1| 24| 12.12%| | |cpu0/alu/alu16/a16/q_out_2_cry_7_0_RNO_0| 1| 24| 12.12%| | |cpu0/alu/alu16/a16/un8_q_out[8] | 1| 24| 12.12%| | |cpu0/alu/rb_in[4] | 21| 24| 12.12%| | |cpu0/alu/rb_in[3] | 22| 24| 12.12%| | |cpu0/alu/alu16/a16/q_out_2_cry_5_0_RNO | 1| 22| 11.11%| | |cpu0/alu/alu16/a16/un8_q_out[5] | 1| 22| 11.11%| | |cpu0/alu/alu16/a16/q_out_2_cry_5_0_RNO_0| 1| 20| 10.10%| | |cpu0/alu/alu16/a16/un8_q_out[6] | 1| 20| 10.10%| | |cpu0/alu/alu16/a16/q_out_2_cry_3_0_RNO | 1| 20| 10.10%| | |cpu0/alu/alu16/a16/un8_q_out[3] | 1| 20| 10.10%| | |----------------------------------------------------------------------------Clock Domains Analysis------------------------Found 1 clocks:Clock Domain: cpu_clkgen Source: clk40_i.PAD Loads: 367Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;Timing summary (Setup):---------------Timing errors: 198 Score: 60114Cumulative negative slack: 60114Constraints cover 1107881 paths, 1 nets, and 9190 connections (95.5% coverage)--------------------------------------------------------------------------------Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101Thu Feb 6 15:35:22 2014Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.Copyright (c) 1995 AT&T Corp. All rights reserved.Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.Copyright (c) 2001 Agere Systems All rights reserved.Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.Report Information------------------Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o P6809_P6809.tw1 P6809_P6809_map.ncd P6809_P6809.prfDesign file: P6809_P6809_map.ncdPreference file: P6809_P6809.prfDevice,speed: LCMXO2-7000HE,MReport level: verbose report, limited to 1 item per preference--------------------------------------------------------------------------------BLOCK ASYNCPATHSBLOCK RESETPATHS--------------------------------------------------------------------------------================================================================================Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;4096 items scored, 0 timing errors detected.--------------------------------------------------------------------------------Passed: The following path meets requirements by 0.386nsLogical Details: Cell type Pin type Cell/ASIC name (clock net +/-)Source: FF Q reset_cnt[0] (from cpu_clkgen +)Destination: FF Data in reset_cnt[0] (to cpu_clkgen +)Delay: 0.330ns (39.7% logic, 60.3% route), 1 logic levels.Constraint Details:0.330ns physical path delay SLICE_444 to SLICE_444 meets-0.056ns LSR_HLD and0.000ns delay constraint requirement (totaling -0.056ns) by 0.386nsPhysical Path Details:Data path SLICE_444 to SLICE_444:Name Fanout Delay (ns) Site ResourceREG_DEL --- 0.131 SLICE_444.CLK to SLICE_444.Q0 SLICE_444 (from cpu_clkgen)ROUTE 5 e 0.199 SLICE_444.Q0 to SLICE_444.LSR reset_cnt[0] (to cpu_clkgen)--------0.330 (39.7% logic, 60.3% route), 1 logic levels.Report Summary------------------------------------------------------------------------------------------Preference(MIN Delays) | Constraint| Actual|Levels----------------------------------------------------------------------------| | |FREQUENCY NET "cpu_clkgen" 40.000000 | | |MHz ; | -| -| 1| | |----------------------------------------------------------------------------All preferences were met.Clock Domains Analysis------------------------Found 1 clocks:Clock Domain: cpu_clkgen Source: clk40_i.PAD Loads: 367Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;Timing summary (Hold):---------------Timing errors: 0 Score: 0Cumulative negative slack: 0Constraints cover 1107881 paths, 1 nets, and 9531 connections (99.1% coverage)Timing summary (Setup and Hold):---------------Timing errors: 198 (setup), 0 (hold)Score: 60114 (setup), 0 (hold)Cumulative negative slack: 60114 (60114+0)----------------------------------------------------------------------------------------------------------------------------------------------------------------