URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk
Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [P6809_P6809.twr] - Rev 12

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Loading design for application trce from file p6809_p6809.ncd.
Design name: CC3_top
NCD version: 3.2
Vendor:      LATTICE
Device:      LCMXO2-7000HE
Package:     TQFP144
Performance: 4
Loading device for application trce from file 'xo2c7000.nph' in environment: C:/lscc/diamond/3.1_x64/ispfpga.
Package Status:                     Final          Version 1.36
Performance Hardware Data Status:   Final)         Version 23.4
Setup and Hold Report

--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.1.0.96
Sun Jul 06 07:47:15 2014

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2014 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr -gui P6809_P6809.ncd P6809_P6809.prf 
Design file:     p6809_p6809.ncd
Preference file: p6809_p6809.prf
Device,speed:    LCMXO2-7000HE,4
Report level:    verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------

Report Type:     based on TRACE automatically generated preferences
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------



================================================================================
Preference: FREQUENCY NET "clk40_i_c" 111.645000 MHz ;
            4096 items scored, 4096 timing errors detected.
--------------------------------------------------------------------------------


Error: The following path exceeds requirements by 24.781ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              cpu0/k_opcode[7]  (from clk40_i_c +)
   Destination:    FF         Data in        cpu0/regs/SS[15]  (to clk40_i_c +)

   Delay:              33.571ns  (26.7% logic, 73.3% route), 18 logic levels.

 Constraint Details:

     33.571ns physical path delay cpu0/SLICE_1217 to cpu0/regs/SLICE_64 exceeds
      8.956ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 8.790ns) by 24.781ns

 Physical Path Details:

      Data path cpu0/SLICE_1217 to cpu0/regs/SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452    R12C21C.CLK to     R12C21C.Q1 cpu0/SLICE_1217 (from clk40_i_c)
ROUTE        42     3.151     R12C21C.Q1 to     R18C26B.C1 cpu0/k_opcode[7]
CTOF_DEL    ---     0.495     R18C26B.C1 to     R18C26B.F1 cpu0/SLICE_726
ROUTE        13     2.235     R18C26B.F1 to     R19C25B.A1 cpu0/state133_3
CTOF_DEL    ---     0.495     R19C25B.A1 to     R19C25B.F1 cpu0/dec_regs/SLICE_659
ROUTE         1     0.436     R19C25B.F1 to     R19C25B.C0 cpu0/dec_regs/un1_path_left_addr85_1_1_2
CTOF_DEL    ---     0.495     R19C25B.C0 to     R19C25B.F0 cpu0/dec_regs/SLICE_659
ROUTE         2     1.343     R19C25B.F0 to     R18C24D.B1 cpu0/dec_regs/un1_path_left_addr85_1_0
CTOF_DEL    ---     0.495     R18C24D.B1 to     R18C24D.F1 cpu0/SLICE_766
ROUTE         1     0.623     R18C24D.F1 to     R17C24A.D1 cpu0/dec_regs/un1_path_left_addr75_1_4
CTOF_DEL    ---     0.495     R17C24A.D1 to     R17C24A.F1 cpu0/dec_regs/SLICE_813
ROUTE         6     0.675     R17C24A.F1 to     R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
CTOF_DEL    ---     0.495     R15C24D.D1 to     R15C24D.F1 cpu0/dec_regs/SLICE_806
ROUTE         8     0.772     R15C24D.F1 to     R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
CTOF_DEL    ---     0.495     R15C24A.C1 to     R15C24A.F1 cpu0/dec_regs/SLICE_802
ROUTE         5     1.441     R15C24A.F1 to     R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
MTOOFX_DEL  ---     0.376     R17C25D.M0 to   R17C25D.OFX0 cpu0/dec_regs/SLICE_264
ROUTE         5     1.882   R17C25D.OFX0 to     R18C22B.A1 cpu0/dec_o_left_path_addr[3]
CTOF_DEL    ---     0.495     R18C22B.A1 to     R18C22B.F1 cpu0/dec_regs/SLICE_846
ROUTE        25     3.725     R18C22B.F1 to      R9C25A.A0 cpu0/dec_o_alu_size
CTOF_DEL    ---     0.495      R9C25A.A0 to      R9C25A.F0 cpu0/SLICE_862
ROUTE         2     2.557      R9C25A.F0 to      R9C20D.B1 cpu0/datamux_o_dest[11]
CTOF_DEL    ---     0.495      R9C20D.B1 to      R9C20D.F1 cpu0/regs/SLICE_945
ROUTE         6     2.382      R9C20D.F1 to     R10C16B.D0 cpu0/regs/left_1[11]
CTOF_DEL    ---     0.495     R10C16B.D0 to     R10C16B.F0 cpu0/regs/SLICE_1220
ROUTE         1     1.450     R10C16B.F0 to     R10C12D.B1 cpu0/regs/N_256
CTOF_DEL    ---     0.495     R10C12D.B1 to     R10C12D.F1 cpu0/regs/SLICE_934
ROUTE         1     0.436     R10C12D.F1 to     R10C12D.C0 cpu0/regs/SS_16[11]
CTOF_DEL    ---     0.495     R10C12D.C0 to     R10C12D.F0 cpu0/regs/SLICE_934
ROUTE         1     1.506     R10C12D.F0 to     R11C12C.C1 cpu0/regs/SS_226_i1_mux
C1TOFCO_DE  ---     0.889     R11C12C.C1 to    R11C12C.FCO cpu0/regs/SLICE_66
ROUTE         1     0.000    R11C12C.FCO to    R11C12D.FCI cpu0/regs/SS_cry[11]
FCITOFCO_D  ---     0.162    R11C12D.FCI to    R11C12D.FCO cpu0/regs/SLICE_65
ROUTE         1     0.000    R11C12D.FCO to    R11C13A.FCI cpu0/regs/SS_cry[13]
FCITOF1_DE  ---     0.643    R11C13A.FCI to     R11C13A.F1 cpu0/regs/SLICE_64
ROUTE         1     0.000     R11C13A.F1 to    R11C13A.DI1 cpu0/regs/SS_s[15] (to clk40_i_c)
                  --------
                   33.571   (26.7% logic, 73.3% route), 18 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to cpu0/SLICE_1217:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     2.399       27.PADDI to    R12C21C.CLK clk40_i_c
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to cpu0/regs/SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     2.399       27.PADDI to    R11C13A.CLK clk40_i_c
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 24.723ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              cpu0/k_opcode[7]  (from clk40_i_c +)
   Destination:    FF         Data in        cpu0/regs/SS[14]  (to clk40_i_c +)

   Delay:              33.513ns  (26.6% logic, 73.4% route), 18 logic levels.

 Constraint Details:

     33.513ns physical path delay cpu0/SLICE_1217 to cpu0/regs/SLICE_64 exceeds
      8.956ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 8.790ns) by 24.723ns

 Physical Path Details:

      Data path cpu0/SLICE_1217 to cpu0/regs/SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452    R12C21C.CLK to     R12C21C.Q1 cpu0/SLICE_1217 (from clk40_i_c)
ROUTE        42     3.151     R12C21C.Q1 to     R18C26B.C1 cpu0/k_opcode[7]
CTOF_DEL    ---     0.495     R18C26B.C1 to     R18C26B.F1 cpu0/SLICE_726
ROUTE        13     2.235     R18C26B.F1 to     R19C25B.A1 cpu0/state133_3
CTOF_DEL    ---     0.495     R19C25B.A1 to     R19C25B.F1 cpu0/dec_regs/SLICE_659
ROUTE         1     0.436     R19C25B.F1 to     R19C25B.C0 cpu0/dec_regs/un1_path_left_addr85_1_1_2
CTOF_DEL    ---     0.495     R19C25B.C0 to     R19C25B.F0 cpu0/dec_regs/SLICE_659
ROUTE         2     1.343     R19C25B.F0 to     R18C24D.B1 cpu0/dec_regs/un1_path_left_addr85_1_0
CTOF_DEL    ---     0.495     R18C24D.B1 to     R18C24D.F1 cpu0/SLICE_766
ROUTE         1     0.623     R18C24D.F1 to     R17C24A.D1 cpu0/dec_regs/un1_path_left_addr75_1_4
CTOF_DEL    ---     0.495     R17C24A.D1 to     R17C24A.F1 cpu0/dec_regs/SLICE_813
ROUTE         6     0.675     R17C24A.F1 to     R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
CTOF_DEL    ---     0.495     R15C24D.D1 to     R15C24D.F1 cpu0/dec_regs/SLICE_806
ROUTE         8     0.772     R15C24D.F1 to     R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
CTOF_DEL    ---     0.495     R15C24A.C1 to     R15C24A.F1 cpu0/dec_regs/SLICE_802
ROUTE         5     1.441     R15C24A.F1 to     R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
MTOOFX_DEL  ---     0.376     R17C25D.M0 to   R17C25D.OFX0 cpu0/dec_regs/SLICE_264
ROUTE         5     1.882   R17C25D.OFX0 to     R18C22B.A1 cpu0/dec_o_left_path_addr[3]
CTOF_DEL    ---     0.495     R18C22B.A1 to     R18C22B.F1 cpu0/dec_regs/SLICE_846
ROUTE        25     3.725     R18C22B.F1 to      R9C25A.A0 cpu0/dec_o_alu_size
CTOF_DEL    ---     0.495      R9C25A.A0 to      R9C25A.F0 cpu0/SLICE_862
ROUTE         2     2.557      R9C25A.F0 to      R9C20D.B1 cpu0/datamux_o_dest[11]
CTOF_DEL    ---     0.495      R9C20D.B1 to      R9C20D.F1 cpu0/regs/SLICE_945
ROUTE         6     2.382      R9C20D.F1 to     R10C16B.D0 cpu0/regs/left_1[11]
CTOF_DEL    ---     0.495     R10C16B.D0 to     R10C16B.F0 cpu0/regs/SLICE_1220
ROUTE         1     1.450     R10C16B.F0 to     R10C12D.B1 cpu0/regs/N_256
CTOF_DEL    ---     0.495     R10C12D.B1 to     R10C12D.F1 cpu0/regs/SLICE_934
ROUTE         1     0.436     R10C12D.F1 to     R10C12D.C0 cpu0/regs/SS_16[11]
CTOF_DEL    ---     0.495     R10C12D.C0 to     R10C12D.F0 cpu0/regs/SLICE_934
ROUTE         1     1.506     R10C12D.F0 to     R11C12C.C1 cpu0/regs/SS_226_i1_mux
C1TOFCO_DE  ---     0.889     R11C12C.C1 to    R11C12C.FCO cpu0/regs/SLICE_66
ROUTE         1     0.000    R11C12C.FCO to    R11C12D.FCI cpu0/regs/SS_cry[11]
FCITOFCO_D  ---     0.162    R11C12D.FCI to    R11C12D.FCO cpu0/regs/SLICE_65
ROUTE         1     0.000    R11C12D.FCO to    R11C13A.FCI cpu0/regs/SS_cry[13]
FCITOF0_DE  ---     0.585    R11C13A.FCI to     R11C13A.F0 cpu0/regs/SLICE_64
ROUTE         1     0.000     R11C13A.F0 to    R11C13A.DI0 cpu0/regs/SS_s[14] (to clk40_i_c)
                  --------
                   33.513   (26.6% logic, 73.4% route), 18 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to cpu0/SLICE_1217:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     2.399       27.PADDI to    R12C21C.CLK clk40_i_c
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to cpu0/regs/SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     2.399       27.PADDI to    R11C13A.CLK clk40_i_c
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 24.619ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              cpu0/k_opcode[7]  (from clk40_i_c +)
   Destination:    FF         Data in        cpu0/regs/SS[13]  (to clk40_i_c +)

   Delay:              33.409ns  (26.3% logic, 73.7% route), 17 logic levels.

 Constraint Details:

     33.409ns physical path delay cpu0/SLICE_1217 to cpu0/regs/SLICE_65 exceeds
      8.956ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 8.790ns) by 24.619ns

 Physical Path Details:

      Data path cpu0/SLICE_1217 to cpu0/regs/SLICE_65:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452    R12C21C.CLK to     R12C21C.Q1 cpu0/SLICE_1217 (from clk40_i_c)
ROUTE        42     3.151     R12C21C.Q1 to     R18C26B.C1 cpu0/k_opcode[7]
CTOF_DEL    ---     0.495     R18C26B.C1 to     R18C26B.F1 cpu0/SLICE_726
ROUTE        13     2.235     R18C26B.F1 to     R19C25B.A1 cpu0/state133_3
CTOF_DEL    ---     0.495     R19C25B.A1 to     R19C25B.F1 cpu0/dec_regs/SLICE_659
ROUTE         1     0.436     R19C25B.F1 to     R19C25B.C0 cpu0/dec_regs/un1_path_left_addr85_1_1_2
CTOF_DEL    ---     0.495     R19C25B.C0 to     R19C25B.F0 cpu0/dec_regs/SLICE_659
ROUTE         2     1.343     R19C25B.F0 to     R18C24D.B1 cpu0/dec_regs/un1_path_left_addr85_1_0
CTOF_DEL    ---     0.495     R18C24D.B1 to     R18C24D.F1 cpu0/SLICE_766
ROUTE         1     0.623     R18C24D.F1 to     R17C24A.D1 cpu0/dec_regs/un1_path_left_addr75_1_4
CTOF_DEL    ---     0.495     R17C24A.D1 to     R17C24A.F1 cpu0/dec_regs/SLICE_813
ROUTE         6     0.675     R17C24A.F1 to     R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
CTOF_DEL    ---     0.495     R15C24D.D1 to     R15C24D.F1 cpu0/dec_regs/SLICE_806
ROUTE         8     0.772     R15C24D.F1 to     R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
CTOF_DEL    ---     0.495     R15C24A.C1 to     R15C24A.F1 cpu0/dec_regs/SLICE_802
ROUTE         5     1.441     R15C24A.F1 to     R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
MTOOFX_DEL  ---     0.376     R17C25D.M0 to   R17C25D.OFX0 cpu0/dec_regs/SLICE_264
ROUTE         5     1.882   R17C25D.OFX0 to     R18C22B.A1 cpu0/dec_o_left_path_addr[3]
CTOF_DEL    ---     0.495     R18C22B.A1 to     R18C22B.F1 cpu0/dec_regs/SLICE_846
ROUTE        25     3.725     R18C22B.F1 to      R9C25A.A0 cpu0/dec_o_alu_size
CTOF_DEL    ---     0.495      R9C25A.A0 to      R9C25A.F0 cpu0/SLICE_862
ROUTE         2     2.557      R9C25A.F0 to      R9C20D.B1 cpu0/datamux_o_dest[11]
CTOF_DEL    ---     0.495      R9C20D.B1 to      R9C20D.F1 cpu0/regs/SLICE_945
ROUTE         6     2.382      R9C20D.F1 to     R10C16B.D0 cpu0/regs/left_1[11]
CTOF_DEL    ---     0.495     R10C16B.D0 to     R10C16B.F0 cpu0/regs/SLICE_1220
ROUTE         1     1.450     R10C16B.F0 to     R10C12D.B1 cpu0/regs/N_256
CTOF_DEL    ---     0.495     R10C12D.B1 to     R10C12D.F1 cpu0/regs/SLICE_934
ROUTE         1     0.436     R10C12D.F1 to     R10C12D.C0 cpu0/regs/SS_16[11]
CTOF_DEL    ---     0.495     R10C12D.C0 to     R10C12D.F0 cpu0/regs/SLICE_934
ROUTE         1     1.506     R10C12D.F0 to     R11C12C.C1 cpu0/regs/SS_226_i1_mux
C1TOFCO_DE  ---     0.889     R11C12C.C1 to    R11C12C.FCO cpu0/regs/SLICE_66
ROUTE         1     0.000    R11C12C.FCO to    R11C12D.FCI cpu0/regs/SS_cry[11]
FCITOF1_DE  ---     0.643    R11C12D.FCI to     R11C12D.F1 cpu0/regs/SLICE_65
ROUTE         1     0.000     R11C12D.F1 to    R11C12D.DI1 cpu0/regs/SS_s[13] (to clk40_i_c)
                  --------
                   33.409   (26.3% logic, 73.7% route), 17 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to cpu0/SLICE_1217:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     2.399       27.PADDI to    R12C21C.CLK clk40_i_c
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to cpu0/regs/SLICE_65:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     2.399       27.PADDI to    R11C12D.CLK clk40_i_c
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 24.561ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              cpu0/k_opcode[7]  (from clk40_i_c +)
   Destination:    FF         Data in        cpu0/regs/SS[12]  (to clk40_i_c +)

   Delay:              33.351ns  (26.2% logic, 73.8% route), 17 logic levels.

 Constraint Details:

     33.351ns physical path delay cpu0/SLICE_1217 to cpu0/regs/SLICE_65 exceeds
      8.956ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 8.790ns) by 24.561ns

 Physical Path Details:

      Data path cpu0/SLICE_1217 to cpu0/regs/SLICE_65:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452    R12C21C.CLK to     R12C21C.Q1 cpu0/SLICE_1217 (from clk40_i_c)
ROUTE        42     3.151     R12C21C.Q1 to     R18C26B.C1 cpu0/k_opcode[7]
CTOF_DEL    ---     0.495     R18C26B.C1 to     R18C26B.F1 cpu0/SLICE_726
ROUTE        13     2.235     R18C26B.F1 to     R19C25B.A1 cpu0/state133_3
CTOF_DEL    ---     0.495     R19C25B.A1 to     R19C25B.F1 cpu0/dec_regs/SLICE_659
ROUTE         1     0.436     R19C25B.F1 to     R19C25B.C0 cpu0/dec_regs/un1_path_left_addr85_1_1_2
CTOF_DEL    ---     0.495     R19C25B.C0 to     R19C25B.F0 cpu0/dec_regs/SLICE_659
ROUTE         2     1.343     R19C25B.F0 to     R18C24D.B1 cpu0/dec_regs/un1_path_left_addr85_1_0
CTOF_DEL    ---     0.495     R18C24D.B1 to     R18C24D.F1 cpu0/SLICE_766
ROUTE         1     0.623     R18C24D.F1 to     R17C24A.D1 cpu0/dec_regs/un1_path_left_addr75_1_4
CTOF_DEL    ---     0.495     R17C24A.D1 to     R17C24A.F1 cpu0/dec_regs/SLICE_813
ROUTE         6     0.675     R17C24A.F1 to     R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
CTOF_DEL    ---     0.495     R15C24D.D1 to     R15C24D.F1 cpu0/dec_regs/SLICE_806
ROUTE         8     0.772     R15C24D.F1 to     R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
CTOF_DEL    ---     0.495     R15C24A.C1 to     R15C24A.F1 cpu0/dec_regs/SLICE_802
ROUTE         5     1.441     R15C24A.F1 to     R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
MTOOFX_DEL  ---     0.376     R17C25D.M0 to   R17C25D.OFX0 cpu0/dec_regs/SLICE_264
ROUTE         5     1.882   R17C25D.OFX0 to     R18C22B.A1 cpu0/dec_o_left_path_addr[3]
CTOF_DEL    ---     0.495     R18C22B.A1 to     R18C22B.F1 cpu0/dec_regs/SLICE_846
ROUTE        25     3.725     R18C22B.F1 to      R9C25A.A0 cpu0/dec_o_alu_size
CTOF_DEL    ---     0.495      R9C25A.A0 to      R9C25A.F0 cpu0/SLICE_862
ROUTE         2     2.557      R9C25A.F0 to      R9C20D.B1 cpu0/datamux_o_dest[11]
CTOF_DEL    ---     0.495      R9C20D.B1 to      R9C20D.F1 cpu0/regs/SLICE_945
ROUTE         6     2.382      R9C20D.F1 to     R10C16B.D0 cpu0/regs/left_1[11]
CTOF_DEL    ---     0.495     R10C16B.D0 to     R10C16B.F0 cpu0/regs/SLICE_1220
ROUTE         1     1.450     R10C16B.F0 to     R10C12D.B1 cpu0/regs/N_256
CTOF_DEL    ---     0.495     R10C12D.B1 to     R10C12D.F1 cpu0/regs/SLICE_934
ROUTE         1     0.436     R10C12D.F1 to     R10C12D.C0 cpu0/regs/SS_16[11]
CTOF_DEL    ---     0.495     R10C12D.C0 to     R10C12D.F0 cpu0/regs/SLICE_934
ROUTE         1     1.506     R10C12D.F0 to     R11C12C.C1 cpu0/regs/SS_226_i1_mux
C1TOFCO_DE  ---     0.889     R11C12C.C1 to    R11C12C.FCO cpu0/regs/SLICE_66
ROUTE         1     0.000    R11C12C.FCO to    R11C12D.FCI cpu0/regs/SS_cry[11]
FCITOF0_DE  ---     0.585    R11C12D.FCI to     R11C12D.F0 cpu0/regs/SLICE_65
ROUTE         1     0.000     R11C12D.F0 to    R11C12D.DI0 cpu0/regs/SS_s[12] (to clk40_i_c)
                  --------
                   33.351   (26.2% logic, 73.8% route), 17 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to cpu0/SLICE_1217:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     2.399       27.PADDI to    R12C21C.CLK clk40_i_c
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to cpu0/regs/SLICE_65:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     2.399       27.PADDI to    R11C12D.CLK clk40_i_c
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 24.119ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              cpu0/k_opcode[7]  (from clk40_i_c +)
   Destination:    FF         Data in        cpu0/regs/SU[15]  (to clk40_i_c +)

   Delay:              32.909ns  (30.3% logic, 69.7% route), 22 logic levels.

 Constraint Details:

     32.909ns physical path delay cpu0/SLICE_1217 to cpu0/regs/SLICE_55 exceeds
      8.956ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 8.790ns) by 24.119ns

 Physical Path Details:

      Data path cpu0/SLICE_1217 to cpu0/regs/SLICE_55:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452    R12C21C.CLK to     R12C21C.Q1 cpu0/SLICE_1217 (from clk40_i_c)
ROUTE        42     3.151     R12C21C.Q1 to     R18C26B.C1 cpu0/k_opcode[7]
CTOF_DEL    ---     0.495     R18C26B.C1 to     R18C26B.F1 cpu0/SLICE_726
ROUTE        13     2.235     R18C26B.F1 to     R19C25B.A1 cpu0/state133_3
CTOF_DEL    ---     0.495     R19C25B.A1 to     R19C25B.F1 cpu0/dec_regs/SLICE_659
ROUTE         1     0.436     R19C25B.F1 to     R19C25B.C0 cpu0/dec_regs/un1_path_left_addr85_1_1_2
CTOF_DEL    ---     0.495     R19C25B.C0 to     R19C25B.F0 cpu0/dec_regs/SLICE_659
ROUTE         2     1.343     R19C25B.F0 to     R18C24D.B1 cpu0/dec_regs/un1_path_left_addr85_1_0
CTOF_DEL    ---     0.495     R18C24D.B1 to     R18C24D.F1 cpu0/SLICE_766
ROUTE         1     0.623     R18C24D.F1 to     R17C24A.D1 cpu0/dec_regs/un1_path_left_addr75_1_4
CTOF_DEL    ---     0.495     R17C24A.D1 to     R17C24A.F1 cpu0/dec_regs/SLICE_813
ROUTE         6     0.675     R17C24A.F1 to     R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
CTOF_DEL    ---     0.495     R15C24D.D1 to     R15C24D.F1 cpu0/dec_regs/SLICE_806
ROUTE         8     0.772     R15C24D.F1 to     R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
CTOF_DEL    ---     0.495     R15C24A.C1 to     R15C24A.F1 cpu0/dec_regs/SLICE_802
ROUTE         5     1.441     R15C24A.F1 to     R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
MTOOFX_DEL  ---     0.376     R17C25D.M0 to   R17C25D.OFX0 cpu0/dec_regs/SLICE_264
ROUTE         5     1.882   R17C25D.OFX0 to     R18C22B.A1 cpu0/dec_o_left_path_addr[3]
CTOF_DEL    ---     0.495     R18C22B.A1 to     R18C22B.F1 cpu0/dec_regs/SLICE_846
ROUTE        25     2.485     R18C22B.F1 to     R10C25C.B1 cpu0/dec_o_alu_size
CTOOFX_DEL  ---     0.721     R10C25C.B1 to   R10C25C.OFX0 cpu0/alu/alu8/datamux_o_dest[2]/SLICE_600
ROUTE         2     1.513   R10C25C.OFX0 to      R9C23D.C0 cpu0/datamux_o_dest[2]
CTOF_DEL    ---     0.495      R9C23D.C0 to      R9C23D.F0 cpu0/regs/SLICE_895
ROUTE         9     2.274      R9C23D.F0 to     R10C16D.A0 cpu0/regs/left_1[2]
CTOF_DEL    ---     0.495     R10C16D.A0 to     R10C16D.F0 cpu0/regs/SLICE_1219
ROUTE         1     1.801     R10C16D.F0 to     R10C10A.A1 cpu0/regs/N_283
CTOF_DEL    ---     0.495     R10C10A.A1 to     R10C10A.F1 cpu0/regs/SLICE_909
ROUTE         1     0.693     R10C10A.F1 to     R10C10A.B0 cpu0/regs/SU_16[2]
CTOF_DEL    ---     0.495     R10C10A.B0 to     R10C10A.F0 cpu0/regs/SLICE_909
ROUTE         1     1.620     R10C10A.F0 to      R12C9C.C0 cpu0/regs/SU_201_i1_mux
C0TOFCO_DE  ---     1.023      R12C9C.C0 to     R12C9C.FCO cpu0/regs/SLICE_61
ROUTE         1     0.000     R12C9C.FCO to     R12C9D.FCI cpu0/regs/SU_cry[3]
FCITOFCO_D  ---     0.162     R12C9D.FCI to     R12C9D.FCO cpu0/regs/SLICE_60
ROUTE         1     0.000     R12C9D.FCO to    R12C10A.FCI cpu0/regs/SU_cry[5]
FCITOFCO_D  ---     0.162    R12C10A.FCI to    R12C10A.FCO cpu0/regs/SLICE_59
ROUTE         1     0.000    R12C10A.FCO to    R12C10B.FCI cpu0/regs/SU_cry[7]
FCITOFCO_D  ---     0.162    R12C10B.FCI to    R12C10B.FCO cpu0/regs/SLICE_58
ROUTE         1     0.000    R12C10B.FCO to    R12C10C.FCI cpu0/regs/SU_cry[9]
FCITOFCO_D  ---     0.162    R12C10C.FCI to    R12C10C.FCO cpu0/regs/SLICE_57
ROUTE         1     0.000    R12C10C.FCO to    R12C10D.FCI cpu0/regs/SU_cry[11]
FCITOFCO_D  ---     0.162    R12C10D.FCI to    R12C10D.FCO cpu0/regs/SLICE_56
ROUTE         1     0.000    R12C10D.FCO to    R12C11A.FCI cpu0/regs/SU_cry[13]
FCITOF1_DE  ---     0.643    R12C11A.FCI to     R12C11A.F1 cpu0/regs/SLICE_55
ROUTE         1     0.000     R12C11A.F1 to    R12C11A.DI1 cpu0/regs/SU_s[15] (to clk40_i_c)
                  --------
                   32.909   (30.3% logic, 69.7% route), 22 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to cpu0/SLICE_1217:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     2.399       27.PADDI to    R12C21C.CLK clk40_i_c
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to cpu0/regs/SLICE_55:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     2.399       27.PADDI to    R12C11A.CLK clk40_i_c
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 24.061ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              cpu0/k_opcode[7]  (from clk40_i_c +)
   Destination:    FF         Data in        cpu0/regs/SU[14]  (to clk40_i_c +)

   Delay:              32.851ns  (30.2% logic, 69.8% route), 22 logic levels.

 Constraint Details:

     32.851ns physical path delay cpu0/SLICE_1217 to cpu0/regs/SLICE_55 exceeds
      8.956ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 8.790ns) by 24.061ns

 Physical Path Details:

      Data path cpu0/SLICE_1217 to cpu0/regs/SLICE_55:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452    R12C21C.CLK to     R12C21C.Q1 cpu0/SLICE_1217 (from clk40_i_c)
ROUTE        42     3.151     R12C21C.Q1 to     R18C26B.C1 cpu0/k_opcode[7]
CTOF_DEL    ---     0.495     R18C26B.C1 to     R18C26B.F1 cpu0/SLICE_726
ROUTE        13     2.235     R18C26B.F1 to     R19C25B.A1 cpu0/state133_3
CTOF_DEL    ---     0.495     R19C25B.A1 to     R19C25B.F1 cpu0/dec_regs/SLICE_659
ROUTE         1     0.436     R19C25B.F1 to     R19C25B.C0 cpu0/dec_regs/un1_path_left_addr85_1_1_2
CTOF_DEL    ---     0.495     R19C25B.C0 to     R19C25B.F0 cpu0/dec_regs/SLICE_659
ROUTE         2     1.343     R19C25B.F0 to     R18C24D.B1 cpu0/dec_regs/un1_path_left_addr85_1_0
CTOF_DEL    ---     0.495     R18C24D.B1 to     R18C24D.F1 cpu0/SLICE_766
ROUTE         1     0.623     R18C24D.F1 to     R17C24A.D1 cpu0/dec_regs/un1_path_left_addr75_1_4
CTOF_DEL    ---     0.495     R17C24A.D1 to     R17C24A.F1 cpu0/dec_regs/SLICE_813
ROUTE         6     0.675     R17C24A.F1 to     R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
CTOF_DEL    ---     0.495     R15C24D.D1 to     R15C24D.F1 cpu0/dec_regs/SLICE_806
ROUTE         8     0.772     R15C24D.F1 to     R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
CTOF_DEL    ---     0.495     R15C24A.C1 to     R15C24A.F1 cpu0/dec_regs/SLICE_802
ROUTE         5     1.441     R15C24A.F1 to     R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
MTOOFX_DEL  ---     0.376     R17C25D.M0 to   R17C25D.OFX0 cpu0/dec_regs/SLICE_264
ROUTE         5     1.882   R17C25D.OFX0 to     R18C22B.A1 cpu0/dec_o_left_path_addr[3]
CTOF_DEL    ---     0.495     R18C22B.A1 to     R18C22B.F1 cpu0/dec_regs/SLICE_846
ROUTE        25     2.485     R18C22B.F1 to     R10C25C.B1 cpu0/dec_o_alu_size
CTOOFX_DEL  ---     0.721     R10C25C.B1 to   R10C25C.OFX0 cpu0/alu/alu8/datamux_o_dest[2]/SLICE_600
ROUTE         2     1.513   R10C25C.OFX0 to      R9C23D.C0 cpu0/datamux_o_dest[2]
CTOF_DEL    ---     0.495      R9C23D.C0 to      R9C23D.F0 cpu0/regs/SLICE_895
ROUTE         9     2.274      R9C23D.F0 to     R10C16D.A0 cpu0/regs/left_1[2]
CTOF_DEL    ---     0.495     R10C16D.A0 to     R10C16D.F0 cpu0/regs/SLICE_1219
ROUTE         1     1.801     R10C16D.F0 to     R10C10A.A1 cpu0/regs/N_283
CTOF_DEL    ---     0.495     R10C10A.A1 to     R10C10A.F1 cpu0/regs/SLICE_909
ROUTE         1     0.693     R10C10A.F1 to     R10C10A.B0 cpu0/regs/SU_16[2]
CTOF_DEL    ---     0.495     R10C10A.B0 to     R10C10A.F0 cpu0/regs/SLICE_909
ROUTE         1     1.620     R10C10A.F0 to      R12C9C.C0 cpu0/regs/SU_201_i1_mux
C0TOFCO_DE  ---     1.023      R12C9C.C0 to     R12C9C.FCO cpu0/regs/SLICE_61
ROUTE         1     0.000     R12C9C.FCO to     R12C9D.FCI cpu0/regs/SU_cry[3]
FCITOFCO_D  ---     0.162     R12C9D.FCI to     R12C9D.FCO cpu0/regs/SLICE_60
ROUTE         1     0.000     R12C9D.FCO to    R12C10A.FCI cpu0/regs/SU_cry[5]
FCITOFCO_D  ---     0.162    R12C10A.FCI to    R12C10A.FCO cpu0/regs/SLICE_59
ROUTE         1     0.000    R12C10A.FCO to    R12C10B.FCI cpu0/regs/SU_cry[7]
FCITOFCO_D  ---     0.162    R12C10B.FCI to    R12C10B.FCO cpu0/regs/SLICE_58
ROUTE         1     0.000    R12C10B.FCO to    R12C10C.FCI cpu0/regs/SU_cry[9]
FCITOFCO_D  ---     0.162    R12C10C.FCI to    R12C10C.FCO cpu0/regs/SLICE_57
ROUTE         1     0.000    R12C10C.FCO to    R12C10D.FCI cpu0/regs/SU_cry[11]
FCITOFCO_D  ---     0.162    R12C10D.FCI to    R12C10D.FCO cpu0/regs/SLICE_56
ROUTE         1     0.000    R12C10D.FCO to    R12C11A.FCI cpu0/regs/SU_cry[13]
FCITOF0_DE  ---     0.585    R12C11A.FCI to     R12C11A.F0 cpu0/regs/SLICE_55
ROUTE         1     0.000     R12C11A.F0 to    R12C11A.DI0 cpu0/regs/SU_s[14] (to clk40_i_c)
                  --------
                   32.851   (30.2% logic, 69.8% route), 22 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to cpu0/SLICE_1217:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     2.399       27.PADDI to    R12C21C.CLK clk40_i_c
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to cpu0/regs/SLICE_55:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     2.399       27.PADDI to    R12C11A.CLK clk40_i_c
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 23.971ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              cpu0/k_opcode[5]  (from clk40_i_c +)
   Destination:    FF         Data in        cpu0/regs/SS[15]  (to clk40_i_c +)

   Delay:              32.761ns  (25.8% logic, 74.2% route), 17 logic levels.

 Constraint Details:

     32.761ns physical path delay cpu0/SLICE_1144 to cpu0/regs/SLICE_64 exceeds
      8.956ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 8.790ns) by 23.971ns

 Physical Path Details:

      Data path cpu0/SLICE_1144 to cpu0/regs/SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452    R12C21A.CLK to     R12C21A.Q1 cpu0/SLICE_1144 (from clk40_i_c)
ROUTE        52     4.508     R12C21A.Q1 to     R19C22A.A0 cpu0/k_opcode[5]
CTOF_DEL    ---     0.495     R19C22A.A0 to     R19C22A.F0 cpu0/SLICE_772
ROUTE         2     1.308     R19C22A.F0 to     R18C24A.A0 cpu0/un1_k_opcode_3_4
CTOF_DEL    ---     0.495     R18C24A.A0 to     R18C24A.F0 cpu0/dec_regs/SLICE_1118
ROUTE         1     0.693     R18C24A.F0 to     R18C24B.B1 cpu0/dec_regs/path_left_addr79
CTOF_DEL    ---     0.495     R18C24B.B1 to     R18C24B.F1 cpu0/dec_regs/SLICE_771
ROUTE         1     0.964     R18C24B.F1 to     R17C24A.A1 cpu0/dec_regs/un1_path_left_addr75_1_0
CTOF_DEL    ---     0.495     R17C24A.A1 to     R17C24A.F1 cpu0/dec_regs/SLICE_813
ROUTE         6     0.675     R17C24A.F1 to     R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
CTOF_DEL    ---     0.495     R15C24D.D1 to     R15C24D.F1 cpu0/dec_regs/SLICE_806
ROUTE         8     0.772     R15C24D.F1 to     R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
CTOF_DEL    ---     0.495     R15C24A.C1 to     R15C24A.F1 cpu0/dec_regs/SLICE_802
ROUTE         5     1.441     R15C24A.F1 to     R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
MTOOFX_DEL  ---     0.376     R17C25D.M0 to   R17C25D.OFX0 cpu0/dec_regs/SLICE_264
ROUTE         5     1.882   R17C25D.OFX0 to     R18C22B.A1 cpu0/dec_o_left_path_addr[3]
CTOF_DEL    ---     0.495     R18C22B.A1 to     R18C22B.F1 cpu0/dec_regs/SLICE_846
ROUTE        25     3.725     R18C22B.F1 to      R9C25A.A0 cpu0/dec_o_alu_size
CTOF_DEL    ---     0.495      R9C25A.A0 to      R9C25A.F0 cpu0/SLICE_862
ROUTE         2     2.557      R9C25A.F0 to      R9C20D.B1 cpu0/datamux_o_dest[11]
CTOF_DEL    ---     0.495      R9C20D.B1 to      R9C20D.F1 cpu0/regs/SLICE_945
ROUTE         6     2.382      R9C20D.F1 to     R10C16B.D0 cpu0/regs/left_1[11]
CTOF_DEL    ---     0.495     R10C16B.D0 to     R10C16B.F0 cpu0/regs/SLICE_1220
ROUTE         1     1.450     R10C16B.F0 to     R10C12D.B1 cpu0/regs/N_256
CTOF_DEL    ---     0.495     R10C12D.B1 to     R10C12D.F1 cpu0/regs/SLICE_934
ROUTE         1     0.436     R10C12D.F1 to     R10C12D.C0 cpu0/regs/SS_16[11]
CTOF_DEL    ---     0.495     R10C12D.C0 to     R10C12D.F0 cpu0/regs/SLICE_934
ROUTE         1     1.506     R10C12D.F0 to     R11C12C.C1 cpu0/regs/SS_226_i1_mux
C1TOFCO_DE  ---     0.889     R11C12C.C1 to    R11C12C.FCO cpu0/regs/SLICE_66
ROUTE         1     0.000    R11C12C.FCO to    R11C12D.FCI cpu0/regs/SS_cry[11]
FCITOFCO_D  ---     0.162    R11C12D.FCI to    R11C12D.FCO cpu0/regs/SLICE_65
ROUTE         1     0.000    R11C12D.FCO to    R11C13A.FCI cpu0/regs/SS_cry[13]
FCITOF1_DE  ---     0.643    R11C13A.FCI to     R11C13A.F1 cpu0/regs/SLICE_64
ROUTE         1     0.000     R11C13A.F1 to    R11C13A.DI1 cpu0/regs/SS_s[15] (to clk40_i_c)
                  --------
                   32.761   (25.8% logic, 74.2% route), 17 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to cpu0/SLICE_1144:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     2.399       27.PADDI to    R12C21A.CLK clk40_i_c
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to cpu0/regs/SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     2.399       27.PADDI to    R11C13A.CLK clk40_i_c
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 23.957ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              cpu0/k_opcode[7]  (from clk40_i_c +)
   Destination:    FF         Data in        cpu0/regs/SU[13]  (to clk40_i_c +)

   Delay:              32.747ns  (29.9% logic, 70.1% route), 21 logic levels.

 Constraint Details:

     32.747ns physical path delay cpu0/SLICE_1217 to cpu0/regs/SLICE_56 exceeds
      8.956ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 8.790ns) by 23.957ns

 Physical Path Details:

      Data path cpu0/SLICE_1217 to cpu0/regs/SLICE_56:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452    R12C21C.CLK to     R12C21C.Q1 cpu0/SLICE_1217 (from clk40_i_c)
ROUTE        42     3.151     R12C21C.Q1 to     R18C26B.C1 cpu0/k_opcode[7]
CTOF_DEL    ---     0.495     R18C26B.C1 to     R18C26B.F1 cpu0/SLICE_726
ROUTE        13     2.235     R18C26B.F1 to     R19C25B.A1 cpu0/state133_3
CTOF_DEL    ---     0.495     R19C25B.A1 to     R19C25B.F1 cpu0/dec_regs/SLICE_659
ROUTE         1     0.436     R19C25B.F1 to     R19C25B.C0 cpu0/dec_regs/un1_path_left_addr85_1_1_2
CTOF_DEL    ---     0.495     R19C25B.C0 to     R19C25B.F0 cpu0/dec_regs/SLICE_659
ROUTE         2     1.343     R19C25B.F0 to     R18C24D.B1 cpu0/dec_regs/un1_path_left_addr85_1_0
CTOF_DEL    ---     0.495     R18C24D.B1 to     R18C24D.F1 cpu0/SLICE_766
ROUTE         1     0.623     R18C24D.F1 to     R17C24A.D1 cpu0/dec_regs/un1_path_left_addr75_1_4
CTOF_DEL    ---     0.495     R17C24A.D1 to     R17C24A.F1 cpu0/dec_regs/SLICE_813
ROUTE         6     0.675     R17C24A.F1 to     R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
CTOF_DEL    ---     0.495     R15C24D.D1 to     R15C24D.F1 cpu0/dec_regs/SLICE_806
ROUTE         8     0.772     R15C24D.F1 to     R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
CTOF_DEL    ---     0.495     R15C24A.C1 to     R15C24A.F1 cpu0/dec_regs/SLICE_802
ROUTE         5     1.441     R15C24A.F1 to     R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
MTOOFX_DEL  ---     0.376     R17C25D.M0 to   R17C25D.OFX0 cpu0/dec_regs/SLICE_264
ROUTE         5     1.882   R17C25D.OFX0 to     R18C22B.A1 cpu0/dec_o_left_path_addr[3]
CTOF_DEL    ---     0.495     R18C22B.A1 to     R18C22B.F1 cpu0/dec_regs/SLICE_846
ROUTE        25     2.485     R18C22B.F1 to     R10C25C.B1 cpu0/dec_o_alu_size
CTOOFX_DEL  ---     0.721     R10C25C.B1 to   R10C25C.OFX0 cpu0/alu/alu8/datamux_o_dest[2]/SLICE_600
ROUTE         2     1.513   R10C25C.OFX0 to      R9C23D.C0 cpu0/datamux_o_dest[2]
CTOF_DEL    ---     0.495      R9C23D.C0 to      R9C23D.F0 cpu0/regs/SLICE_895
ROUTE         9     2.274      R9C23D.F0 to     R10C16D.A0 cpu0/regs/left_1[2]
CTOF_DEL    ---     0.495     R10C16D.A0 to     R10C16D.F0 cpu0/regs/SLICE_1219
ROUTE         1     1.801     R10C16D.F0 to     R10C10A.A1 cpu0/regs/N_283
CTOF_DEL    ---     0.495     R10C10A.A1 to     R10C10A.F1 cpu0/regs/SLICE_909
ROUTE         1     0.693     R10C10A.F1 to     R10C10A.B0 cpu0/regs/SU_16[2]
CTOF_DEL    ---     0.495     R10C10A.B0 to     R10C10A.F0 cpu0/regs/SLICE_909
ROUTE         1     1.620     R10C10A.F0 to      R12C9C.C0 cpu0/regs/SU_201_i1_mux
C0TOFCO_DE  ---     1.023      R12C9C.C0 to     R12C9C.FCO cpu0/regs/SLICE_61
ROUTE         1     0.000     R12C9C.FCO to     R12C9D.FCI cpu0/regs/SU_cry[3]
FCITOFCO_D  ---     0.162     R12C9D.FCI to     R12C9D.FCO cpu0/regs/SLICE_60
ROUTE         1     0.000     R12C9D.FCO to    R12C10A.FCI cpu0/regs/SU_cry[5]
FCITOFCO_D  ---     0.162    R12C10A.FCI to    R12C10A.FCO cpu0/regs/SLICE_59
ROUTE         1     0.000    R12C10A.FCO to    R12C10B.FCI cpu0/regs/SU_cry[7]
FCITOFCO_D  ---     0.162    R12C10B.FCI to    R12C10B.FCO cpu0/regs/SLICE_58
ROUTE         1     0.000    R12C10B.FCO to    R12C10C.FCI cpu0/regs/SU_cry[9]
FCITOFCO_D  ---     0.162    R12C10C.FCI to    R12C10C.FCO cpu0/regs/SLICE_57
ROUTE         1     0.000    R12C10C.FCO to    R12C10D.FCI cpu0/regs/SU_cry[11]
FCITOF1_DE  ---     0.643    R12C10D.FCI to     R12C10D.F1 cpu0/regs/SLICE_56
ROUTE         1     0.000     R12C10D.F1 to    R12C10D.DI1 cpu0/regs/SU_s[13] (to clk40_i_c)
                  --------
                   32.747   (29.9% logic, 70.1% route), 21 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to cpu0/SLICE_1217:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     2.399       27.PADDI to    R12C21C.CLK clk40_i_c
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to cpu0/regs/SLICE_56:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     2.399       27.PADDI to    R12C10D.CLK clk40_i_c
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 23.922ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              cpu0/k_ind_ea[7]  (from clk40_i_c +)
   Destination:    FF         Data in        cpu0/regs/SS[15]  (to clk40_i_c +)

   Delay:              32.712ns  (27.6% logic, 72.4% route), 18 logic levels.

 Constraint Details:

     32.712ns physical path delay SLICE_284 to cpu0/regs/SLICE_64 exceeds
      8.956ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 8.790ns) by 23.922ns

 Physical Path Details:

      Data path SLICE_284 to cpu0/regs/SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452    R14C14A.CLK to     R14C14A.Q1 SLICE_284 (from clk40_i_c)
ROUTE        26     3.767     R14C14A.Q1 to      R5C14B.A1 cpu0/k_ind_ea[7]
CTOF_DEL    ---     0.495      R5C14B.A1 to      R5C14B.F1 cpu0/regs/ea/SLICE_877
ROUTE        18     1.450      R5C14B.F1 to      R5C15D.A1 cpu0/regs/ea/N_62
CTOF_DEL    ---     0.495      R5C15D.A1 to      R5C15D.F1 cpu0/regs/ea/SLICE_668
ROUTE        18     1.939      R5C15D.F1 to      R6C15B.D1 cpu0/regs/ea/N_107
CTOF_DEL    ---     0.495      R6C15B.D1 to      R6C15B.F1 cpu0/regs/ea/SLICE_876
ROUTE        16     2.634      R6C15B.F1 to      R8C12C.A1 cpu0/regs/ea/un1_eapostbyte_12
CTOF_DEL    ---     0.495      R8C12C.A1 to      R8C12C.F1 cpu0/regs/ea/SLICE_1211
ROUTE         1     1.163      R8C12C.F1 to      R8C13D.C0 cpu0/regs/ea/N_77
C0TOFCO_DE  ---     1.023      R8C13D.C0 to     R8C13D.FCO cpu0/regs/ea/SLICE_51
ROUTE         1     0.000     R8C13D.FCO to     R8C14A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
FCITOFCO_D  ---     0.162     R8C14A.FCI to     R8C14A.FCO cpu0/regs/ea/SLICE_50
ROUTE         1     0.000     R8C14A.FCO to     R8C14B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
FCITOFCO_D  ---     0.162     R8C14B.FCI to     R8C14B.FCO cpu0/regs/ea/SLICE_49
ROUTE         1     0.000     R8C14B.FCO to     R8C14C.FCI cpu0/regs/ea/eamem_addr_o_cry_10
FCITOF0_DE  ---     0.585     R8C14C.FCI to      R8C14C.F0 cpu0/regs/ea/SLICE_48
ROUTE         4     3.207      R8C14C.F0 to      R9C22A.A1 cpu0/regs/ea/regs_o_eamem_addr[11]
CTOF_DEL    ---     0.495      R9C22A.A1 to      R9C22A.F1 cpu0/regs/ea/SLICE_1071
ROUTE         1     1.193      R9C22A.F1 to      R9C25A.C0 cpu0/regs/ea/N_1327
CTOF_DEL    ---     0.495      R9C25A.C0 to      R9C25A.F0 cpu0/SLICE_862
ROUTE         2     2.557      R9C25A.F0 to      R9C20D.B1 cpu0/datamux_o_dest[11]
CTOF_DEL    ---     0.495      R9C20D.B1 to      R9C20D.F1 cpu0/regs/SLICE_945
ROUTE         6     2.382      R9C20D.F1 to     R10C16B.D0 cpu0/regs/left_1[11]
CTOF_DEL    ---     0.495     R10C16B.D0 to     R10C16B.F0 cpu0/regs/SLICE_1220
ROUTE         1     1.450     R10C16B.F0 to     R10C12D.B1 cpu0/regs/N_256
CTOF_DEL    ---     0.495     R10C12D.B1 to     R10C12D.F1 cpu0/regs/SLICE_934
ROUTE         1     0.436     R10C12D.F1 to     R10C12D.C0 cpu0/regs/SS_16[11]
CTOF_DEL    ---     0.495     R10C12D.C0 to     R10C12D.F0 cpu0/regs/SLICE_934
ROUTE         1     1.506     R10C12D.F0 to     R11C12C.C1 cpu0/regs/SS_226_i1_mux
C1TOFCO_DE  ---     0.889     R11C12C.C1 to    R11C12C.FCO cpu0/regs/SLICE_66
ROUTE         1     0.000    R11C12C.FCO to    R11C12D.FCI cpu0/regs/SS_cry[11]
FCITOFCO_D  ---     0.162    R11C12D.FCI to    R11C12D.FCO cpu0/regs/SLICE_65
ROUTE         1     0.000    R11C12D.FCO to    R11C13A.FCI cpu0/regs/SS_cry[13]
FCITOF1_DE  ---     0.643    R11C13A.FCI to     R11C13A.F1 cpu0/regs/SLICE_64
ROUTE         1     0.000     R11C13A.F1 to    R11C13A.DI1 cpu0/regs/SS_s[15] (to clk40_i_c)
                  --------
                   32.712   (27.6% logic, 72.4% route), 18 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to SLICE_284:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     2.399       27.PADDI to    R14C14A.CLK clk40_i_c
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to cpu0/regs/SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     2.399       27.PADDI to    R11C13A.CLK clk40_i_c
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 23.913ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              cpu0/k_opcode[5]  (from clk40_i_c +)
   Destination:    FF         Data in        cpu0/regs/SS[14]  (to clk40_i_c +)

   Delay:              32.703ns  (25.7% logic, 74.3% route), 17 logic levels.

 Constraint Details:

     32.703ns physical path delay cpu0/SLICE_1144 to cpu0/regs/SLICE_64 exceeds
      8.956ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 8.790ns) by 23.913ns

 Physical Path Details:

      Data path cpu0/SLICE_1144 to cpu0/regs/SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452    R12C21A.CLK to     R12C21A.Q1 cpu0/SLICE_1144 (from clk40_i_c)
ROUTE        52     4.508     R12C21A.Q1 to     R19C22A.A0 cpu0/k_opcode[5]
CTOF_DEL    ---     0.495     R19C22A.A0 to     R19C22A.F0 cpu0/SLICE_772
ROUTE         2     1.308     R19C22A.F0 to     R18C24A.A0 cpu0/un1_k_opcode_3_4
CTOF_DEL    ---     0.495     R18C24A.A0 to     R18C24A.F0 cpu0/dec_regs/SLICE_1118
ROUTE         1     0.693     R18C24A.F0 to     R18C24B.B1 cpu0/dec_regs/path_left_addr79
CTOF_DEL    ---     0.495     R18C24B.B1 to     R18C24B.F1 cpu0/dec_regs/SLICE_771
ROUTE         1     0.964     R18C24B.F1 to     R17C24A.A1 cpu0/dec_regs/un1_path_left_addr75_1_0
CTOF_DEL    ---     0.495     R17C24A.A1 to     R17C24A.F1 cpu0/dec_regs/SLICE_813
ROUTE         6     0.675     R17C24A.F1 to     R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
CTOF_DEL    ---     0.495     R15C24D.D1 to     R15C24D.F1 cpu0/dec_regs/SLICE_806
ROUTE         8     0.772     R15C24D.F1 to     R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
CTOF_DEL    ---     0.495     R15C24A.C1 to     R15C24A.F1 cpu0/dec_regs/SLICE_802
ROUTE         5     1.441     R15C24A.F1 to     R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
MTOOFX_DEL  ---     0.376     R17C25D.M0 to   R17C25D.OFX0 cpu0/dec_regs/SLICE_264
ROUTE         5     1.882   R17C25D.OFX0 to     R18C22B.A1 cpu0/dec_o_left_path_addr[3]
CTOF_DEL    ---     0.495     R18C22B.A1 to     R18C22B.F1 cpu0/dec_regs/SLICE_846
ROUTE        25     3.725     R18C22B.F1 to      R9C25A.A0 cpu0/dec_o_alu_size
CTOF_DEL    ---     0.495      R9C25A.A0 to      R9C25A.F0 cpu0/SLICE_862
ROUTE         2     2.557      R9C25A.F0 to      R9C20D.B1 cpu0/datamux_o_dest[11]
CTOF_DEL    ---     0.495      R9C20D.B1 to      R9C20D.F1 cpu0/regs/SLICE_945
ROUTE         6     2.382      R9C20D.F1 to     R10C16B.D0 cpu0/regs/left_1[11]
CTOF_DEL    ---     0.495     R10C16B.D0 to     R10C16B.F0 cpu0/regs/SLICE_1220
ROUTE         1     1.450     R10C16B.F0 to     R10C12D.B1 cpu0/regs/N_256
CTOF_DEL    ---     0.495     R10C12D.B1 to     R10C12D.F1 cpu0/regs/SLICE_934
ROUTE         1     0.436     R10C12D.F1 to     R10C12D.C0 cpu0/regs/SS_16[11]
CTOF_DEL    ---     0.495     R10C12D.C0 to     R10C12D.F0 cpu0/regs/SLICE_934
ROUTE         1     1.506     R10C12D.F0 to     R11C12C.C1 cpu0/regs/SS_226_i1_mux
C1TOFCO_DE  ---     0.889     R11C12C.C1 to    R11C12C.FCO cpu0/regs/SLICE_66
ROUTE         1     0.000    R11C12C.FCO to    R11C12D.FCI cpu0/regs/SS_cry[11]
FCITOFCO_D  ---     0.162    R11C12D.FCI to    R11C12D.FCO cpu0/regs/SLICE_65
ROUTE         1     0.000    R11C12D.FCO to    R11C13A.FCI cpu0/regs/SS_cry[13]
FCITOF0_DE  ---     0.585    R11C13A.FCI to     R11C13A.F0 cpu0/regs/SLICE_64
ROUTE         1     0.000     R11C13A.F0 to    R11C13A.DI0 cpu0/regs/SS_s[14] (to clk40_i_c)
                  --------
                   32.703   (25.7% logic, 74.3% route), 17 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to cpu0/SLICE_1144:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     2.399       27.PADDI to    R12C21A.CLK clk40_i_c
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to cpu0/regs/SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     2.399       27.PADDI to    R11C13A.CLK clk40_i_c
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.

Warning:  29.641MHz is the maximum frequency for this preference.

Report Summary
--------------
----------------------------------------------------------------------------
Preference                              |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
FREQUENCY NET "clk40_i_c" 111.645000    |             |             |
MHz ;                                   |  111.645 MHz|   29.641 MHz|  18 *
                                        |             |             |
----------------------------------------------------------------------------


1 preference(marked by "*" above) not met.

----------------------------------------------------------------------------
Critical Nets                           |   Loads|  Errors| % of total
----------------------------------------------------------------------------
cpu0/dec_o_alu_size                     |      25|    3143|     76.73%
                                        |        |        |
cpu0/dec_o_left_path_addr[3]            |       5|    2799|     68.33%
                                        |        |        |
cpu0/dec_regs/un1_path_left_addr75_1    |       6|    2724|     66.50%
                                        |        |        |
cpu0/dec_regs/path_left_addr_2_sqmuxa   |       8|    2457|     59.99%
                                        |        |        |
cpu0/dec_regs/path_left_addr_o_sn_N_2   |       5|    2152|     52.54%
                                        |        |        |
cpu0/dec_regs/un1_path_left_addr85_1_0  |       2|    1902|     46.44%
                                        |        |        |
cpu0/dec_regs/un1_path_left_addr75_1_4  |       1|    1706|     41.65%
                                        |        |        |
cpu0/regs/SU_cry[9]                     |       1|    1283|     31.32%
                                        |        |        |
cpu0/dec_regs/un1_path_left_addr85_1_1_2|       1|    1267|     30.93%
                                        |        |        |
cpu0/regs/SS_cry[11]                    |       1|    1111|     27.12%
                                        |        |        |
cpu0/regs/SU_cry[5]                     |       1|    1107|     27.03%
                                        |        |        |
cpu0/state133_3                         |      13|    1096|     26.76%
                                        |        |        |
cpu0/regs/SU_cry[11]                    |       1|    1045|     25.51%
                                        |        |        |
cpu0/regs/SU_cry[7]                     |       1|    1024|     25.00%
                                        |        |        |
cpu0/regs/left_1[11]                    |       6|     955|     23.32%
                                        |        |        |
cpu0/datamux_o_dest[11]                 |       2|     955|     23.32%
                                        |        |        |
cpu0/k_opcode[7]                        |      42|     951|     23.22%
                                        |        |        |
cpu0/regs/SU_cry[3]                     |       1|     891|     21.75%
                                        |        |        |
cpu0/regs/ea/N_107                      |      18|     882|     21.53%
                                        |        |        |
cpu0/regs/ea/un1_eapostbyte_12          |      16|     864|     21.09%
                                        |        |        |
cpu0/regs/N_256                         |       1|     852|     20.80%
                                        |        |        |
cpu0/regs/SS_226_i1_mux                 |       1|     852|     20.80%
                                        |        |        |
cpu0/regs/SS_16[11]                     |       1|     852|     20.80%
                                        |        |        |
cpu0/regs/ea/eamem_addr_o_cry_8         |       1|     770|     18.80%
                                        |        |        |
cpu0/regs/SU_cry[13]                    |       1|     672|     16.41%
                                        |        |        |
cpu0/dec_regs/un1_path_left_addr75_1_0  |       1|     636|     15.53%
                                        |        |        |
cpu0/alu/k_cpu_addr_1_sqmuxa_1          |       1|     619|     15.11%
                                        |        |        |
cpu0/un1_cpu_reset_9                    |       4|     619|     15.11%
                                        |        |        |
cpu0/regs/ea/eamem_addr_o_cry_6         |       1|     616|     15.04%
                                        |        |        |
cpu0/un1_state_116                      |      16|     615|     15.01%
                                        |        |        |
cpu0/regs/SS_cry[13]                    |       1|     612|     14.94%
                                        |        |        |
cpu0/dec_regs/un1_path_left_addr85_1_1_1|       1|     588|     14.36%
                                        |        |        |
cpu0/regs/left_1[2]                     |       9|     585|     14.28%
                                        |        |        |
cpu0/datamux_o_dest[2]                  |       2|     585|     14.28%
                                        |        |        |
cpu0/dec_regs/path_left_addr79          |       1|     583|     14.23%
                                        |        |        |
cpu0/regs/ea/N_62                       |      18|     576|     14.06%
                                        |        |        |
cpu0/regs/N_283                         |       1|     545|     13.31%
                                        |        |        |
cpu0/regs/SU_201_i1_mux                 |       1|     545|     13.31%
                                        |        |        |
cpu0/regs/SU_16[2]                      |       1|     545|     13.31%
                                        |        |        |
cpu0/k_opcode[1]                        |      61|     537|     13.11%
                                        |        |        |
cpu0/datamux_o_dest[9]                  |       2|     525|     12.82%
                                        |        |        |
cpu0/regs/left_1[9]                     |       6|     525|     12.82%
                                        |        |        |
cpu0/regs/left_1[3]                     |       9|     502|     12.26%
                                        |        |        |
cpu0/datamux_o_dest[3]                  |       2|     502|     12.26%
                                        |        |        |
cpu0/un1_k_opcode_3_4                   |       2|     499|     12.18%
                                        |        |        |
cpu0/un1_k_cpu_addr_1_cry_8             |       1|     472|     11.52%
                                        |        |        |
cpu0/k_opcode[5]                        |      52|     469|     11.45%
                                        |        |        |
cpu0/regs/SS_cry[5]                     |       1|     463|     11.30%
                                        |        |        |
cpu0/un1_k_cpu_addr_1_cry_10            |       1|     459|     11.21%
                                        |        |        |
cpu0/regs/ea/eamem_addr_o_cry_10        |       1|     450|     10.99%
                                        |        |        |
cpu0/regs/N_290                         |       1|     445|     10.86%
                                        |        |        |
cpu0/regs/SU_208_i1_mux                 |       1|     445|     10.86%
                                        |        |        |
cpu0/regs/SU_16[9]                      |       1|     445|     10.86%
                                        |        |        |
cpu0/un1_k_cpu_addr_1_cry_6             |       1|     444|     10.84%
                                        |        |        |
cpu0/regs/SS_cry[9]                     |       1|     437|     10.67%
                                        |        |        |
cpu0/regs/SS_cry[7]                     |       1|     424|     10.35%
                                        |        |        |
cpu0/alu/mulu/N_1325                    |       1|     419|     10.23%
                                        |        |        |
----------------------------------------------------------------------------


Clock Domains Analysis
------------------------

Found 1 clocks:

Clock Domain: clk40_i_c   Source: clk40_i.PAD   Loads: 318
   Covered under: FREQUENCY NET "clk40_i_c" 111.645000 MHz ;


Timing summary (Setup):
---------------

Timing errors: 4096  Score: 88089612
Cumulative negative slack: 88089612

Constraints cover 1430483 paths, 1 nets, and 9633 connections (99.1% coverage)

--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.1.0.96
Sun Jul 06 07:47:16 2014

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2014 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr -gui P6809_P6809.ncd P6809_P6809.prf 
Design file:     p6809_p6809.ncd
Preference file: p6809_p6809.prf
Device,speed:    LCMXO2-7000HE,m
Report level:    verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------

BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------



================================================================================
Preference: FREQUENCY NET "clk40_i_c" 111.645000 MHz ;
            4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed: The following path meets requirements by 0.199ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              textctrl/chars_data[1]  (from clk40_i_c +)
   Destination:    DP8KC      Port           textctrl/font/fontrom_0_0_3(ASIC)  (to clk40_i_c +)

   Delay:               0.304ns  (43.1% logic, 56.9% route), 1 logic levels.

 Constraint Details:

      0.304ns physical path delay SLICE_412 to textctrl/font/fontrom_0_0_3 meets
      0.052ns ADDR_HLD and
      0.000ns delay constraint less
     -0.053ns skew requirement (totaling 0.105ns) by 0.199ns

 Physical Path Details:

      Data path SLICE_412 to textctrl/font/fontrom_0_0_3:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131    R18C28D.CLK to     R18C28D.Q1 SLICE_412 (from clk40_i_c)
ROUTE         4     0.173     R18C28D.Q1 to *R_R20C27.ADA6 textctrl/chars_data[1] (to clk40_i_c)
                  --------
                    0.304   (43.1% logic, 56.9% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to SLICE_412:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     0.846       27.PADDI to    R18C28D.CLK clk40_i_c
                  --------
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to textctrl/font/fontrom_0_0_3:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     0.899       27.PADDI to *R_R20C27.CLKA clk40_i_c
                  --------
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.216ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              textctrl/line_cnt[3]  (from clk40_i_c +)
   Destination:    DP8KC      Port           textctrl/font/fontrom_0_3_0(ASIC)  (to clk40_i_c +)

   Delay:               0.339ns  (38.6% logic, 61.4% route), 1 logic levels.

 Constraint Details:

      0.339ns physical path delay textctrl/SLICE_421 to textctrl/font/fontrom_0_3_0 meets
      0.052ns ADDR_HLD and
      0.000ns delay constraint less
     -0.071ns skew requirement (totaling 0.123ns) by 0.216ns

 Physical Path Details:

      Data path textctrl/SLICE_421 to textctrl/font/fontrom_0_3_0:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131    R22C26B.CLK to     R22C26B.Q1 textctrl/SLICE_421 (from clk40_i_c)
ROUTE         7     0.208     R22C26B.Q1 to *R_R20C24.ADA4 textctrl/line_cnt[3] (to clk40_i_c)
                  --------
                    0.339   (38.6% logic, 61.4% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to textctrl/SLICE_421:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     0.828       27.PADDI to    R22C26B.CLK clk40_i_c
                  --------
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to textctrl/font/fontrom_0_3_0:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     0.899       27.PADDI to *R_R20C24.CLKA clk40_i_c
                  --------
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.277ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              textctrl/chars_data[0]  (from clk40_i_c +)
   Destination:    DP8KC      Port           textctrl/font/fontrom_0_0_3(ASIC)  (to clk40_i_c +)

   Delay:               0.382ns  (34.3% logic, 65.7% route), 1 logic levels.

 Constraint Details:

      0.382ns physical path delay SLICE_412 to textctrl/font/fontrom_0_0_3 meets
      0.052ns ADDR_HLD and
      0.000ns delay constraint less
     -0.053ns skew requirement (totaling 0.105ns) by 0.277ns

 Physical Path Details:

      Data path SLICE_412 to textctrl/font/fontrom_0_0_3:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131    R18C28D.CLK to     R18C28D.Q0 SLICE_412 (from clk40_i_c)
ROUTE         4     0.251     R18C28D.Q0 to *R_R20C27.ADA5 textctrl/chars_data[0] (to clk40_i_c)
                  --------
                    0.382   (34.3% logic, 65.7% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to SLICE_412:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     0.846       27.PADDI to    R18C28D.CLK clk40_i_c
                  --------
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to textctrl/font/fontrom_0_0_3:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     0.899       27.PADDI to *R_R20C27.CLKA clk40_i_c
                  --------
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.294ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              cpu0/k_cpu_addr[0]  (from clk40_i_c +)
   Destination:    DP8KC      Port           textctrl/chars/textmem4k_0_2_1(ASIC)  (to clk40_i_c +)

   Delay:               0.418ns  (31.3% logic, 68.7% route), 1 logic levels.

 Constraint Details:

      0.418ns physical path delay cpu0/SLICE_183 to textctrl/chars/textmem4k_0_2_1 meets
      0.071ns ADDR_HLD and
      0.000ns delay constraint less
     -0.053ns skew requirement (totaling 0.124ns) by 0.294ns

 Physical Path Details:

      Data path cpu0/SLICE_183 to textctrl/chars/textmem4k_0_2_1:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131    R16C14C.CLK to     R16C14C.Q0 cpu0/SLICE_183 (from clk40_i_c)
ROUTE        11     0.287     R16C14C.Q0 to *R_R13C13.ADB1 addr_o_c[0] (to clk40_i_c)
                  --------
                    0.418   (31.3% logic, 68.7% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to cpu0/SLICE_183:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     0.846       27.PADDI to    R16C14C.CLK clk40_i_c
                  --------
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to textctrl/chars/textmem4k_0_2_1:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     0.899       27.PADDI to *R_R13C13.CLKB clk40_i_c
                  --------
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.302ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              textctrl/chars_data[7]  (from clk40_i_c +)
   Destination:    DP8KC      Port           textctrl/font/fontrom_0_0_3(ASIC)  (to clk40_i_c +)

   Delay:               0.407ns  (32.2% logic, 67.8% route), 1 logic levels.

 Constraint Details:

      0.407ns physical path delay SLICE_415 to textctrl/font/fontrom_0_0_3 meets
      0.052ns ADDR_HLD and
      0.000ns delay constraint less
     -0.053ns skew requirement (totaling 0.105ns) by 0.302ns

 Physical Path Details:

      Data path SLICE_415 to textctrl/font/fontrom_0_0_3:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131    R16C28A.CLK to     R16C28A.Q1 SLICE_415 (from clk40_i_c)
ROUTE         4     0.276     R16C28A.Q1 to *_R20C27.ADA12 textctrl/chars_data[7] (to clk40_i_c)
                  --------
                    0.407   (32.2% logic, 67.8% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to SLICE_415:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     0.846       27.PADDI to    R16C28A.CLK clk40_i_c
                  --------
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to textctrl/font/fontrom_0_0_3:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     0.899       27.PADDI to *R_R20C27.CLKA clk40_i_c
                  --------
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.314ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              cpu0/k_cpu_addr[6]  (from clk40_i_c +)
   Destination:    DP8KC      Port           bios/bios2k_0_1_0(ASIC)  (to clk40_i_c +)

   Delay:               0.419ns  (31.3% logic, 68.7% route), 1 logic levels.

 Constraint Details:

      0.419ns physical path delay cpu0/SLICE_186 to bios/bios2k_0_1_0 meets
      0.052ns ADDR_HLD and
      0.000ns delay constraint less
     -0.053ns skew requirement (totaling 0.105ns) by 0.314ns

 Physical Path Details:

      Data path cpu0/SLICE_186 to bios/bios2k_0_1_0:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131    R15C12A.CLK to     R15C12A.Q0 cpu0/SLICE_186 (from clk40_i_c)
ROUTE         8     0.288     R15C12A.Q0 to *R_R13C10.ADA8 addr_o_c[6] (to clk40_i_c)
                  --------
                    0.419   (31.3% logic, 68.7% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to cpu0/SLICE_186:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     0.846       27.PADDI to    R15C12A.CLK clk40_i_c
                  --------
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to bios/bios2k_0_1_0:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     0.899       27.PADDI to *R_R13C10.CLKA clk40_i_c
                  --------
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.322ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              cpu0/k_cpu_addr[5]  (from clk40_i_c +)
   Destination:    DP8KC      Port           textctrl/chars/textmem4k_0_2_1(ASIC)  (to clk40_i_c +)

   Delay:               0.446ns  (29.4% logic, 70.6% route), 1 logic levels.

 Constraint Details:

      0.446ns physical path delay cpu0/SLICE_185 to textctrl/chars/textmem4k_0_2_1 meets
      0.071ns ADDR_HLD and
      0.000ns delay constraint less
     -0.053ns skew requirement (totaling 0.124ns) by 0.322ns

 Physical Path Details:

      Data path cpu0/SLICE_185 to textctrl/chars/textmem4k_0_2_1:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131    R16C13D.CLK to     R16C13D.Q1 cpu0/SLICE_185 (from clk40_i_c)
ROUTE         9     0.315     R16C13D.Q1 to *R_R13C13.ADB6 addr_o_c[5] (to clk40_i_c)
                  --------
                    0.446   (29.4% logic, 70.6% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to cpu0/SLICE_185:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     0.846       27.PADDI to    R16C13D.CLK clk40_i_c
                  --------
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to textctrl/chars/textmem4k_0_2_1:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     0.899       27.PADDI to *R_R13C13.CLKB clk40_i_c
                  --------
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.326ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              textctrl/line_cnt[1]  (from clk40_i_c +)
   Destination:    DP8KC      Port           textctrl/font/fontrom_0_0_3(ASIC)  (to clk40_i_c +)

   Delay:               0.449ns  (29.2% logic, 70.8% route), 1 logic levels.

 Constraint Details:

      0.449ns physical path delay textctrl/SLICE_420 to textctrl/font/fontrom_0_0_3 meets
      0.052ns ADDR_HLD and
      0.000ns delay constraint less
     -0.071ns skew requirement (totaling 0.123ns) by 0.326ns

 Physical Path Details:

      Data path textctrl/SLICE_420 to textctrl/font/fontrom_0_0_3:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131    R22C27D.CLK to     R22C27D.Q1 textctrl/SLICE_420 (from clk40_i_c)
ROUTE         9     0.318     R22C27D.Q1 to *R_R20C27.ADA2 textctrl/line_cnt[1] (to clk40_i_c)
                  --------
                    0.449   (29.2% logic, 70.8% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to textctrl/SLICE_420:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     0.828       27.PADDI to    R22C27D.CLK clk40_i_c
                  --------
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to textctrl/font/fontrom_0_0_3:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     0.899       27.PADDI to *R_R20C27.CLKA clk40_i_c
                  --------
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.326ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              cpu0/k_cpu_addr[9]  (from clk40_i_c +)
   Destination:    DP8KC      Port           textctrl/chars/textmem4k_0_2_1(ASIC)  (to clk40_i_c +)

   Delay:               0.450ns  (29.1% logic, 70.9% route), 1 logic levels.

 Constraint Details:

      0.450ns physical path delay cpu0/SLICE_187 to textctrl/chars/textmem4k_0_2_1 meets
      0.071ns ADDR_HLD and
      0.000ns delay constraint less
     -0.053ns skew requirement (totaling 0.124ns) by 0.326ns

 Physical Path Details:

      Data path cpu0/SLICE_187 to textctrl/chars/textmem4k_0_2_1:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131    R15C12B.CLK to     R15C12B.Q1 cpu0/SLICE_187 (from clk40_i_c)
ROUTE         8     0.319     R15C12B.Q1 to *_R13C13.ADB10 addr_o_c[9] (to clk40_i_c)
                  --------
                    0.450   (29.1% logic, 70.9% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to cpu0/SLICE_187:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     0.846       27.PADDI to    R15C12B.CLK clk40_i_c
                  --------
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to textctrl/chars/textmem4k_0_2_1:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     0.899       27.PADDI to *R_R13C13.CLKB clk40_i_c
                  --------
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.328ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              textctrl/line_cnt[1]  (from clk40_i_c +)
   Destination:    DP8KC      Port           textctrl/font/fontrom_0_3_0(ASIC)  (to clk40_i_c +)

   Delay:               0.451ns  (29.0% logic, 71.0% route), 1 logic levels.

 Constraint Details:

      0.451ns physical path delay textctrl/SLICE_420 to textctrl/font/fontrom_0_3_0 meets
      0.052ns ADDR_HLD and
      0.000ns delay constraint less
     -0.071ns skew requirement (totaling 0.123ns) by 0.328ns

 Physical Path Details:

      Data path textctrl/SLICE_420 to textctrl/font/fontrom_0_3_0:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131    R22C27D.CLK to     R22C27D.Q1 textctrl/SLICE_420 (from clk40_i_c)
ROUTE         9     0.320     R22C27D.Q1 to *R_R20C24.ADA2 textctrl/line_cnt[1] (to clk40_i_c)
                  --------
                    0.451   (29.0% logic, 71.0% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to textctrl/SLICE_420:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     0.828       27.PADDI to    R22C27D.CLK clk40_i_c
                  --------
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to textctrl/font/fontrom_0_3_0:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       318     0.899       27.PADDI to *R_R20C24.CLKA clk40_i_c
                  --------
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.

Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays)                  |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
FREQUENCY NET "clk40_i_c" 111.645000    |             |             |
MHz ;                                   |     0.000 ns|     0.199 ns|   1  
                                        |             |             |
----------------------------------------------------------------------------


All preferences were met.


Clock Domains Analysis
------------------------

Found 1 clocks:

Clock Domain: clk40_i_c   Source: clk40_i.PAD   Loads: 318
   Covered under: FREQUENCY NET "clk40_i_c" 111.645000 MHz ;


Timing summary (Hold):
---------------

Timing errors: 0  Score: 0
Cumulative negative slack: 0

Constraints cover 1430483 paths, 1 nets, and 9633 connections (99.1% coverage)



Timing summary (Setup and Hold):
---------------

Timing errors: 4096 (setup), 0 (hold)
Score: 88089612 (setup), 0 (hold)
Cumulative negative slack: 88089612 (88089612+0)
--------------------------------------------------------------------------------

--------------------------------------------------------------------------------
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[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [P6809_P6809.twr] - Rev 12
