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<HEAD><TITLE>Synthesis Report</TITLE>
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<PRE><A name="Syn"></A><B><U><big>Synthesis Report</big></U></B>
#Build: Synplify Pro G-2012.09L-SP1 , Build 029R, Mar 11 2013
#install: /usr/local/diamond/2.2_x64/synpbase
#OS: Linux
#Hostname: node01.pacito.sys
#Implementation: P6809
$ Start of Compile
#Wed Dec 25 17:50:10 2013
Synopsys Verilog Compiler, version comp201209rcp1, Build 271R, built Mar 11 2013
@N|Running in 64-bit mode
Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/machxo2.v"
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/pmi_def.v"
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/umr_capim.v"
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_objects.v"
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_pipes.svh"
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/hypermods.v"
@I::"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v"
@I::"/home/pacito/02_Elektronik/020_V6809/6809/alu16.v"
@I:"/home/pacito/02_Elektronik/020_V6809/6809/alu16.v":"/home/pacito/02_Elektronik/020_V6809/6809/defs.v"
@I::"/home/pacito/02_Elektronik/020_V6809/6809/decoders.v"
@I::"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v"
@I::"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v"
@I::"/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v"
@I::"/home/pacito/02_Elektronik/020_V6809/6809/lattice/bios2k.v"
Verilog syntax check successful!
File /home/pacito/02_Elektronik/020_V6809/6809/decoders.v changed - recompiling
File /home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v changed - recompiling
File /home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v changed - recompiling
Selecting top level module CC3_top
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/alu16.v":13:7:13:11|Synthesizing module alu16
@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/alu16.v":493:0:493:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":7:7:7:14|Synthesizing module regblock
@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":225:0:225:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":50:10:50:13|No assignment to regh[7]
@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":50:21:50:24|No assignment to regl[6]
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/decoders.v":9:7:9:17|Synthesizing module decode_regs
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/decoders.v":108:7:108:15|Synthesizing module decode_op
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/decoders.v":236:7:236:15|Synthesizing module decode_ea
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/decoders.v":262:7:262:16|Synthesizing module decode_alu
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/decoders.v":334:7:334:20|Synthesizing module test_condition
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":25:7:25:16|Synthesizing module MC6809_cpu
@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":405:6:405:13|Ignoring system task $display
@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":961:0:961:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_pull_reg_write -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_pp_active_reg[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_postbyte0[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_new_pc[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Register bit k_mem_dest[0] is always 1, optimizing ...
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Register bit k_mem_dest[1] is always 0, optimizing ...
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Register bit next_mem_state[1] is always 0, optimizing ...
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Register bit next_mem_state[2] is always 0, optimizing ...
@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Pruning register bits 2 to 1 of next_mem_state[5:0]
@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1120:7:1120:9|Synthesizing module VHI
@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1291:7:1291:11|Synthesizing module DP8KC
@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1124:7:1124:9|Synthesizing module VLO
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/lattice/bios2k.v":8:7:8:12|Synthesizing module bios2k
@W: CL168 :"/home/pacito/02_Elektronik/020_V6809/6809/lattice/bios2k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v":7:7:7:13|Synthesizing module CC3_top
@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v":28:14:28:21|No assignment to clk_div2
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v":33:25:33:35|No assignment to wire cpu1_addr_o
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v":34:40:34:51|No assignment to wire cpu1_data_in
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v":34:54:34:66|No assignment to wire cpu1_data_out
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v":35:23:35:29|No assignment to wire cpu1_we
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v":35:32:35:38|No assignment to wire cpu1_oe
@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v":34:54:34:66|*Input cpu1_data_out[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v":33:25:33:35|*Input cpu1_addr_o[10:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Pruning register bits 5 to 2 of next_push_state[5:0]
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/decoders.v":338:18:338:20|Input port bits 7 to 4 of CCR[7:0] are unused
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/decoders.v":264:18:264:26|Input port bits 5 to 4 of postbyte0[7:0] are unused
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/decoders.v":237:18:237:27|Input port bits 6 to 5 of eapostbyte[7:0] are unused
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Dec 25 17:50:12 2013
###########################################################]
Premap Report
Synopsys Lattice Technology Pre-mapping, Version maplat, Build 618R, Built Mar 14 2013 09:13:46
Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
Product Version G-2012.09L-SP1
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
@L: /home/pacito/02_Elektronik/020_V6809/6809/lattice/P6809/P6809_P6809_scck.rpt
Printing clock summary report in "/home/pacito/02_Elektronik/020_V6809/6809/lattice/P6809/P6809_P6809_scck.rpt" file
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 94MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 94MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 109MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 111MB)
Clock Summary
**************
Start Requested Requested Clock Clock
Clock Frequency Period Type Group
--------------------------------------------------------------------------------------------------------------------
CC3_top|clk40_i 1.0 MHz 1000.000 inferred Inferred_clkgroup_0
CC3_top|cpu_clk_derived_clock 1.0 MHz 1000.000 derived (from CC3_top|clk40_i) Inferred_clkgroup_0
====================================================================================================================
@W: MT529 :"/home/pacito/02_Elektronik/020_V6809/6809/lattice/bios2k.v":74:10:74:21|Found inferred clock CC3_top|clk40_i which controls 1 sequential elements including bios.bios2k_0_0_1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
syn_allowed_resources : blockrams=26 set on top level netlist CC3_top
Finished Pre Mapping Phase.Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 136MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Dec 25 17:50:13 2013
###########################################################]
Map & Optimize Report
Synopsys Lattice Technology Mapper, Version maplat, Build 618R, Built Mar 14 2013 09:13:46
Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
Product Version G-2012.09L-SP1
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 106MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 108MB)
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)
Available hyper_sources - for debug and ip models
None Found
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)
@N:"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Found counter in view:work.MC6809_cpu(verilog) inst k_cpu_addr[15:0]
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_clear_e in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_set_e in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":172:0:172:5|Removing sequential instance regs.fflag in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":172:0:172:5|Removing sequential instance regs.intff in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":172:0:172:5|Removing sequential instance regs.eflag in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 154MB peak: 156MB)
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Removing sequential instance cpu0.k_reg_firq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Removing sequential instance cpu0.k_reg_nmi[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 150MB peak: 157MB)
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 167MB)
@N: FA113 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":205:24:205:32|Pipelining module un63_regl[15:0]
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Register k_inc_pc pushed in.
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Register k_write_pc pushed in.
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Register k_new_pc[15:0] pushed in.
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/alu16.v":376:0:376:5|Register regq8[7:0] pushed in.
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/alu16.v":376:0:376:5|Register regq16[15:0] pushed in.
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/alu16.v":376:0:376:5|Register reg_z_in pushed in.
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/alu16.v":376:0:376:5|Register reg_n_in pushed in.
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":172:0:172:5|Register vff pushed in.
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":172:0:172:5|Register zff pushed in.
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":172:0:172:5|Register nff pushed in.
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":172:0:172:5|Register hflag pushed in.
@N: FA113 :"/home/pacito/02_Elektronik/020_V6809/6809/alu16.v":180:19:180:32|Pipelining module daa_lnm9
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/alu16.v":376:0:376:5|Register regq16[15:0] pushed in.
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/alu16.v":376:0:376:5|Register regq8[7:0] pushed in.
@N: MF169 :|Register NoName pushed in.
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":172:0:172:5|Register cff pushed in.
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":289:2:289:3|Found addmux in view:work.CC3_top(verilog) inst cpu0.dec_regs.k_new_pc_17_2_i_m2[15:0] from cpu0.un1_regs_o_pc[15:0]
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":205:24:205:32|Found addmux in view:work.CC3_top(verilog) inst cpu0.regs.regl\[5\]_8[15:0] from cpu0.regs.un63_regl[15:0]
Starting Early Timing Optimization (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 154MB peak: 167MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 154MB peak: 167MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 153MB peak: 167MB)
Finished preparing to map (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 152MB peak: 167MB)
Finished technology mapping (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 206MB peak: 229MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
------------------------------------------------------------
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 167MB peak: 229MB)
@N: FX164 |The option to pack flops in the IOB has not been specified
Finished restoring hierarchy (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 168MB peak: 229MB)
#### START OF CLOCK OPTIMIZATION REPORT #####[
1 non-gated/non-generated clock tree(s) driving 473 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
274 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks
=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------
@K:CKID0001 clk40_i port 473 cpu_clk
=======================================================================================
===== Gated/Generated Clocks =====
************** None **************
----------------------------------
==================================
##### END OF CLOCK OPTIMIZATION REPORT ######]
Writing Analyst data base /home/pacito/02_Elektronik/020_V6809/6809/lattice/P6809/P6809_P6809.srm
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 170MB peak: 229MB)
Writing EDIF Netlist and constraint files
G-2012.09L-SP1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 174MB peak: 229MB)
@W: MT420 |Found inferred clock CC3_top|clk40_i with period 1000.00ns. Please declare a user-defined clock on object "p:clk40_i"
##### START OF TIMING REPORT #####[
# Timing Report written on Wed Dec 25 17:50:28 2013
#
Top view: CC3_top
Requested Frequency: 1.0 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
Performance Summary
*******************
Worst slack in design: 975.177
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
------------------------------------------------------------------------------------------------------------------------
CC3_top|clk40_i 1.0 MHz 40.3 MHz 1000.000 24.823 975.177 inferred Inferred_clkgroup_0
========================================================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
--------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
--------------------------------------------------------------------------------------------------------------------------
CC3_top|clk40_i CC3_top|clk40_i | 1000.000 975.177 | No paths - | No paths - | No paths -
==========================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: CC3_top|clk40_i
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------
cpu0.k_opcode[1] CC3_top|clk40_i FD1P3AX Q k_opcode[1] 1.350 975.177
cpu0.k_opcode[7] CC3_top|clk40_i FD1P3AX Q k_opcode[7] 1.344 975.183
cpu0.k_opcode[4] CC3_top|clk40_i FD1P3AX Q k_opcode[4] 1.309 975.218
cpu0.k_opcode[5] CC3_top|clk40_i FD1P3AX Q k_opcode[5] 1.288 975.239
cpu0.k_pp_active_reg[0] CC3_top|clk40_i FD1P3AX Q k_pp_active_reg[0] 1.204 975.340
cpu0.k_pp_active_reg[1] CC3_top|clk40_i FD1P3AX Q k_pp_active_reg[1] 1.188 975.356
cpu0.k_pp_active_reg[3] CC3_top|clk40_i FD1P3AX Q k_pp_active_reg[3] 1.188 975.356
cpu0.k_pp_active_reg[2] CC3_top|clk40_i FD1P3AX Q k_pp_active_reg[2] 1.180 975.364
cpu0.k_pp_active_reg[4] CC3_top|clk40_i FD1P3AX Q k_pp_active_reg[4] 1.180 975.364
cpu0.k_pp_active_reg[5] CC3_top|clk40_i FD1P3AX Q k_pp_active_reg[5] 1.180 975.364
==============================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------------
cpu0.alu.regq16_pipe CC3_top|clk40_i FD1P3AX D N_712 1000.089 975.177
cpu0.alu.regq16_pipe_11 CC3_top|clk40_i FD1P3AX D N_711 1000.089 975.319
cpu0.alu.regq16_pipe_22 CC3_top|clk40_i FD1P3AX D N_710 1000.089 975.319
cpu0.alu.regq16_pipe_33 CC3_top|clk40_i FD1P3AX D N_709 1000.089 975.462
cpu0.alu.regq16_pipe_44 CC3_top|clk40_i FD1P3AX D N_708 1000.089 975.462
cpu0.alu.regq16_pipe_55 CC3_top|clk40_i FD1P3AX D N_707 1000.089 975.605
cpu0.alu.regq16_pipe_66 CC3_top|clk40_i FD1P3AX D N_706 1000.089 975.605
cpu0.alu.cff_pipe_5 CC3_top|clk40_i FD1P3AX D N_1009 1000.089 975.676
cpu0.alu.regq16_pipe_88 CC3_top|clk40_i FD1P3AX D N_704 1000.089 975.676
cpu0.alu.regq16_pipe_77 CC3_top|clk40_i FD1P3AX D N_705 1000.089 975.748
===================================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 1000.000
- Setup time: -0.089
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 1000.089
- Propagation time: 24.912
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : 975.177
Number of logic level(s): 26
Starting point: cpu0.k_opcode[1] / Q
Ending point: cpu0.alu.regq16_pipe / D
The start point is clocked by CC3_top|clk40_i [rising] on pin CK
The end point is clocked by CC3_top|clk40_i [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------
cpu0.k_opcode[1] FD1P3AX Q Out 1.350 1.350 -
k_opcode[1] Net - - - - 48
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_a6_2_1 ORCALUT4 A In 0.000 1.350 -
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_a6_2_1 ORCALUT4 Z Out 1.017 2.367 -
un1_dest_reg_2_sqmuxa_1_1_a6_2_1 Net - - - - 1
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_a6_2 ORCALUT4 B In 0.000 2.367 -
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_a6_2 ORCALUT4 Z Out 1.017 3.384 -
N_372 Net - - - - 1
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_2 ORCALUT4 A In 0.000 3.384 -
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_2 ORCALUT4 Z Out 1.017 4.401 -
un1_dest_reg_2_sqmuxa_1_1_2 Net - - - - 1
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1 ORCALUT4 C In 0.000 4.401 -
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1 ORCALUT4 Z Out 1.193 5.593 -
un1_dest_reg_2_sqmuxa_1_0 Net - - - - 4
cpu0.dec_regs.path_left_addr[0] ORCALUT4 D In 0.000 5.593 -
cpu0.dec_regs.path_left_addr[0] ORCALUT4 Z Out 0.449 6.042 -
dec_o_left_path_addr[0] Net - - - - 3
cpu0.regs.datamux_o_alu_in_left_path_addr_1_0[0] ORCALUT4 C In 0.000 6.042 -
cpu0.regs.datamux_o_alu_in_left_path_addr_1_0[0] ORCALUT4 Z Out 1.225 7.267 -
N_959 Net - - - - 5
cpu0.regs.datamux_o_alu_in_left_path_addr_1_0_RNIB1K51[0] ORCALUT4 B In 0.000 7.267 -
cpu0.regs.datamux_o_alu_in_left_path_addr_1_0_RNIB1K51[0] ORCALUT4 Z Out 1.406 8.673 -
datamux_o_alu_in_left_path_addr_1[0] Net - - - - 55
cpu0.regs.path_left_data_7_am_1[0] ORCALUT4 A In 0.000 8.673 -
cpu0.regs.path_left_data_7_am_1[0] ORCALUT4 Z Out 1.017 9.690 -
path_left_data_7_am_1[0] Net - - - - 1
cpu0.regs.path_left_data_7_am[0] ORCALUT4 B In 0.000 9.690 -
cpu0.regs.path_left_data_7_am[0] ORCALUT4 Z Out 1.017 10.707 -
path_left_data_7_am[0] Net - - - - 1
cpu0.regs.path_left_data_7[0] PFUMX BLUT In 0.000 10.707 -
cpu0.regs.path_left_data_7[0] PFUMX Z Out -0.033 10.674 -
N_401 Net - - - - 1
cpu0.regs.path_left_data[0] L6MUX21 D0 In 0.000 10.674 -
cpu0.regs.path_left_data[0] L6MUX21 Z Out 0.868 11.542 -
regs_o_left_path_data[0] Net - - - - 3
cpu0.alu.datamux_o_alu_in_left_path_data[0] ORCALUT4 C In 0.000 11.542 -
cpu0.alu.datamux_o_alu_in_left_path_data[0] ORCALUT4 Z Out 1.384 12.926 -
datamux_o_alu_in_left_path_data[0] Net - - - - 41
cpu0.alu.mul16_w_madd_0_cry_0_0 CCU2D C1 In 0.000 12.926 -
cpu0.alu.mul16_w_madd_0_cry_0_0 CCU2D COUT Out 1.544 14.470 -
mul16_w_madd_0_cry_0 Net - - - - 1
cpu0.alu.mul16_w_madd_0_cry_1_0 CCU2D CIN In 0.000 14.470 -
cpu0.alu.mul16_w_madd_0_cry_1_0 CCU2D S0 Out 1.621 16.091 -
mul16_w_madd_4 Net - - - - 2
cpu0.alu.mul16_w_madd_4_cry_0_0 CCU2D A1 In 0.000 16.091 -
cpu0.alu.mul16_w_madd_4_cry_0_0 CCU2D COUT Out 1.544 17.636 -
mul16_w_madd_4_cry_0 Net - - - - 1
cpu0.alu.mul16_w_madd_4_cry_1_0 CCU2D CIN In 0.000 17.636 -
cpu0.alu.mul16_w_madd_4_cry_1_0 CCU2D S1 Out 1.621 19.257 -
mul16_w_madd Net - - - - 2
cpu0.alu.mul16_w_madd_cry_0_0 CCU2D A1 In 0.000 19.257 -
cpu0.alu.mul16_w_madd_cry_0_0 CCU2D COUT Out 1.544 20.801 -
mul16_w_madd_cry_0 Net - - - - 1
cpu0.alu.mul16_w_madd_cry_1_0 CCU2D CIN In 0.000 20.801 -
cpu0.alu.mul16_w_madd_cry_1_0 CCU2D COUT Out 0.143 20.944 -
mul16_w_madd_cry_2 Net - - - - 1
cpu0.alu.mul16_w_madd_cry_3_0 CCU2D CIN In 0.000 20.944 -
cpu0.alu.mul16_w_madd_cry_3_0 CCU2D COUT Out 0.143 21.087 -
mul16_w_madd_cry_4 Net - - - - 1
cpu0.alu.mul16_w_madd_cry_5_0 CCU2D CIN In 0.000 21.087 -
cpu0.alu.mul16_w_madd_cry_5_0 CCU2D COUT Out 0.143 21.230 -
mul16_w_madd_cry_6 Net - - - - 1
cpu0.alu.mul16_w_madd_cry_7_0 CCU2D CIN In 0.000 21.230 -
cpu0.alu.mul16_w_madd_cry_7_0 CCU2D COUT Out 0.143 21.372 -
mul16_w_madd_cry_8 Net - - - - 1
cpu0.alu.mul16_w_madd_cry_9_0 CCU2D CIN In 0.000 21.372 -
cpu0.alu.mul16_w_madd_cry_9_0 CCU2D COUT Out 0.143 21.515 -
mul16_w_madd_cry_10 Net - - - - 1
cpu0.alu.mul16_w_madd_s_11_0 CCU2D CIN In 0.000 21.515 -
cpu0.alu.mul16_w_madd_s_11_0 CCU2D S0 Out 1.549 23.064 -
mul16_w[15] Net - - - - 1
cpu0.alu.q16_11_bm[15] ORCALUT4 A In 0.000 23.064 -
cpu0.alu.q16_11_bm[15] ORCALUT4 Z Out 1.017 24.081 -
q16_11_bm[15] Net - - - - 1
cpu0.alu.q16_11[15] PFUMX ALUT In 0.000 24.081 -
cpu0.alu.q16_11[15] PFUMX Z Out 0.214 24.295 -
N_696 Net - - - - 1
cpu0.alu.q16_12[15] ORCALUT4 B In 0.000 24.295 -
cpu0.alu.q16_12[15] ORCALUT4 Z Out 0.617 24.912 -
N_712 Net - - - - 1
cpu0.alu.regq16_pipe FD1P3AX D In 0.000 24.912 -
=============================================================================================================================
##### END OF TIMING REPORT #####]
---------------------------------------
Resource Usage Report
Part: lcmxo2_7000he-4
Register bits: 469 of 6864 (7%)
PIC Latch: 0
I/O cells: 49
Block Rams : 2 of 26 (7%)
Details:
CCU2D: 205
DP8KC: 2
FD1P3AX: 449
FD1P3DX: 6
FD1P3IX: 1
FD1P3JX: 4
FD1S3AX: 1
GSR: 1
IB: 1
INV: 5
L6MUX21: 21
OB: 48
OFS1P3DX: 8
ORCALUT4: 1904
PFUMX: 224
PUR: 1
VHI: 4
VLO: 10
true: 6
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 44MB peak: 229MB)
Process took 0h:00m:14s realtime, 0h:00m:14s cputime
# Wed Dec 25 17:50:28 2013
###########################################################]
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