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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_multiply.v] - Rev 2
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////////////////////////////////////////////////////////////////////// //// //// //// multiply for 8051 Core //// //// //// //// This file is part of the 8051 cores project //// //// http://www.opencores.org/cores/8051/ //// //// //// //// Description //// //// Implementation of multipication used in alu.v //// //// //// //// To Do: //// //// Nothing //// //// //// //// Author(s): //// //// - Simon Teran, simont@opencores.org //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2001 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // ver: 1 // // synopsys translate_off `include "oc8051_timescale.v" // synopsys translate_on module oc8051_multiply (src1, src2, des1, des2, desOv); // // this module is part of alu // src1 (in) first operand // src2 (in) second operand // des1 (out) first result // des2 (out) second result // desOv (out) Overflow output // input [7:0] src1, src2; output desOv; output [7:0] des1, des2; reg desOv; reg [7:0] des1, des2; always @(src1 or src2) begin {des2, des1} = src1* src2; if (des2!=8'b00000000) desOv = 1'b1; else desOv = 1'b0; end endmodule
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