Subversion Repositories aes_pipe

Release 11.1 par L.33 (lin)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.

blackpearl-laptop::  Thu Mar 25 14:30:35 2010

par -w -ol high ../out/aes.ncd ../out/aes.map.ncd 


Constraints file: ../out/aes.pcf.
Loading device for application Rf_Device from file '5vlx50t.nph' in environment /opt/Xilinx/11.1/ISE.
   "aes_top" is an NCD, version 3.2, device xc5vlx50t, package ff1136, speed -1

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)


Device speed data version:  "PRODUCTION 1.64 2009-03-03".



Device Utilization Summary:

   Number of BUFGs                           2 out of 32      6%
   Number of External IOBs                 386 out of 480    80%
      Number of LOCed IOBs                   0 out of 386     0%

   Number of Slice Registers              7873 out of 28800  27%
      Number used as Flip Flops           7873
      Number used as Latches                 0
      Number used as LatchThrus              0

   Number of Slice LUTS                  14724 out of 28800  51%
   Number of Slice LUT-Flip Flop pairs   15770 out of 28800  54%


Overall effort level (-ol):   High 
Router effort level (-rl):    High 

Starting initial Timing Analysis.  REAL time: 47 secs 
Finished initial Timing Analysis.  REAL time: 48 secs 

Starting Router


Phase  1  : 77449 unrouted;      REAL time: 52 secs 

Phase  2  : 67441 unrouted;      REAL time: 1 mins 5 secs 

Phase  3  : 11182 unrouted;      REAL time: 4 mins 3 secs 

Phase  4  : 11253 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 4 mins 26 secs 

Updating file: ../out/aes.map.ncd with current fully routed design.

Phase  5  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 5 mins 14 secs 

Phase  6  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 5 mins 14 secs 

Phase  7  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 5 mins 14 secs 

Phase  8  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 5 mins 14 secs 

Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 5 mins 14 secs 

Phase 10  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 5 mins 24 secs 
Total REAL time to Router completion: 5 mins 24 secs 
Total CPU time to Router completion: 5 mins 13 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|         clk_i_BUFGP | BUFGCTRL_X0Y1| No   | 3403 |  0.334     |  1.843      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
  TS_clk = PERIOD TIMEGRP "clk_i" 3 ns HIGH | SETUP       |     0.026ns|     2.974ns|       0|           0
   50%                                      | HOLD        |     0.296ns|            |       0|           0
------------------------------------------------------------------------------------------------------


All constraints were met.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 5 mins 42 secs 
Total CPU time to PAR completion: 5 mins 30 secs 

Peak Memory Usage:  425 MB

Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 0

Writing design to file ../out/aes.map.ncd



PAR done!