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[/] [aes_pipe/] [trunk/] [syn/] [Xilinx/] [log/] [aes.twr] - Rev 10
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--------------------------------------------------------------------------------Release 11.1 Trace (lin)Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved./opt/Xilinx/11.1/ISE/bin/lin/unwrapped/trce -v 10 -fastpaths -xml../log/aes.twx ../out/aes.map.ncd -o ../log/aes.twr ../out/aes.pcfDesign file: aes.map.ncdPhysical constraint file: aes.pcfDevice,package,speed: xc5vlx50t,ff1136,-1 (PRODUCTION 1.64 2009-03-03, STEPPING level 0)Report level: verbose report, limited to 10 items per constraintEnvironment Variable Effect-------------------- ------NONE No environment variables were set--------------------------------------------------------------------------------INFO:Timing:2752 - To get complete path coverage, use the unconstrained pathsoption. All paths that are not constrained will be reported in theunconstrained paths section(s) of the report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based ona 50 Ohm transmission line loading model. For the details of this model,and for more information on accounting for different loading conditions,please see the device datasheet.================================================================================Timing constraint: TS_clk = PERIOD TIMEGRP "clk_i" 3 ns HIGH 50%;59472 paths analyzed, 27896 endpoints analyzed, 0 failing endpoints0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)Minimum period is 2.974ns.--------------------------------------------------------------------------------Slack (setup path): 0.026ns (requirement - (data path - clock path skew + uncertainty))Source: proc[0].mix/outrkey<2>_1_5 (FF)Destination: proc[1].add/dataout<2>_1_5 (FF)Requirement: 3.000nsData Path Delay: 2.793ns (Levels of Logic = 1)Clock Path Skew: -0.146ns (1.244 - 1.390)Source Clock: clk_i_BUFGP rising at 0.000nsDestination Clock: clk_i_BUFGP rising at 3.000nsClock Uncertainty: 0.035nsClock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PETotal System Jitter (TSJ): 0.070nsTotal Input Jitter (TIJ): 0.000nsDiscrete Jitter (DJ): 0.000nsPhase Error (PE): 0.000nsMaximum Data Path: proc[0].mix/outrkey<2>_1_5 to proc[1].add/dataout<2>_1_5Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X20Y103.BQ Tcko 0.471 proc[0].mix/outrkey<2>_1_7proc[0].mix/outrkey<2>_1_5SLICE_X47Y110.B6 net (fanout=4) 2.295 proc[0].mix/outrkey<2>_1_5SLICE_X47Y110.CLK Tas 0.027 proc[1].add/dataout<2>_1_7proc[1].add/Mxor_added<2><1>_Result<5>1proc[1].add/dataout<2>_1_5------------------------------------------------- ---------------------------Total 2.793ns (0.498ns logic, 2.295ns route)(17.8% logic, 82.2% route)--------------------------------------------------------------------------------Slack (setup path): 0.026ns (requirement - (data path - clock path skew + uncertainty))Source: add_f_1/dataout<1>_1_1 (FF)Destination: sbox_f_1/g0[1].g1[1].sub/byteout_5 (FF)Requirement: 3.000nsData Path Delay: 2.850ns (Levels of Logic = 2)Clock Path Skew: -0.089ns (1.226 - 1.315)Source Clock: clk_i_BUFGP rising at 0.000nsDestination Clock: clk_i_BUFGP rising at 3.000nsClock Uncertainty: 0.035nsClock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PETotal System Jitter (TSJ): 0.070nsTotal Input Jitter (TIJ): 0.000nsDiscrete Jitter (DJ): 0.000nsPhase Error (PE): 0.000nsMaximum Data Path: add_f_1/dataout<1>_1_1 to sbox_f_1/g0[1].g1[1].sub/byteout_5Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X52Y59.BQ Tcko 0.471 add_f_1/dataout<1>_1_3add_f_1/dataout<1>_1_1SLICE_X59Y62.C1 net (fanout=32) 1.538 add_f_1/dataout<1>_1_1SLICE_X59Y62.C Tilo 0.094 sbox_f_1/g0[2].g1[0].sub_Mrom_byteout_rom000022sbox_f_1/g0[1].g1[1].sub_Mrom_byteout_rom0000101SLICE_X56Y61.B5 net (fanout=1) 0.546 sbox_f_1/g0[1].g1[1].sub_Mrom_byteout_rom0000101SLICE_X56Y61.CLK Tas 0.201 sbox_f_1/g0[1].g1[1].sub/byteout<5>sbox_f_1/g0[1].g1[1].sub_Mrom_byteout_rom000010_f7sbox_f_1/g0[1].g1[1].sub_Mrom_byteout_rom000010_f7_rtsbox_f_1/g0[1].g1[1].sub_Mrom_byteout_rom000010_f8sbox_f_1/g0[1].g1[1].sub/byteout_5------------------------------------------------- ---------------------------Total 2.850ns (0.766ns logic, 2.084ns route)(26.9% logic, 73.1% route)--------------------------------------------------------------------------------Slack (setup path): 0.027ns (requirement - (data path - clock path skew + uncertainty))Source: proc[3].add/dataout<3>_1_4 (FF)Destination: proc[3].sbox/g0[3].g1[1].sub/byteout_4 (FF)Requirement: 3.000nsData Path Delay: 2.814ns (Levels of Logic = 2)Clock Path Skew: -0.124ns (1.168 - 1.292)Source Clock: clk_i_BUFGP rising at 0.000nsDestination Clock: clk_i_BUFGP rising at 3.000nsClock Uncertainty: 0.035nsClock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PETotal System Jitter (TSJ): 0.070nsTotal Input Jitter (TIJ): 0.000nsDiscrete Jitter (DJ): 0.000nsPhase Error (PE): 0.000nsMaximum Data Path: proc[3].add/dataout<3>_1_4 to proc[3].sbox/g0[3].g1[1].sub/byteout_4Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X24Y89.AQ Tcko 0.471 proc[3].add/dataout<3>_1_7proc[3].add/dataout<3>_1_4SLICE_X29Y84.B1 net (fanout=32) 1.591 proc[3].add/dataout<3>_1_4SLICE_X29Y84.B Tilo 0.094 proc[3].sbox/g0[3].g1[1].sub_Mrom_byteout_rom000083proc[3].sbox/g0[3].g1[1].sub_Mrom_byteout_rom000083SLICE_X28Y84.D6 net (fanout=1) 0.433 proc[3].sbox/g0[3].g1[1].sub_Mrom_byteout_rom000083SLICE_X28Y84.CLK Tas 0.225 proc[3].sbox/g0[3].g1[1].sub/byteout<4>proc[3].sbox/g0[3].g1[1].sub_Mrom_byteout_rom00008_f7_0proc[3].sbox/g0[3].g1[1].sub_Mrom_byteout_rom00008_f71_rtproc[3].sbox/g0[3].g1[1].sub_Mrom_byteout_rom00008_f8proc[3].sbox/g0[3].g1[1].sub/byteout_4------------------------------------------------- ---------------------------Total 2.814ns (0.790ns logic, 2.024ns route)(28.1% logic, 71.9% route)--------------------------------------------------------------------------------Slack (setup path): 0.029ns (requirement - (data path - clock path skew + uncertainty))Source: proc[4].add/dataout<0>_3_5 (FF)Destination: proc[4].sbox/g0[0].g1[3].sub/byteout_1 (FF)Requirement: 3.000nsData Path Delay: 2.833ns (Levels of Logic = 2)Clock Path Skew: -0.103ns (1.169 - 1.272)Source Clock: clk_i_BUFGP rising at 0.000nsDestination Clock: clk_i_BUFGP rising at 3.000nsClock Uncertainty: 0.035nsClock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PETotal System Jitter (TSJ): 0.070nsTotal Input Jitter (TIJ): 0.000nsDiscrete Jitter (DJ): 0.000nsPhase Error (PE): 0.000nsMaximum Data Path: proc[4].add/dataout<0>_3_5 to proc[4].sbox/g0[0].g1[3].sub/byteout_1Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X24Y60.BQ Tcko 0.471 proc[4].add/dataout<0>_3_7proc[4].add/dataout<0>_3_5SLICE_X19Y52.A4 net (fanout=32) 1.447 proc[4].add/dataout<0>_3_5SLICE_X19Y52.A Tilo 0.094 proc[4].sbox/g0[0].g1[3].sub_Mrom_byteout_rom0000141proc[4].sbox/g0[0].g1[3].sub_Mrom_byteout_rom000024SLICE_X15Y51.D6 net (fanout=1) 0.569 proc[4].sbox/g0[0].g1[3].sub_Mrom_byteout_rom000024SLICE_X15Y51.CLK Tas 0.252 proc[4].sbox/g0[0].g1[3].sub/byteout<1>proc[4].sbox/g0[0].g1[3].sub_Mrom_byteout_rom00002_f7_0proc[4].sbox/g0[0].g1[3].sub_Mrom_byteout_rom00002_f71_rtproc[4].sbox/g0[0].g1[3].sub_Mrom_byteout_rom00002_f8proc[4].sbox/g0[0].g1[3].sub/byteout_1------------------------------------------------- ---------------------------Total 2.833ns (0.817ns logic, 2.016ns route)(28.8% logic, 71.2% route)--------------------------------------------------------------------------------Slack (setup path): 0.031ns (requirement - (data path - clock path skew + uncertainty))Source: proc[7].add/dataout<0>_1_4 (FF)Destination: proc[7].sbox/g0[0].g1[1].sub/byteout_3 (FF)Requirement: 3.000nsData Path Delay: 2.875ns (Levels of Logic = 2)Clock Path Skew: -0.059ns (1.245 - 1.304)Source Clock: clk_i_BUFGP rising at 0.000nsDestination Clock: clk_i_BUFGP rising at 3.000nsClock Uncertainty: 0.035nsClock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PETotal System Jitter (TSJ): 0.070nsTotal Input Jitter (TIJ): 0.000nsDiscrete Jitter (DJ): 0.000nsPhase Error (PE): 0.000nsMaximum Data Path: proc[7].add/dataout<0>_1_4 to proc[7].sbox/g0[0].g1[1].sub/byteout_3Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X29Y13.AQ Tcko 0.450 proc[7].add/dataout<0>_1_7proc[7].add/dataout<0>_1_4SLICE_X27Y8.A1 net (fanout=32) 1.693 proc[7].add/dataout<0>_1_4SLICE_X27Y8.A Tilo 0.094 proc[7].sbox/g0[0].g1[1].sub_Mrom_byteout_rom000063proc[7].sbox/g0[0].g1[1].sub_Mrom_byteout_rom000063SLICE_X27Y10.D5 net (fanout=1) 0.386 proc[7].sbox/g0[0].g1[1].sub_Mrom_byteout_rom000063SLICE_X27Y10.CLK Tas 0.252 proc[7].sbox/g0[0].g1[1].sub/byteout<3>proc[7].sbox/g0[0].g1[1].sub_Mrom_byteout_rom00006_f7_0proc[7].sbox/g0[0].g1[1].sub_Mrom_byteout_rom00006_f71_rtproc[7].sbox/g0[0].g1[1].sub_Mrom_byteout_rom00006_f8proc[7].sbox/g0[0].g1[1].sub/byteout_3------------------------------------------------- ---------------------------Total 2.875ns (0.796ns logic, 2.079ns route)(27.7% logic, 72.3% route)--------------------------------------------------------------------------------Slack (setup path): 0.036ns (requirement - (data path - clock path skew + uncertainty))Source: proc[8].add/dataout<1>_3_4 (FF)Destination: proc[8].sbox/g0[1].g1[3].sub/byteout_3 (FF)Requirement: 3.000nsData Path Delay: 2.786ns (Levels of Logic = 2)Clock Path Skew: -0.143ns (1.130 - 1.273)Source Clock: clk_i_BUFGP rising at 0.000nsDestination Clock: clk_i_BUFGP rising at 3.000nsClock Uncertainty: 0.035nsClock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PETotal System Jitter (TSJ): 0.070nsTotal Input Jitter (TIJ): 0.000nsDiscrete Jitter (DJ): 0.000nsPhase Error (PE): 0.000nsMaximum Data Path: proc[8].add/dataout<1>_3_4 to proc[8].sbox/g0[1].g1[3].sub/byteout_3Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X36Y35.AQ Tcko 0.471 proc[8].add/dataout<1>_3_7proc[8].add/dataout<1>_3_4SLICE_X35Y42.C3 net (fanout=32) 1.552 proc[8].add/dataout<1>_3_4SLICE_X35Y42.C Tilo 0.094 sbox_f_1/g0[3].g1[2].sub_Mrom_byteout_rom000083proc[8].sbox/g0[1].g1[3].sub_Mrom_byteout_rom000063SLICE_X32Y42.D6 net (fanout=1) 0.444 proc[8].sbox/g0[1].g1[3].sub_Mrom_byteout_rom000063SLICE_X32Y42.CLK Tas 0.225 proc[8].sbox/g0[1].g1[3].sub/byteout<3>proc[8].sbox/g0[1].g1[3].sub_Mrom_byteout_rom00006_f7_0proc[8].sbox/g0[1].g1[3].sub_Mrom_byteout_rom00006_f71_rtproc[8].sbox/g0[1].g1[3].sub_Mrom_byteout_rom00006_f8proc[8].sbox/g0[1].g1[3].sub/byteout_3------------------------------------------------- ---------------------------Total 2.786ns (0.790ns logic, 1.996ns route)(28.4% logic, 71.6% route)--------------------------------------------------------------------------------Slack (setup path): 0.036ns (requirement - (data path - clock path skew + uncertainty))Source: proc[8].mix/g0[1].mix/out2_2 (FF)Destination: add_f_1/dataout<2>_1_2 (FF)Requirement: 3.000nsData Path Delay: 2.762ns (Levels of Logic = 1)Clock Path Skew: -0.167ns (1.208 - 1.375)Source Clock: clk_i_BUFGP rising at 0.000nsDestination Clock: clk_i_BUFGP rising at 3.000nsClock Uncertainty: 0.035nsClock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PETotal System Jitter (TSJ): 0.070nsTotal Input Jitter (TIJ): 0.000nsDiscrete Jitter (DJ): 0.000nsPhase Error (PE): 0.000nsMaximum Data Path: proc[8].mix/g0[1].mix/out2_2 to add_f_1/dataout<2>_1_2Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X55Y36.CQ Tcko 0.450 proc[8].mix/g0[1].mix/out2<5>proc[8].mix/g0[1].mix/out2_2SLICE_X57Y73.C5 net (fanout=1) 2.283 proc[8].mix/g0[1].mix/out2<2>SLICE_X57Y73.CLK Tas 0.029 add_f_1/dataout<2>_1_3add_f_1/Mxor_added<2><1>_Result<2>1add_f_1/dataout<2>_1_2------------------------------------------------- ---------------------------Total 2.762ns (0.479ns logic, 2.283ns route)(17.3% logic, 82.7% route)--------------------------------------------------------------------------------Slack (setup path): 0.040ns (requirement - (data path - clock path skew + uncertainty))Source: proc[5].sbox/g0[1].g1[1].sub/byteout_2 (FF)Destination: proc[5].mix/g0[0].mix/out1_3 (FF)Requirement: 3.000nsData Path Delay: 2.871ns (Levels of Logic = 1)Clock Path Skew: -0.054ns (1.331 - 1.385)Source Clock: clk_i_BUFGP rising at 0.000nsDestination Clock: clk_i_BUFGP rising at 3.000nsClock Uncertainty: 0.035nsClock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PETotal System Jitter (TSJ): 0.070nsTotal Input Jitter (TIJ): 0.000nsDiscrete Jitter (DJ): 0.000nsPhase Error (PE): 0.000nsMaximum Data Path: proc[5].sbox/g0[1].g1[1].sub/byteout_2 to proc[5].mix/g0[0].mix/out1_3Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X0Y32.BQ Tcko 0.471 proc[5].sbox/g0[1].g1[1].sub/byteout<2>proc[5].sbox/g0[1].g1[1].sub/byteout_2SLICE_X10Y18.A6 net (fanout=7) 2.253 proc[5].sbox/g0[1].g1[1].sub/byteout<2>SLICE_X10Y18.CLK Tas 0.147 proc[5].mix/g0[0].mix/out1<3>proc[5].mix/g0[0].mix/out1_xor0000<3>1proc[5].mix/g0[0].mix/out1_xor0000<3>_f7proc[5].mix/g0[0].mix/out1_3------------------------------------------------- ---------------------------Total 2.871ns (0.618ns logic, 2.253ns route)(21.5% logic, 78.5% route)--------------------------------------------------------------------------------Slack (setup path): 0.041ns (requirement - (data path - clock path skew + uncertainty))Source: proc[6].add/dataout<2>_0_5 (FF)Destination: proc[6].sbox/g0[2].g1[0].sub/byteout_4 (FF)Requirement: 3.000nsData Path Delay: 2.742ns (Levels of Logic = 2)Clock Path Skew: -0.182ns (1.254 - 1.436)Source Clock: clk_i_BUFGP rising at 0.000nsDestination Clock: clk_i_BUFGP rising at 3.000nsClock Uncertainty: 0.035nsClock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PETotal System Jitter (TSJ): 0.070nsTotal Input Jitter (TIJ): 0.000nsDiscrete Jitter (DJ): 0.000nsPhase Error (PE): 0.000nsMaximum Data Path: proc[6].add/dataout<2>_0_5 to proc[6].sbox/g0[2].g1[0].sub/byteout_4Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X14Y16.BQ Tcko 0.450 proc[6].add/dataout<2>_0_7proc[6].add/dataout<2>_0_5SLICE_X20Y20.C2 net (fanout=32) 1.524 proc[6].add/dataout<2>_0_5SLICE_X20Y20.C Tilo 0.094 proc[6].sbox/g0[2].g1[0].sub/byteout<4>proc[6].sbox/g0[2].g1[0].sub_Mrom_byteout_rom000082SLICE_X20Y20.D6 net (fanout=1) 0.449 proc[6].sbox/g0[2].g1[0].sub_Mrom_byteout_rom000082SLICE_X20Y20.CLK Tas 0.225 proc[6].sbox/g0[2].g1[0].sub/byteout<4>proc[6].sbox/g0[2].g1[0].sub_Mrom_byteout_rom00008_f7_0proc[6].sbox/g0[2].g1[0].sub_Mrom_byteout_rom00008_f71_rtproc[6].sbox/g0[2].g1[0].sub_Mrom_byteout_rom00008_f8proc[6].sbox/g0[2].g1[0].sub/byteout_4------------------------------------------------- ---------------------------Total 2.742ns (0.769ns logic, 1.973ns route)(28.0% logic, 72.0% route)--------------------------------------------------------------------------------Slack (setup path): 0.041ns (requirement - (data path - clock path skew + uncertainty))Source: proc[5].sbox/g0[1].g1[1].sub/byteout_2 (FF)Destination: proc[5].mix/g0[0].mix/out1_3 (FF)Requirement: 3.000nsData Path Delay: 2.870ns (Levels of Logic = 1)Clock Path Skew: -0.054ns (1.331 - 1.385)Source Clock: clk_i_BUFGP rising at 0.000nsDestination Clock: clk_i_BUFGP rising at 3.000nsClock Uncertainty: 0.035nsClock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PETotal System Jitter (TSJ): 0.070nsTotal Input Jitter (TIJ): 0.000nsDiscrete Jitter (DJ): 0.000nsPhase Error (PE): 0.000nsMaximum Data Path: proc[5].sbox/g0[1].g1[1].sub/byteout_2 to proc[5].mix/g0[0].mix/out1_3Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X0Y32.BQ Tcko 0.471 proc[5].sbox/g0[1].g1[1].sub/byteout<2>proc[5].sbox/g0[1].g1[1].sub/byteout_2SLICE_X10Y18.B6 net (fanout=7) 2.260 proc[5].sbox/g0[1].g1[1].sub/byteout<2>SLICE_X10Y18.CLK Tas 0.139 proc[5].mix/g0[0].mix/out1<3>proc[5].mix/g0[0].mix/out1_xor0000<3>2proc[5].mix/g0[0].mix/out1_xor0000<3>_f7proc[5].mix/g0[0].mix/out1_3------------------------------------------------- ---------------------------Total 2.870ns (0.610ns logic, 2.260ns route)(21.3% logic, 78.7% route)--------------------------------------------------------------------------------Hold Paths: TS_clk = PERIOD TIMEGRP "clk_i" 3 ns HIGH 50%;--------------------------------------------------------------------------------Slack (hold path): 0.296ns (requirement - (clock path skew + uncertainty - data path))Source: proc[0].sbox/nextkey<0>_2_5 (FF)Destination: proc[0].mix/outrkey<0>_2_5 (FF)Requirement: 0.000nsData Path Delay: 0.452ns (Levels of Logic = 0)Clock Path Skew: 0.156ns (1.377 - 1.221)Source Clock: clk_i_BUFGP rising at 3.000nsDestination Clock: clk_i_BUFGP rising at 3.000nsClock Uncertainty: 0.000nsMinimum Data Path: proc[0].sbox/nextkey<0>_2_5 to proc[0].mix/outrkey<0>_2_5Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X55Y79.BQ Tcko 0.414 proc[0].sbox/nextkey<0>_2_7proc[0].sbox/nextkey<0>_2_5SLICE_X56Y80.BX net (fanout=1) 0.280 proc[0].sbox/nextkey<0>_2_5SLICE_X56Y80.CLK Tckdi (-Th) 0.242 proc[0].mix/outrkey<0>_2_7proc[0].mix/outrkey<0>_2_5------------------------------------------------- ---------------------------Total 0.452ns (0.172ns logic, 0.280ns route)(38.1% logic, 61.9% route)--------------------------------------------------------------------------------Slack (hold path): 0.339ns (requirement - (clock path skew + uncertainty - data path))Source: proc[1].sbox/nextkey<0>_0_5 (FF)Destination: proc[1].mix/outrkey<0>_0_5 (FF)Requirement: 0.000nsData Path Delay: 0.472ns (Levels of Logic = 0)Clock Path Skew: 0.133ns (1.348 - 1.215)Source Clock: clk_i_BUFGP rising at 3.000nsDestination Clock: clk_i_BUFGP rising at 3.000nsClock Uncertainty: 0.000nsMinimum Data Path: proc[1].sbox/nextkey<0>_0_5 to proc[1].mix/outrkey<0>_0_5Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X43Y99.BQ Tcko 0.414 proc[1].sbox/nextkey<0>_0_7proc[1].sbox/nextkey<0>_0_5SLICE_X43Y101.BX net (fanout=1) 0.289 proc[1].sbox/nextkey<0>_0_5SLICE_X43Y101.CLK Tckdi (-Th) 0.231 proc[1].mix/outrkey<0>_0_7proc[1].mix/outrkey<0>_0_5------------------------------------------------- ---------------------------Total 0.472ns (0.183ns logic, 0.289ns route)(38.8% logic, 61.2% route)--------------------------------------------------------------------------------Slack (hold path): 0.412ns (requirement - (clock path skew + uncertainty - data path))Source: proc[0].add/step1/sub1/byteout_5 (FF)Destination: proc[0].sbox/nextkey<0>_0_5 (FF)Requirement: 0.000nsData Path Delay: 0.499ns (Levels of Logic = 1)Clock Path Skew: 0.087ns (0.577 - 0.490)Source Clock: clk_i_BUFGP rising at 3.000nsDestination Clock: clk_i_BUFGP rising at 3.000nsClock Uncertainty: 0.000nsMinimum Data Path: proc[0].add/step1/sub1/byteout_5 to proc[0].sbox/nextkey<0>_0_5Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X45Y79.BQ Tcko 0.414 proc[0].add/step1/sub1/byteout<5>proc[0].add/step1/sub1/byteout_5SLICE_X46Y79.B6 net (fanout=4) 0.281 proc[0].add/step1/sub1/byteout<5>SLICE_X46Y79.CLK Tah (-Th) 0.196 proc[0].sbox/nextkey<0>_0_7proc[0].sbox/Mxor_nextkey<0>_0_xor0000_Result<5>1proc[0].sbox/nextkey<0>_0_5------------------------------------------------- ---------------------------Total 0.499ns (0.218ns logic, 0.281ns route)(43.7% logic, 56.3% route)--------------------------------------------------------------------------------Slack (hold path): 0.419ns (requirement - (clock path skew + uncertainty - data path))Source: proc[1].sbox/nextkey<1>_1_2 (FF)Destination: proc[1].mix/outrkey<1>_1_2 (FF)Requirement: 0.000nsData Path Delay: 0.491ns (Levels of Logic = 0)Clock Path Skew: 0.072ns (0.543 - 0.471)Source Clock: clk_i_BUFGP rising at 3.000nsDestination Clock: clk_i_BUFGP rising at 3.000nsClock Uncertainty: 0.000nsMinimum Data Path: proc[1].sbox/nextkey<1>_1_2 to proc[1].mix/outrkey<1>_1_2Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X27Y108.CQ Tcko 0.414 proc[1].sbox/nextkey<1>_1_3proc[1].sbox/nextkey<1>_1_2SLICE_X22Y108.CX net (fanout=1) 0.295 proc[1].sbox/nextkey<1>_1_2SLICE_X22Y108.CLK Tckdi (-Th) 0.218 proc[1].mix/outrkey<1>_1_3proc[1].mix/outrkey<1>_1_2------------------------------------------------- ---------------------------Total 0.491ns (0.196ns logic, 0.295ns route)(39.9% logic, 60.1% route)--------------------------------------------------------------------------------Slack (hold path): 0.420ns (requirement - (clock path skew + uncertainty - data path))Source: proc[6].add/step1/c0_3_4 (FF)Destination: proc[6].sbox/nextkey<3>_0_4 (FF)Requirement: 0.000nsData Path Delay: 0.474ns (Levels of Logic = 1)Clock Path Skew: 0.054ns (0.493 - 0.439)Source Clock: clk_i_BUFGP rising at 3.000nsDestination Clock: clk_i_BUFGP rising at 3.000nsClock Uncertainty: 0.000nsMinimum Data Path: proc[6].add/step1/c0_3_4 to proc[6].sbox/nextkey<3>_0_4Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X31Y24.AQ Tcko 0.414 proc[6].add/step1/c0_3_7proc[6].add/step1/c0_3_4SLICE_X33Y24.A6 net (fanout=1) 0.257 proc[6].add/step1/c0_3_4SLICE_X33Y24.CLK Tah (-Th) 0.197 proc[6].sbox/nextkey<3>_0_7proc[6].sbox/Mxor_nextkey<3>_0_xor0000_Result<4>1proc[6].sbox/nextkey<3>_0_4------------------------------------------------- ---------------------------Total 0.474ns (0.217ns logic, 0.257ns route)(45.8% logic, 54.2% route)--------------------------------------------------------------------------------Slack (hold path): 0.421ns (requirement - (clock path skew + uncertainty - data path))Source: proc[8].add/step1/c0_3_0 (FF)Destination: proc[8].sbox/nextkey<3>_0_0 (FF)Requirement: 0.000nsData Path Delay: 0.461ns (Levels of Logic = 1)Clock Path Skew: 0.040ns (0.546 - 0.506)Source Clock: clk_i_BUFGP rising at 3.000nsDestination Clock: clk_i_BUFGP rising at 3.000nsClock Uncertainty: 0.000nsMinimum Data Path: proc[8].add/step1/c0_3_0 to proc[8].sbox/nextkey<3>_0_0Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X51Y36.AQ Tcko 0.414 proc[8].add/step1/c0_3_3proc[8].add/step1/c0_3_0SLICE_X48Y36.A6 net (fanout=1) 0.266 proc[8].add/step1/c0_3_0SLICE_X48Y36.CLK Tah (-Th) 0.219 proc[8].sbox/nextkey<3>_0_3proc[8].sbox/Mxor_nextkey<3>_0_xor0000_Result<0>1proc[8].sbox/nextkey<3>_0_0------------------------------------------------- ---------------------------Total 0.461ns (0.195ns logic, 0.266ns route)(42.3% logic, 57.7% route)--------------------------------------------------------------------------------Slack (hold path): 0.422ns (requirement - (clock path skew + uncertainty - data path))Source: proc[3].add/step1/c0_3_4 (FF)Destination: proc[3].sbox/nextkey<3>_0_4 (FF)Requirement: 0.000nsData Path Delay: 0.480ns (Levels of Logic = 1)Clock Path Skew: 0.058ns (0.470 - 0.412)Source Clock: clk_i_BUFGP rising at 3.000nsDestination Clock: clk_i_BUFGP rising at 3.000nsClock Uncertainty: 0.000nsMinimum Data Path: proc[3].add/step1/c0_3_4 to proc[3].sbox/nextkey<3>_0_4Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X33Y70.AQ Tcko 0.414 proc[3].add/step1/c0_3_7proc[3].add/step1/c0_3_4SLICE_X30Y70.A6 net (fanout=1) 0.263 proc[3].add/step1/c0_3_4SLICE_X30Y70.CLK Tah (-Th) 0.197 proc[3].sbox/nextkey<3>_0_7proc[3].sbox/Mxor_nextkey<3>_0_xor0000_Result<4>1proc[3].sbox/nextkey<3>_0_4------------------------------------------------- ---------------------------Total 0.480ns (0.217ns logic, 0.263ns route)(45.2% logic, 54.8% route)--------------------------------------------------------------------------------Slack (hold path): 0.422ns (requirement - (clock path skew + uncertainty - data path))Source: proc[6].mix/g0[2].mix/out1_1 (FF)Destination: proc[7].add/dataout<1>_2_1 (FF)Requirement: 0.000nsData Path Delay: 0.464ns (Levels of Logic = 1)Clock Path Skew: 0.042ns (0.542 - 0.500)Source Clock: clk_i_BUFGP rising at 3.000nsDestination Clock: clk_i_BUFGP rising at 3.000nsClock Uncertainty: 0.000nsMinimum Data Path: proc[6].mix/g0[2].mix/out1_1 to proc[7].add/dataout<1>_2_1Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X27Y20.AQ Tcko 0.414 proc[6].mix/g0[2].mix/out1<2>proc[6].mix/g0[2].mix/out1_1SLICE_X24Y20.B6 net (fanout=1) 0.272 proc[6].mix/g0[2].mix/out1<1>SLICE_X24Y20.CLK Tah (-Th) 0.222 proc[7].add/dataout<1>_2_3proc[7].add/Mxor_added<1><2>_Result<1>1proc[7].add/dataout<1>_2_1------------------------------------------------- ---------------------------Total 0.464ns (0.192ns logic, 0.272ns route)(41.4% logic, 58.6% route)--------------------------------------------------------------------------------Slack (hold path): 0.422ns (requirement - (clock path skew + uncertainty - data path))Source: add_f_1/step1/c2_3_2 (FF)Destination: sbox_f_1/nextkey<3>_2_2 (FF)Requirement: 0.000nsData Path Delay: 0.486ns (Levels of Logic = 1)Clock Path Skew: 0.064ns (0.559 - 0.495)Source Clock: clk_i_BUFGP rising at 3.000nsDestination Clock: clk_i_BUFGP rising at 3.000nsClock Uncertainty: 0.000nsMinimum Data Path: add_f_1/step1/c2_3_2 to sbox_f_1/nextkey<3>_2_2Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X49Y45.CQ Tcko 0.414 add_f_1/step1/c2_3_3add_f_1/step1/c2_3_2SLICE_X50Y44.C6 net (fanout=1) 0.267 add_f_1/step1/c2_3_2SLICE_X50Y44.CLK Tah (-Th) 0.195 sbox_f_1/nextkey<3>_2_3sbox_f_1/Mxor_nextkey<3>_2_xor0000_Result<2>1sbox_f_1/nextkey<3>_2_2------------------------------------------------- ---------------------------Total 0.486ns (0.219ns logic, 0.267ns route)(45.1% logic, 54.9% route)--------------------------------------------------------------------------------Slack (hold path): 0.423ns (requirement - (clock path skew + uncertainty - data path))Source: proc[6].add/step1/c0_3_7 (FF)Destination: proc[6].sbox/nextkey<3>_0_7 (FF)Requirement: 0.000nsData Path Delay: 0.477ns (Levels of Logic = 1)Clock Path Skew: 0.054ns (0.493 - 0.439)Source Clock: clk_i_BUFGP rising at 3.000nsDestination Clock: clk_i_BUFGP rising at 3.000nsClock Uncertainty: 0.000nsMinimum Data Path: proc[6].add/step1/c0_3_7 to proc[6].sbox/nextkey<3>_0_7Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X31Y24.DQ Tcko 0.414 proc[6].add/step1/c0_3_7proc[6].add/step1/c0_3_7SLICE_X33Y24.D6 net (fanout=1) 0.258 proc[6].add/step1/c0_3_7SLICE_X33Y24.CLK Tah (-Th) 0.195 proc[6].sbox/nextkey<3>_0_7proc[6].sbox/Mxor_nextkey<3>_0_xor0000_Result<7>1proc[6].sbox/nextkey<3>_0_7------------------------------------------------- ---------------------------Total 0.477ns (0.219ns logic, 0.258ns route)(45.9% logic, 54.1% route)--------------------------------------------------------------------------------Component Switching Limit Checks: TS_clk = PERIOD TIMEGRP "clk_i" 3 ns HIGH 50%;--------------------------------------------------------------------------------Slack: 1.946ns (period - (min low pulse limit / (low pulse / period)))Period: 3.000nsLow pulse: 1.500nsLow pulse limit: 0.527ns (Trpw)Physical resource: proc[8].sbox/g0[0].g1[3].sub/byteout<3>/SRLogical resource: proc[8].sbox/g0[0].g1[3].sub/byteout_3/SRLocation pin: SLICE_X38Y26.SRClock network: rst_i_BUFGP--------------------------------------------------------------------------------Slack: 1.946ns (period - (min high pulse limit / (high pulse / period)))Period: 3.000nsHigh pulse: 1.500nsHigh pulse limit: 0.527ns (Trpw)Physical resource: proc[8].sbox/g0[0].g1[3].sub/byteout<3>/SRLogical resource: proc[8].sbox/g0[0].g1[3].sub/byteout_3/SRLocation pin: SLICE_X38Y26.SRClock network: rst_i_BUFGP--------------------------------------------------------------------------------Slack: 1.946ns (period - (min low pulse limit / (low pulse / period)))Period: 3.000nsLow pulse: 1.500nsLow pulse limit: 0.527ns (Trpw)Physical resource: proc[8].sbox/g0[2].g1[3].sub/byteout<3>/SRLogical resource: proc[8].sbox/g0[2].g1[3].sub/byteout_3/SRLocation pin: SLICE_X59Y24.SRClock network: rst_i_BUFGP--------------------------------------------------------------------------------Slack: 1.946ns (period - (min high pulse limit / (high pulse / period)))Period: 3.000nsHigh pulse: 1.500nsHigh pulse limit: 0.527ns (Trpw)Physical resource: proc[8].sbox/g0[2].g1[3].sub/byteout<3>/SRLogical resource: proc[8].sbox/g0[2].g1[3].sub/byteout_3/SRLocation pin: SLICE_X59Y24.SRClock network: rst_i_BUFGP--------------------------------------------------------------------------------Slack: 1.946ns (period - (min low pulse limit / (low pulse / period)))Period: 3.000nsLow pulse: 1.500nsLow pulse limit: 0.527ns (Trpw)Physical resource: proc[8].sbox/g0[3].g1[3].sub/byteout<3>/SRLogical resource: proc[8].sbox/g0[3].g1[3].sub/byteout_3/SRLocation pin: SLICE_X58Y42.SRClock network: rst_i_BUFGP--------------------------------------------------------------------------------Slack: 1.946ns (period - (min high pulse limit / (high pulse / period)))Period: 3.000nsHigh pulse: 1.500nsHigh pulse limit: 0.527ns (Trpw)Physical resource: proc[8].sbox/g0[3].g1[3].sub/byteout<3>/SRLogical resource: proc[8].sbox/g0[3].g1[3].sub/byteout_3/SRLocation pin: SLICE_X58Y42.SRClock network: rst_i_BUFGP--------------------------------------------------------------------------------Slack: 1.946ns (period - (min low pulse limit / (low pulse / period)))Period: 3.000nsLow pulse: 1.500nsLow pulse limit: 0.527ns (Trpw)Physical resource: proc[7].sbox/g0[1].g1[3].sub/byteout<3>/SRLogical resource: proc[7].sbox/g0[1].g1[3].sub/byteout_3/SRLocation pin: SLICE_X42Y7.SRClock network: rst_i_BUFGP--------------------------------------------------------------------------------Slack: 1.946ns (period - (min high pulse limit / (high pulse / period)))Period: 3.000nsHigh pulse: 1.500nsHigh pulse limit: 0.527ns (Trpw)Physical resource: proc[7].sbox/g0[1].g1[3].sub/byteout<3>/SRLogical resource: proc[7].sbox/g0[1].g1[3].sub/byteout_3/SRLocation pin: SLICE_X42Y7.SRClock network: rst_i_BUFGP--------------------------------------------------------------------------------Slack: 1.946ns (period - (min low pulse limit / (low pulse / period)))Period: 3.000nsLow pulse: 1.500nsLow pulse limit: 0.527ns (Trpw)Physical resource: proc[7].sbox/g0[2].g1[3].sub/byteout<3>/SRLogical resource: proc[7].sbox/g0[2].g1[3].sub/byteout_3/SRLocation pin: SLICE_X33Y11.SRClock network: rst_i_BUFGP--------------------------------------------------------------------------------Slack: 1.946ns (period - (min high pulse limit / (high pulse / period)))Period: 3.000nsHigh pulse: 1.500nsHigh pulse limit: 0.527ns (Trpw)Physical resource: proc[7].sbox/g0[2].g1[3].sub/byteout<3>/SRLogical resource: proc[7].sbox/g0[2].g1[3].sub/byteout_3/SRLocation pin: SLICE_X33Y11.SRClock network: rst_i_BUFGP--------------------------------------------------------------------------------All constraints were met.Data Sheet report:-----------------All values displayed in nanoseconds (ns)Clock to Setup on destination clock clk_i---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+clk_i | 2.974| | | |---------------+---------+---------+---------+---------+Timing summary:---------------Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)Constraints cover 59472 paths, 0 nets, and 69148 connectionsDesign statistics:Minimum period: 2.974ns{1} (Maximum frequency: 336.247MHz)------------------------------------Footnotes-----------------------------------1) The minimum period statistic assumes all single cycle delays.Analysis completed Thu Mar 25 15:34:03 2010--------------------------------------------------------------------------------Trace Settings:-------------------------Trace SettingsPeak Memory Usage: 381 MB