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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [ip/] [Communication/] [ethmac_100.IP] - Rev 48
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#######################################################################
## File: ethmac_100.IP
##
## Copyright (C) 2014-2019 Alireza Monemi
##
## This file is part of ProNoC 1.9.1
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
$ipgen = bless( {
'version' => 2,
'parameters' => {
'TX_FIFO_DATA_WIDTH' => {
'type' => 'Fixed',
'global_param' => 0,
'redefine_param' => 1,
'default' => ' 32',
'content' => '',
'info' => undef
},
'TX_FIFO_DEPTH' => {
'default' => ' 16',
'content' => '',
'info' => undef,
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 0
},
'RX_FIFO_CNT_WIDTH' => {
'info' => undef,
'default' => ' 5',
'content' => '',
'global_param' => 0,
'redefine_param' => 1,
'type' => 'Fixed'
},
'RX_FIFO_DATA_WIDTH' => {
'default' => ' 32',
'content' => '',
'info' => undef,
'type' => 'Fixed',
'global_param' => 0,
'redefine_param' => 1
},
'TX_FIFO_CNT_WIDTH' => {
'content' => '',
'default' => ' 5',
'info' => undef,
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 0
},
'RX_FIFO_DEPTH' => {
'default' => ' 16',
'content' => '',
'info' => undef,
'type' => 'Fixed',
'global_param' => 0,
'redefine_param' => 1
}
},
'gen_sw_files' => [
'/mpsoc/rtl/src_peripheral/ethmac/ethfrename_sep_t${IP}.h'
],
'system_h' => '
void ${IP}_init();
void ${IP}_interrupt();
void ${IP}_recv_ack(void);
int ${IP}_send(int length); //return (-1) or length (still processing previous) or asserted
#define ${IP}_BASE_ADDR $BASE
#define ${IP}_MODER (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x00 )))
#define ${IP}_INT_SOURCE (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x04 )))
#define ${IP}_INT_MASK (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x08 )))
#define ${IP}_IPGT (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x0C )))
#define ${IP}_IPGR1 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x10 )))
#define ${IP}_IPGR2 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x14 )))
#define ${IP}_PACKETLEN (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x18 )))
#define ${IP}_COLLCONF (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x1C )))
#define ${IP}_TX_BD_NUM (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x20 )))
#define ${IP}_CTRLMODER (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x24 )))
#define ${IP}_MIIMODER (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x28 )))
#define ${IP}_MIICOMMAND (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x2C )))
#define ${IP}_MIIADDR (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x30 )))
#define ${IP}_MIITX_DATA (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x34 )))
#define ${IP}_MIIRX_DATA (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x38 )))
#define ${IP}_MIISTATUS (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x3C )))
#define ${IP}_MAC_ADDR0 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x40 )))
#define ${IP}_MAC_ADDR1 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x44 )))
#define ${IP}_HASH0_ADR (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x48 )))
#define ${IP}_HASH1_ADR (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x4C )))
#define ${IP}_TXCTRL (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x50 )))
#define ${IP}_TXBD0H (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x404 )))
#define ${IP}_TXBD0L (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x400 )))
#define ${IP}_RXBD0H (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x604 ))) //this depends on TX_BD_NUM but this is the standard value
#define ${IP}_RXBD0L (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x600 ))) //this depends on TX_BD_NUM but this is the standard value
#include "${IP}.h"',
'plugs' => {
'reset' => {
'reset' => {},
'type' => 'num',
'value' => 1,
'0' => {
'name' => 'reset'
}
},
'wb_slave' => {
'value' => 1,
'type' => 'num',
'wb_slave' => {},
'0' => {
'width' => 11,
'name' => 'wb_slave',
'addr' => '0x9200_0000 0x92ff_ffff Ethernet Controller'
}
},
'interrupt_peripheral' => {
'0' => {
'name' => 'interrupt_peripheral'
},
'interrupt_peripheral' => {},
'type' => 'num',
'value' => 1
},
'clk' => {
'clk' => {},
'0' => {
'name' => 'clk'
},
'type' => 'num',
'value' => 1
},
'wb_master' => {
'value' => 1,
'type' => 'num',
'wb_master' => {},
'0' => {
'name' => 'wb_master'
}
}
},
'sw_files' => [],
'custom_file' => {
'0' => {}
},
'file_name' => 'mpsoc/rtl/src_peripheral/ethmac/ethtop.v',
'custom_file_num' => 1,
'parameters_order' => [
'TX_FIFO_DATA_WIDTH',
'TX_FIFO_DEPTH',
'TX_FIFO_CNT_WIDTH',
'RX_FIFO_DATA_WIDTH',
'RX_FIFO_DEPTH',
'RX_FIFO_CNT_WIDTH'
],
'ip_name' => 'ethmac_100',
'description' => 'The Ethernet MAC 10/100 Mbps.
For more information please check: https://opencores.org/project,ethmac',
'ports' => {
'm_wb_adr_o' => {
'intfc_port' => 'adr_o',
'range' => '31:0',
'type' => 'output',
'intfc_name' => 'plug:wb_master[0]'
},
'wb_err_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'type' => 'output',
'intfc_port' => 'err_o'
},
'wb_we_i' => {
'range' => '',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'we_i'
},
'm_wb_sel_o' => {
'intfc_name' => 'plug:wb_master[0]',
'range' => '3:0',
'type' => 'output',
'intfc_port' => 'sel_o'
},
'mrxdv_pad_i' => {
'range' => '',
'type' => 'input',
'intfc_name' => 'IO',
'intfc_port' => 'IO'
},
'int_o' => {
'intfc_port' => 'int_o',
'type' => 'output',
'range' => '',
'intfc_name' => 'plug:interrupt_peripheral[0]'
},
'm_wb_dat_i' => {
'intfc_port' => 'dat_i',
'type' => 'input',
'range' => '31:0',
'intfc_name' => 'plug:wb_master[0]'
},
'wb_clk_i' => {
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:clk[0]',
'intfc_port' => 'clk_i'
},
'm_wb_ack_i' => {
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'ack_i'
},
'wb_rst_i' => {
'intfc_port' => 'reset_i',
'range' => '',
'type' => 'input',
'intfc_name' => 'plug:reset[0]'
},
'mrxd_pad_i' => {
'intfc_port' => 'IO',
'range' => '3:0',
'type' => 'input',
'intfc_name' => 'IO'
},
'mtxerr_pad_o' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'type' => 'output',
'range' => ''
},
'md_pad_o' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'type' => 'output',
'range' => ''
},
'wb_adr_i' => {
'intfc_port' => 'adr_i',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input',
'range' => '9:0'
},
'wb_dat_o' => {
'intfc_port' => 'dat_o',
'intfc_name' => 'plug:wb_slave[0]',
'range' => '31:0',
'type' => 'output'
},
'm_wb_err_i' => {
'intfc_name' => 'plug:wb_master[0]',
'type' => 'input',
'range' => '',
'intfc_port' => 'err_i'
},
'mtxen_pad_o' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'range' => '',
'type' => 'output'
},
'mrxerr_pad_i' => {
'type' => 'input',
'range' => '',
'intfc_name' => 'IO',
'intfc_port' => 'IO'
},
'mtx_clk_pad_i' => {
'type' => 'input',
'range' => '',
'intfc_name' => 'IO',
'intfc_port' => 'IO'
},
'm_wb_stb_o' => {
'intfc_port' => 'stb_o',
'intfc_name' => 'plug:wb_master[0]',
'type' => 'output',
'range' => ''
},
'mcrs_pad_i' => {
'type' => 'input',
'range' => '',
'intfc_name' => 'IO',
'intfc_port' => 'IO'
},
'm_wb_dat_o' => {
'intfc_port' => 'dat_o',
'intfc_name' => 'plug:wb_master[0]',
'type' => 'output',
'range' => '31:0'
},
'm_wb_we_o' => {
'intfc_port' => 'we_o',
'range' => '',
'type' => 'output',
'intfc_name' => 'plug:wb_master[0]'
},
'mdc_pad_o' => {
'range' => '',
'type' => 'output',
'intfc_name' => 'IO',
'intfc_port' => 'IO'
},
'mtxd_pad_o' => {
'type' => 'output',
'range' => '3:0',
'intfc_name' => 'IO',
'intfc_port' => 'IO'
},
'wb_stb_i' => {
'intfc_port' => 'stb_i',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input',
'range' => ''
},
'md_pad_i' => {
'intfc_name' => 'IO',
'range' => '',
'type' => 'input',
'intfc_port' => 'IO'
},
'wb_ack_o' => {
'range' => '',
'type' => 'output',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'ack_o'
},
'mcoll_pad_i' => {
'intfc_name' => 'IO',
'range' => '',
'type' => 'input',
'intfc_port' => 'IO'
},
'm_wb_cyc_o' => {
'range' => '',
'type' => 'output',
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'cyc_o'
},
'wb_cyc_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'cyc_i'
},
'wb_sel_i' => {
'intfc_port' => 'sel_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => '3:0',
'type' => 'input'
},
'wb_dat_i' => {
'intfc_port' => 'dat_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => '31:0',
'type' => 'input'
},
'md_padoe_o' => {
'intfc_name' => 'IO',
'type' => 'output',
'range' => '',
'intfc_port' => 'IO'
},
'mrx_clk_pad_i' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'range' => '',
'type' => 'input'
}
},
'module_name' => 'ethtop',
'unused' => {
'plug:wb_master[0]' => [
'tag_o',
'rty_i',
'bte_o',
'cti_o'
],
'plug:wb_slave[0]' => [
'cti_i',
'bte_i',
'rty_o',
'tag_i'
]
},
'hdl_files' => [
'/mpsoc/rtl/src_peripheral/ethmac'
],
'category' => 'Communication',
'modules' => {
'ethtop' => {}
},
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'ports_order' => [
'wb_clk_i',
'wb_rst_i',
'wb_dat_i',
'wb_dat_o',
'wb_adr_i',
'wb_sel_i',
'wb_we_i',
'wb_cyc_i',
'wb_stb_i',
'wb_ack_o',
'wb_err_o',
'm_wb_adr_o',
'm_wb_sel_o',
'm_wb_we_o',
'm_wb_dat_o',
'm_wb_dat_i',
'm_wb_cyc_o',
'm_wb_stb_o',
'm_wb_ack_i',
'm_wb_err_i',
'mtx_clk_pad_i',
'mtxd_pad_o',
'mtxen_pad_o',
'mtxerr_pad_o',
'mrx_clk_pad_i',
'mrxd_pad_i',
'mrxdv_pad_i',
'mrxerr_pad_i',
'mcoll_pad_i',
'mcrs_pad_i',
'mdc_pad_o',
'md_pad_i',
'md_pad_o',
'md_padoe_o',
'int_o'
],
'system_c' => 'void ${IP}_recv_ack(void)
{
${IP}_rx_done = 0;
${IP}_rx_len = 0;
//accept further data (reset RXBD to empty)
${IP}_RXBD0L = RX_READY; //len = 0 | IRQ & WR = 1 | EMPTY = 1
}
void ${IP}_init()
{
//TXEN & RXEN = 1; PAD & CRC = 1; FULLD = 1
${IP}_MODER = ETH_TXEN | ETH_RXEN | ETH_PAD | ETH_CRCEN | ETH_FULLD;
//PHY ADDR = 0x001
${IP}_MIIADDR = 0x00000001;
//enable all interrupts
${IP}_INT_MASK = ETH_RXB | ETH_TXB;
//set MAC ADDR
${IP}_MAC_ADDR1 = (${IP}_MAC_ADDR_5 << 8) | ${IP}_MAC_ADDR_4; //low word = mac ADDR high word
${IP}_MAC_ADDR0 = (${IP}_MAC_ADDR_3 << 24) | (${IP}_MAC_ADDR_2 << 16)
| (${IP}_MAC_ADDR_1 << 8) | ${IP}_MAC_ADDR_0; //mac ADDR rest
//configure TXBD0
${IP}_TXBD0H = (unsigned long) ${IP}_tx_packet; //ADDR used for tx_data
${IP}_TXBD0L = TX_READY; //length = 0 | PAD & CRC = 1 | IRQ & WR = 1
//configure RXBD0
${IP}_RXBD0H = (unsigned long)${IP}_rx_packet; //ADDR used for tx_data
${IP}_RXBD0L = RX_READY; //len = 0 | IRQ & WR = 1 | EMPTY = 1
//set txdata
${IP}_tx_packet[0] = ${IP}_BROADCAST_ADDR_5;
${IP}_tx_packet[1] = ${IP}_BROADCAST_ADDR_4;
${IP}_tx_packet[2] = ${IP}_BROADCAST_ADDR_3;
${IP}_tx_packet[3] = ${IP}_BROADCAST_ADDR_2;
${IP}_tx_packet[4] = ${IP}_BROADCAST_ADDR_1;
${IP}_tx_packet[5] = ${IP}_BROADCAST_ADDR_0;
${IP}_tx_packet[6] = ${IP}_MAC_ADDR_5;
${IP}_tx_packet[7] = ${IP}_MAC_ADDR_4;
${IP}_tx_packet[8] = ${IP}_MAC_ADDR_3;
${IP}_tx_packet[9] = ${IP}_MAC_ADDR_2;
${IP}_tx_packet[10] = ${IP}_MAC_ADDR_1;
${IP}_tx_packet[11] = ${IP}_MAC_ADDR_0;
//erase interrupts
${IP}_INT_SOURCE = ETH_RXC | ETH_TXC | ETH_BUSY | ETH_RXE | ETH_RXB | ETH_TXE | ETH_TXB;
${IP}_tx_done = 1;
${IP}_rx_done = 0;
${IP}_rx_len = 0;
${IP}_tx_data = & ${IP}_tx_packet[HDR_LEN];
${IP}_rx_data = & ${IP}_rx_packet[HDR_LEN];
}
int ${IP}_send(int length)
{
if (!${IP}_tx_done) //if previous command not fully processed, bail out
return -1;
${IP}_tx_done = 0;
${IP}_tx_packet[12] = length >> 8;
${IP}_tx_packet[13] = length;
${IP}_TXBD0L = (( 0x0000FFFF & ( length + HDR_LEN ) ) << 16) | BD_SND;
return length;
}
void ${IP}_interrupt()
{
unsigned long source = ${IP}_INT_SOURCE;
if ( source & ETH_TXB )
{
${IP}_tx_done = 1;
//erase interrupt
${IP}_INT_SOURCE |= ETH_TXB;
}
if ( source & ETH_RXB )
{
${IP}_rx_done = 1;
${IP}_rx_len = (${IP}_RXBD0L >> 16) - HDR_LEN - CRC_LEN;
//erase interrupt
${IP}_INT_SOURCE |= ETH_RXB;
}
}'
}, 'ip_gen' );