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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_c/] [jtag/] [test_rtl/] [jtag_ram_test/] [src_verilog/] [lib/] [clk_source.v] - Rev 38
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`timescale 1ns / 1ps module clk_source ( input reset_in, input clk_in, output reset_out, output clk_out ); altera_reset_synchronizer sync( .reset_in (reset_in), .clk (clk_in), .reset_out (reset_out) ); assign clk_out=clk_in; endmodule