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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [lm32/] [verilog/] [src/] [JTAGB.v] - Rev 17
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module JTAGB ( output JTCK, output JRTI1, output JRTI2, output JTDI, output JSHIFT, output JUPDATE, output JRSTN, output JCE1, output JCE2, input JTDO1, input JTDO2 ) /*synthesis syn_black_box */; endmodule