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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [mor1kx-5.0/] [rtl/] [verilog/] [mor1kx-defines.v] - Rev 48
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/* **************************************************************************** This Source Code Form is subject to the terms of the Open Hardware Description License, v. 1.0. If a copy of the OHDL was not distributed with this file, You can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt Description: mor1kx defines Copyright (C) 2012 Authors Author(s): Julius Baxter <juliusbaxter@gmail.com> ***************************************************************************** */ /* ORBIS32 opcodes - top 6 bits */ `define OR1K_INSN_WIDTH 32 `define OR1K_RD_SELECT 25:21 `define OR1K_RA_SELECT 20:16 `define OR1K_RB_SELECT 15:11 `define OR1K_IMM_WIDTH 16 `define OR1K_IMM_SELECT 15:0 `define OR1K_ALU_OPC_WIDTH 4 `define OR1K_ALU_OPC_SELECT 3:0 `define OR1K_ALU_OPC_ADD `OR1K_ALU_OPC_WIDTH'h0 `define OR1K_ALU_OPC_ADDC `OR1K_ALU_OPC_WIDTH'h1 `define OR1K_ALU_OPC_SUB `OR1K_ALU_OPC_WIDTH'h2 `define OR1K_ALU_OPC_AND `OR1K_ALU_OPC_WIDTH'h3 `define OR1K_ALU_OPC_OR `OR1K_ALU_OPC_WIDTH'h4 `define OR1K_ALU_OPC_XOR `OR1K_ALU_OPC_WIDTH'h5 `define OR1K_ALU_OPC_MUL `OR1K_ALU_OPC_WIDTH'h6 `define OR1K_ALU_OPC_RESV `OR1K_ALU_OPC_WIDTH'h7 `define OR1K_ALU_OPC_SHRT `OR1K_ALU_OPC_WIDTH'h8 `define OR1K_ALU_OPC_DIV `OR1K_ALU_OPC_WIDTH'h9 `define OR1K_ALU_OPC_DIVU `OR1K_ALU_OPC_WIDTH'ha `define OR1K_ALU_OPC_MULU `OR1K_ALU_OPC_WIDTH'hb `define OR1K_ALU_OPC_EXTBH `OR1K_ALU_OPC_WIDTH'hc `define OR1K_ALU_OPC_EXTW `OR1K_ALU_OPC_WIDTH'hd `define OR1K_ALU_OPC_CMOV `OR1K_ALU_OPC_WIDTH'he `define OR1K_ALU_OPC_FFL1 `OR1K_ALU_OPC_WIDTH'hf `define OR1K_ALU_OPC_SECONDARY_WIDTH 3 `define OR1K_ALU_OPC_SECONDARY_SELECT 8:6 `define OR1K_ALU_OPC_SECONDARY_SHRT_SLL `OR1K_ALU_OPC_SECONDARY_WIDTH'h0 `define OR1K_ALU_OPC_SECONDARY_SHRT_SRL `OR1K_ALU_OPC_SECONDARY_WIDTH'h1 `define OR1K_ALU_OPC_SECONDARY_SHRT_SRA `OR1K_ALU_OPC_SECONDARY_WIDTH'h2 `define OR1K_ALU_OPC_SECONDARY_SHRT_ROR `OR1K_ALU_OPC_SECONDARY_WIDTH'h3 `define OR1K_ALU_OPC_SECONDARY_EXTBH_EXTHS `OR1K_ALU_OPC_SECONDARY_WIDTH'h0 `define OR1K_ALU_OPC_SECONDARY_EXTW_EXTWS `OR1K_ALU_OPC_SECONDARY_WIDTH'h0 `define OR1K_ALU_OPC_SECONDARY_EXTBH_EXTBS `OR1K_ALU_OPC_SECONDARY_WIDTH'h1 `define OR1K_ALU_OPC_SECONDARY_EXTW_EXTWZ `OR1K_ALU_OPC_SECONDARY_WIDTH'h1 `define OR1K_ALU_OPC_SECONDARY_EXTBH_EXTHZ `OR1K_ALU_OPC_SECONDARY_WIDTH'h2 `define OR1K_ALU_OPC_SECONDARY_EXTBH_EXTBZ `OR1K_ALU_OPC_SECONDARY_WIDTH'h3 `define OR1K_COMP_OPC_WIDTH 4 `define OR1K_COMP_OPC_SELECT 24:21 `define OR1K_COMP_OPC_EQ `OR1K_COMP_OPC_WIDTH'h0 `define OR1K_COMP_OPC_NE `OR1K_COMP_OPC_WIDTH'h1 `define OR1K_COMP_OPC_GTU `OR1K_COMP_OPC_WIDTH'h2 `define OR1K_COMP_OPC_GEU `OR1K_COMP_OPC_WIDTH'h3 `define OR1K_COMP_OPC_LTU `OR1K_COMP_OPC_WIDTH'h4 `define OR1K_COMP_OPC_LEU `OR1K_COMP_OPC_WIDTH'h5 `define OR1K_COMP_OPC_GTS `OR1K_COMP_OPC_WIDTH'ha `define OR1K_COMP_OPC_GES `OR1K_COMP_OPC_WIDTH'hb `define OR1K_COMP_OPC_LTS `OR1K_COMP_OPC_WIDTH'hc `define OR1K_COMP_OPC_LES `OR1K_COMP_OPC_WIDTH'hd `define OR1K_JUMPBRANCH_IMMEDIATE_SELECT 25:0 `define OR1K_SYSTRAPSYNC_OPC_WIDTH 3 `define OR1K_SYSTRAPSYNC_OPC_SELECT 25:23 `define OR1K_SYSTRAPSYNC_OPC_SYSCALL `OR1K_SYSTRAPSYNC_OPC_WIDTH'h0 `define OR1K_SYSTRAPSYNC_OPC_TRAP `OR1K_SYSTRAPSYNC_OPC_WIDTH'h2 `define OR1K_SYSTRAPSYNC_OPC_MSYNC `OR1K_SYSTRAPSYNC_OPC_WIDTH'h4 `define OR1K_SYSTRAPSYNC_OPC_PSYNC `OR1K_SYSTRAPSYNC_OPC_WIDTH'h5 `define OR1K_SYSTRAPSYNC_OPC_CSYNC `OR1K_SYSTRAPSYNC_OPC_WIDTH'h6 `define OR1K_OPCODE_WIDTH 6 `define OR1K_OPCODE_SELECT 31:26 `define OR1K_OPCODE_J {2'b00, 4'h0} `define OR1K_OPCODE_JAL {2'b00, 4'h1} `define OR1K_OPCODE_BNF {2'b00, 4'h3} `define OR1K_OPCODE_BF {2'b00, 4'h4} `define OR1K_OPCODE_NOP {2'b00, 4'h5} `define OR1K_OPCODE_MOVHI {2'b00, 4'h6} `define OR1K_OPCODE_MACRC {2'b00, 4'h6} /* `define OR1K_OPCODE_SYS {2'b00, 4'h8} `define OR1K_OPCODE_TRAP {2'b00, 4'h8} `define OR1K_OPCODE_MSYNC {2'b00, 4'h8} `define OR1K_OPCODE_PSYNC {2'b00, 4'h8} `define OR1K_OPCODE_CSYNC {2'b00, 4'h8} */ `define OR1K_OPCODE_SYSTRAPSYNC {2'b00, 4'h8} `define OR1K_OPCODE_RFE {2'b00, 4'h9} `define OR1K_OPCODE_JR {2'b01, 4'h1} `define OR1K_OPCODE_JALR {2'b01, 4'h2} `define OR1K_OPCODE_MACI {2'b01, 4'h3} `define OR1K_OPCODE_LWA {2'b01, 4'hB} `define OR1K_OPCODE_CUST1 {2'b01, 4'hC} `define OR1K_OPCODE_CUST2 {2'b01, 4'hD} `define OR1K_OPCODE_CUST3 {2'b01, 4'hE} `define OR1K_OPCODE_CUST4 {2'b01, 4'hF} `define OR1K_OPCODE_LD {2'b10, 4'h0} `define OR1K_OPCODE_LWZ {2'b10, 4'h1} `define OR1K_OPCODE_LWS {2'b10, 4'h2} `define OR1K_OPCODE_LBZ {2'b10, 4'h3} `define OR1K_OPCODE_LBS {2'b10, 4'h4} `define OR1K_OPCODE_LHZ {2'b10, 4'h5} `define OR1K_OPCODE_LHS {2'b10, 4'h6} `define OR1K_OPCODE_ADDI {2'b10, 4'h7} `define OR1K_OPCODE_ADDIC {2'b10, 4'h8} `define OR1K_OPCODE_ANDI {2'b10, 4'h9} `define OR1K_OPCODE_ORI {2'b10, 4'hA} `define OR1K_OPCODE_XORI {2'b10, 4'hB} `define OR1K_OPCODE_MULI {2'b10, 4'hC} `define OR1K_OPCODE_MFSPR {2'b10, 4'hD} /* `define OR1K_OPCODE_SLLI {2'b10, 4'hE} `define OR1K_OPCODE_SRLI {2'b10, 4'hE} `define OR1K_OPCODE_SRAI {2'b10, 4'hE} `define OR1K_OPCODE_RORI {2'b10, 4'hE} */ `define OR1K_OPCODE_SHRTI {2'b10, 4'hE} /* `define OR1K_OPCODE_SFEQI {2'b10, 4'hF} `define OR1K_OPCODE_SFNEI {2'b10, 4'hF} `define OR1K_OPCODE_SFGTUI {2'b10, 4'hF} `define OR1K_OPCODE_SFGEUI {2'b10, 4'hF} `define OR1K_OPCODE_SFLTUI {2'b10, 4'hF} `define OR1K_OPCODE_SFLEUI {2'b10, 4'hF} `define OR1K_OPCODE_SFGTSI {2'b10, 4'hF} `define OR1K_OPCODE_SFGESI {2'b10, 4'hF} `define OR1K_OPCODE_SFLTSI {2'b10, 4'hF} `define OR1K_OPCODE_SFLESI {2'b10, 4'hF} */ `define OR1K_OPCODE_SFIMM {2'b10, 4'hF} `define OR1K_OPCODE_MTSPR {2'b11, 4'h0} `define OR1K_OPCODE_MAC {2'b11, 4'h1} `define OR1K_OPCODE_MSB {2'b11, 4'h1} `define OR1K_OPCODE_SWA {2'b11, 4'h3} `define OR1K_OPCODE_SD {2'b11, 4'h4} `define OR1K_OPCODE_SW {2'b11, 4'h5} `define OR1K_OPCODE_SB {2'b11, 4'h6} `define OR1K_OPCODE_SH {2'b11, 4'h7} /* `define OR1K_OPCODE_ADD {2'b11, 4'h8} `define OR1K_OPCODE_ADDC {2'b11, 4'h8} `define OR1K_OPCODE_SUB {2'b11, 4'h8} `define OR1K_OPCODE_AND {2'b11, 4'h8} `define OR1K_OPCODE_OR {2'b11, 4'h8} `define OR1K_OPCODE_XOR {2'b11, 4'h8} `define OR1K_OPCODE_MUL {2'b11, 4'h8} `define OR1K_OPCODE_SLL {2'b11, 4'h8} `define OR1K_OPCODE_SRL {2'b11, 4'h8} `define OR1K_OPCODE_SRA {2'b11, 4'h8} `define OR1K_OPCODE_ROR {2'b11, 4'h8} `define OR1K_OPCODE_DIV {2'b11, 4'h8} `define OR1K_OPCODE_DIVU {2'b11, 4'h8} `define OR1K_OPCODE_MULU {2'b11, 4'h8} `define OR1K_OPCODE_EXTBS {2'b11, 4'h8} `define OR1K_OPCODE_EXTHS {2'b11, 4'h8} `define OR1K_OPCODE_EXTWS {2'b11, 4'h8} `define OR1K_OPCODE_EXTBZ {2'b11, 4'h8} `define OR1K_OPCODE_EXTHZ {2'b11, 4'h8} `define OR1K_OPCODE_EXTWZ {2'b11, 4'h8} `define OR1K_OPCODE_CMOV {2'b11, 4'h8} `define OR1K_OPCODE_FF1 {2'b11, 4'h8} `define OR1K_OPCODE_FL1 {2'b11, 4'h8} */ `define OR1K_OPCODE_ALU {2'b11, 4'h8} /* `define OR1K_OPCODE_SFEQ {2'b11, 4'h9} `define OR1K_OPCODE_SFNE {2'b11, 4'h9} `define OR1K_OPCODE_SFGTU {2'b11, 4'h9} `define OR1K_OPCODE_SFGEU {2'b11, 4'h9} `define OR1K_OPCODE_SFLTU {2'b11, 4'h9} `define OR1K_OPCODE_SFLEU {2'b11, 4'h9} `define OR1K_OPCODE_SFGTS {2'b11, 4'h9} `define OR1K_OPCODE_SFGES {2'b11, 4'h9} `define OR1K_OPCODE_SFLTS {2'b11, 4'h9} `define OR1K_OPCODE_SFLES {2'b11, 4'h9} */ `define OR1K_OPCODE_SF {2'b11, 4'h9} `define OR1K_OPCODE_CUST5 {2'b11, 4'hC} `define OR1K_OPCODE_CUST6 {2'b11, 4'hD} `define OR1K_OPCODE_CUST7 {2'b11, 4'hE} `define OR1K_OPCODE_CUST8 {2'b11, 4'hF} // // ORFPX32 opcodes // `define OR1K_OPCODE_FPU {2'b11, 4'h2} // FP OPs // MSbit indicates FPU operation valid `define OR1K_FPUOP_WIDTH 8 `define OR1K_FPUOP_SELECT 7:0 // Select bits for Ordered/Unordered comparison `define OR1K_FPUOP_GENERIC_CMP_WIDTH 3 `define OR1K_FPUOP_GENERIC_CMP_SELECT 2:0 // Unordered comparison bit `define OR1K_FPUOP_UNORDERED_CMP_BIT 5 // FP instruction is double precision if bit 4 is set. We're a 32-bit // implementation thus do not support double precision FP `define OR1K_FPUOP_DOUBLE_BIT 4 // FP Arithmetic OPCs `define OR1K_FPUOP_ADD 8'b0000_0000 `define OR1K_FPUOP_SUB 8'b0000_0001 `define OR1K_FPUOP_MUL 8'b0000_0010 `define OR1K_FPUOP_DIV 8'b0000_0011 `define OR1K_FPUOP_ITOF 8'b0000_0100 `define OR1K_FPUOP_FTOI 8'b0000_0101 `define OR1K_FPUOP_REM 8'b0000_0110 `define OR1K_FPUOP_RESERVED 8'b0000_0111 // FP Ordered Comparison OPCs `define OR1K_FPCOP_SFEQ 8'b0000_1000 `define OR1K_FPCOP_SFNE 8'b0000_1001 `define OR1K_FPCOP_SFGT 8'b0000_1010 `define OR1K_FPCOP_SFGE 8'b0000_1011 `define OR1K_FPCOP_SFLT 8'b0000_1100 `define OR1K_FPCOP_SFLE 8'b0000_1101 // FP Unordered Comparison OPCs `define OR1K_FPCOP_SFUEQ 8'b0010_1000 `define OR1K_FPCOP_SFUNE 8'b0010_1001 `define OR1K_FPCOP_SFUGT 8'b0010_1010 `define OR1K_FPCOP_SFUGE 8'b0010_1011 `define OR1K_FPCOP_SFULT 8'b0010_1100 `define OR1K_FPCOP_SFULE 8'b0010_1101 `define OR1K_FPCOP_SFUN 8'b0010_1110 // // OR1K SPR defines // `include "mor1kx-sprs.v" /* Exception addresses */ `define OR1K_RESET_VECTOR 5'h01 `define OR1K_BERR_VECTOR 5'h02 `define OR1K_DPF_VECTOR 5'h03 `define OR1K_IPF_VECTOR 5'h04 `define OR1K_TT_VECTOR 5'h05 `define OR1K_ALIGN_VECTOR 5'h06 `define OR1K_ILLEGAL_VECTOR 5'h07 `define OR1K_INT_VECTOR 5'h08 `define OR1K_DTLB_VECTOR 5'h09 `define OR1K_ITLB_VECTOR 5'h0a `define OR1K_RANGE_VECTOR 5'h0b `define OR1K_SYSCALL_VECTOR 5'h0c `define OR1K_FP_VECTOR 5'h0d `define OR1K_TRAP_VECTOR 5'h0e // Whether we'll allow things using AYNC reset to have it: //`define OR_ASYNC_RST or posedge rst `define OR_ASYNC_RST // Implementation version defines `define MOR1KX_CPUID 8'h01 // mor1kx breaks up the VR2 version register to be 3 8-bit fields // MSB is major version, middle byte is minor version number // and final byte is the pipeline identifier. `define MOR1KX_VERSION_MAJOR 8'd5 `define MOR1KX_VERSION_MINOR 8'd0 // mor1kx implementation-specific register definitions `define MOR1KX_PIPEID_CAPPUCCINO 8'd1 `define MOR1KX_PIPEID_ESPRESSO 8'd2 `define MOR1KX_PIPEID_PRONTOESPRESSO 8'd3