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<h1>memory_registers Module Reference</h1> </div>
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<!-- doxytag: class="memory_registers" -->
<p>Contains the microcode ROM and D0-D7, A0-A7 registers.
<a href="#_details">More...</a></p>
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Inheritance diagram for memory_registers:<!-- endSectionHeader --></div>
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<p><a href="classmemory__registers-members.html">List of all members.</a></p>
<table class="memberdecls">
<tr><td colspan="2"><h2><a name="Always Constructs"></a>
Always Constructs</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a09281e3224878c570c81844785844fe0">ALWAYS_29</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classmemory__registers.html#a530f92fc2ad12c95eaaf9975ce66328d">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classmemory__registers.html#a59a623e9fc522a0198461d262518b47d">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td colspan="2"><h2><a name="Inputs"></a>
Inputs</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a530f92fc2ad12c95eaaf9975ce66328d">clock</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a59a623e9fc522a0198461d262518b47d">reset_n</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a8174a0e183d6dd13598deb339666b7d0">An_address</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a7501990dea3a36c15ab84759b7da292f">An_input</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a20bd5b67a680ceba6b956beb9fb15d53">An_write_enable</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a372678f9a4b4a1af40aee2ec0f5df2e7">Dn_address</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a110868019add533d8fe706364e05eac6">Dn_input</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#af79f52c0c27beb855e979b6c98f5f116">Dn_write_enable</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a18f2a2d414fc31a8f91c0de1b2bfe2f4">Dn_size</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a7e81aeac5571c0bebedbfaad6af7f1e3">micro_pc</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">8</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td colspan="2"><h2><a name="Outputs"></a>
Outputs</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a37b7137181cefe7ef1383b5978e6b62e">An_output</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#ae304b6533d7652732511e719aeb898f6">usp</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a6956b38010744862b4e3666f9e544dbe">Dn_output</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#ad622bf153bdda61958b631dc6c25b033">micro_data</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">87</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td colspan="2"><h2><a name="Module Instances"></a>
Module Instances</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><a class="el" href="classmemory__registers.html#a892186b1bfe856b1ddaf1d8b3a448f50">altsyncram::an_ram_inst</a> </b> </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><a class="el" href="classmemory__registers.html#a5b0f1fb5a259a06899ac6ac3b52835e0">altsyncram::dn_ram_inst</a> </b> </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><a class="el" href="classmemory__registers.html#afc54073a43b749eb1f1376c4b31cd1e3">altsyncram::micro_rom_inst</a> </b> </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td colspan="2"><h2><a name="Signals"></a>
Signals</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classmemory__registers.html#a7a4f8a1e17b638ec960a63d0713de22d">An_ram_write_enable</a> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classmemory__registers.html#a454bafa8d74c3f699f05155e2c786b64">An_ram_output</a> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classmemory__registers.html#ad26e10bd26667b9f780823058dacda1f">dn_byteena</a> </td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>Contains the microcode ROM and D0-D7, A0-A7 registers. </p>
<p>The <a class="el" href="classmemory__registers.html" title="Contains the microcode ROM and D0-D7, A0-A7 registers.">memory_registers</a> module contains:</p>
<ul>
<li>data and address registers (D0-D7, A0-A7) implemented as an on-chip RAM.</li>
<li>the microcode implemented as an on-chip ROM.</li>
</ul>
<p>Currently this module contains <em>altsyncram</em> instantiations from Altera Megafunction/LPM library. </p>
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02033">2033</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<hr/><h2>Member Function Documentation</h2>
<a class="anchor" id="a09281e3224878c570c81844785844fe0"></a><!-- doxytag: member="memory_registers::ALWAYS_29" ref="a09281e3224878c570c81844785844fe0" args="clock, reset_n" -->
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<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_29 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classmemory__registers.html#a530f92fc2ad12c95eaaf9975ce66328d">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
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<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classmemory__registers.html#a59a623e9fc522a0198461d262518b47d">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
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<code> [Always Construct]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02066">2066</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<div class="fragment"><pre class="fragment">
<a name="l02066"></a>02066 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classmemory__registers.html#a530f92fc2ad12c95eaaf9975ce66328d">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classmemory__registers.html#a59a623e9fc522a0198461d262518b47d">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l02067"></a>02067 <span class="vhdlkeyword">if</span>(<a class="code" href="classmemory__registers.html#a59a623e9fc522a0198461d262518b47d">reset_n</a> == <span class="vhdllogic">1'b0</span>) <a class="code" href="classmemory__registers.html#ae304b6533d7652732511e719aeb898f6">usp</a> <= <span class="vhdllogic">32'd0</span>;
<a name="l02068"></a>02068 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classmemory__registers.html#a8174a0e183d6dd13598deb339666b7d0">An_address</a> == <span class="vhdllogic">4'b0111</span> && <a class="code" href="classmemory__registers.html#a20bd5b67a680ceba6b956beb9fb15d53">An_write_enable</a>) <a class="code" href="classmemory__registers.html#ae304b6533d7652732511e719aeb898f6">usp</a> <= <a class="code" href="classmemory__registers.html#a7501990dea3a36c15ab84759b7da292f">An_input</a>;
<a name="l02069"></a>02069 <span class="vhdlkeyword">end</span>
</pre></div>
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</div>
<hr/><h2>Member Data Documentation</h2>
<a class="anchor" id="a530f92fc2ad12c95eaaf9975ce66328d"></a><!-- doxytag: member="memory_registers::clock" ref="a530f92fc2ad12c95eaaf9975ce66328d" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a530f92fc2ad12c95eaaf9975ce66328d">clock</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02034">2034</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a59a623e9fc522a0198461d262518b47d"></a><!-- doxytag: member="memory_registers::reset_n" ref="a59a623e9fc522a0198461d262518b47d" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a59a623e9fc522a0198461d262518b47d">reset_n</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02035">2035</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a8174a0e183d6dd13598deb339666b7d0"></a><!-- doxytag: member="memory_registers::An_address" ref="a8174a0e183d6dd13598deb339666b7d0" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a8174a0e183d6dd13598deb339666b7d0">An_address</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02038">2038</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a7501990dea3a36c15ab84759b7da292f"></a><!-- doxytag: member="memory_registers::An_input" ref="a7501990dea3a36c15ab84759b7da292f" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a7501990dea3a36c15ab84759b7da292f">An_input</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02039">2039</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a20bd5b67a680ceba6b956beb9fb15d53"></a><!-- doxytag: member="memory_registers::An_write_enable" ref="a20bd5b67a680ceba6b956beb9fb15d53" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a20bd5b67a680ceba6b956beb9fb15d53">An_write_enable</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02040">2040</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a37b7137181cefe7ef1383b5978e6b62e"></a><!-- doxytag: member="memory_registers::An_output" ref="a37b7137181cefe7ef1383b5978e6b62e" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a37b7137181cefe7ef1383b5978e6b62e">An_output</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02041">2041</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="ae304b6533d7652732511e719aeb898f6"></a><!-- doxytag: member="memory_registers::usp" ref="ae304b6533d7652732511e719aeb898f6" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#ae304b6533d7652732511e719aeb898f6">usp</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02043">2043</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a372678f9a4b4a1af40aee2ec0f5df2e7"></a><!-- doxytag: member="memory_registers::Dn_address" ref="a372678f9a4b4a1af40aee2ec0f5df2e7" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a372678f9a4b4a1af40aee2ec0f5df2e7">Dn_address</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02045">2045</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a110868019add533d8fe706364e05eac6"></a><!-- doxytag: member="memory_registers::Dn_input" ref="a110868019add533d8fe706364e05eac6" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a110868019add533d8fe706364e05eac6">Dn_input</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02046">2046</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="af79f52c0c27beb855e979b6c98f5f116"></a><!-- doxytag: member="memory_registers::Dn_write_enable" ref="af79f52c0c27beb855e979b6c98f5f116" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#af79f52c0c27beb855e979b6c98f5f116">Dn_write_enable</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02047">2047</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a18f2a2d414fc31a8f91c0de1b2bfe2f4"></a><!-- doxytag: member="memory_registers::Dn_size" ref="a18f2a2d414fc31a8f91c0de1b2bfe2f4" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a18f2a2d414fc31a8f91c0de1b2bfe2f4">Dn_size</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02049">2049</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a6956b38010744862b4e3666f9e544dbe"></a><!-- doxytag: member="memory_registers::Dn_output" ref="a6956b38010744862b4e3666f9e544dbe" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a6956b38010744862b4e3666f9e544dbe">Dn_output</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02050">2050</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a7e81aeac5571c0bebedbfaad6af7f1e3"></a><!-- doxytag: member="memory_registers::micro_pc" ref="a7e81aeac5571c0bebedbfaad6af7f1e3" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a7e81aeac5571c0bebedbfaad6af7f1e3">micro_pc</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">8</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02052">2052</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="ad622bf153bdda61958b631dc6c25b033"></a><!-- doxytag: member="memory_registers::micro_data" ref="ad622bf153bdda61958b631dc6c25b033" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#ad622bf153bdda61958b631dc6c25b033">micro_data</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">87</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02053">2053</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a7a4f8a1e17b638ec960a63d0713de22d"></a><!-- doxytag: member="memory_registers::An_ram_write_enable" ref="a7a4f8a1e17b638ec960a63d0713de22d" args="wire" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a7a4f8a1e17b638ec960a63d0713de22d">An_ram_write_enable</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02056">2056</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a454bafa8d74c3f699f05155e2c786b64"></a><!-- doxytag: member="memory_registers::An_ram_output" ref="a454bafa8d74c3f699f05155e2c786b64" args="wire[31:0]" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a454bafa8d74c3f699f05155e2c786b64">An_ram_output</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[31:0]]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02058">2058</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="ad26e10bd26667b9f780823058dacda1f"></a><!-- doxytag: member="memory_registers::dn_byteena" ref="ad26e10bd26667b9f780823058dacda1f" args="wire[3:0]" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#ad26e10bd26667b9f780823058dacda1f">dn_byteena</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[3:0]]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02061">2061</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="afc54073a43b749eb1f1376c4b31cd1e3"></a><!-- doxytag: member="memory_registers::altsyncram" ref="afc54073a43b749eb1f1376c4b31cd1e3" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#afc54073a43b749eb1f1376c4b31cd1e3">altsyncram</a></span> <b><span class="vhdlchar">micro_rom_inst</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Module Instance]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02104">2104</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a5b0f1fb5a259a06899ac6ac3b52835e0"></a><!-- doxytag: member="memory_registers::altsyncram" ref="a5b0f1fb5a259a06899ac6ac3b52835e0" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a5b0f1fb5a259a06899ac6ac3b52835e0">altsyncram</a></span> <b><span class="vhdlchar">dn_ram_inst</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Module Instance]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02088">2088</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a892186b1bfe856b1ddaf1d8b3a448f50"></a><!-- doxytag: member="memory_registers::altsyncram" ref="a892186b1bfe856b1ddaf1d8b3a448f50" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a892186b1bfe856b1ddaf1d8b3a448f50">altsyncram</a></span> <b><span class="vhdlchar">an_ram_inst</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Module Instance]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02072">2072</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<hr/>The documentation for this class was generated from the following file:<ul>
<li><a class="el" href="ao68000_8v_source.html">ao68000.v</a></li>
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<hr class="footer"/><address class="footer"><small>Generated on Sat Dec 11 2010 13:21:13 for ao68000 by 
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<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
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