URL
https://opencores.org/ocsvn/ao68000/ao68000/trunk
Subversion Repositories ao68000
[/] [ao68000/] [trunk/] [doc/] [doxygen/] [html/] [page_spec_architecture.html] - Rev 12
Go to most recent revision | Compare with Previous | Blame | View Log
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
<title>ao68000: Architecture</title>
<link href="tabs.css" rel="stylesheet" type="text/css"/>
<link href="doxygen.css" rel="stylesheet" type="text/css"/>
</head>
<body>
<!-- Generated by Doxygen 1.7.2 -->
<div class="navigation" id="top">
<div class="tabs">
<ul class="tablist">
<li><a href="index.html"><span>Main Page</span></a></li>
<li><a href="modules.html"><span>Modules</span></a></li>
<li><a href="annotated.html"><span>Design Unit List</span></a></li>
<li><a href="files.html"><span>Files</span></a></li>
</ul>
</div>
<div class="navpath">
<ul>
<li><a class="el" href="index.html">index</a> </li>
</ul>
</div>
</div>
<div class="header">
<div class="headertitle">
<h1>Architecture </h1> </div>
</div>
<div class="contents">
<table border="0" align="center">
<caption align="bottom"><b>Figure 1:</b> Simplified block diagram of <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> top module. </caption>
<tr>
<td><div align="center">
<img src="architecture.png" alt="architecture.png"/>
</div>
</td></tr>
</table>
<h3><a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a></h3>
<p><a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> top level module. </p>
<p>This module contains only instantiations of sub-modules and wire declarations. </p>
<h3><a class="el" href="classbus__control.html" title="Initiate WISHBONE MASTER bus cycles.">bus_control</a></h3>
<p>Initiate WISHBONE MASTER bus cycles. </p>
<p>The <a class="el" href="classbus__control.html" title="Initiate WISHBONE MASTER bus cycles.">bus_control</a> module is the only module that has contact with signals from outside of the IP core. It is responsible for initiating WISHBONE MASTER bus cycles. The cycles can be divided into:</p>
<ul>
<li>memory read cycles (supervisor data, supervisor program, user data, user program)</li>
<li>memory write cycles (supervisor data, user data),</li>
<li>interrupt acknowledge.</li>
</ul>
<p>Every cycle is supplemented with the following tags:</p>
<ul>
<li>standard WISHBONE cycle tags: SGL_O, BLK_O, RMW_O,</li>
<li>register feedback WISHBONE address tags: CTI_O and BTE_O,</li>
<li><a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> specific cycle tag: fc_o which is equivalent to MC68000 function codes.</li>
</ul>
<p>The <a class="el" href="classbus__control.html" title="Initiate WISHBONE MASTER bus cycles.">bus_control</a> module is also responsible for registering interrupt inputs and initiating the interrupt acknowledge cycle in response to a microcode request. Microcode requests a interrupt acknowledge at the end of instruction processing, when the interrupt privilege level is higher than the current interrupt privilege mask, as specified in the MC68000 User's Manual.</p>
<p>Finally, <a class="el" href="classbus__control.html" title="Initiate WISHBONE MASTER bus cycles.">bus_control</a> controls also two <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> specific core outputs:</p>
<ul>
<li>blocked output, high when that the processor is blocked after encountering a double bus error. The only way to leave this block state is by reseting the <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> by the asynchronous reset input signal.</li>
<li>reset output, high when processing the RESET instruction. Can be used to reset external devices. </li>
</ul>
<h3>registers</h3>
<p>Microcode controlled registers. </p>
<p>Most of the <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> IP core registers are located in this module. At every clock cycle the microcode controls what to save into these registers. Some of the more important registers include:</p>
<ul>
<li>operand1, operand2 registers are inputs to the ALU,</li>
<li>address, size, do_read_flag, do_write_flag, do_interrupt_flag registers tell the <a class="el" href="classbus__control.html" title="Initiate WISHBONE MASTER bus cycles.">bus_control</a> module what kind of bus cycle to perform,</li>
<li>pc register stores the current program counter,</li>
<li>ir register stores the current instruction word,</li>
<li>ea_mod, ea_type registers store the currently selected addressing mode. </li>
</ul>
<h3><a class="el" href="classmemory__registers.html" title="Contains the microcode ROM and D0-D7, A0-A7 registers.">memory_registers</a></h3>
<p>Contains the microcode ROM and D0-D7, A0-A7 registers. </p>
<p>The <a class="el" href="classmemory__registers.html" title="Contains the microcode ROM and D0-D7, A0-A7 registers.">memory_registers</a> module contains:</p>
<ul>
<li>data and address registers (D0-D7, A0-A7) implemented as an on-chip RAM.</li>
<li>the microcode implemented as an on-chip ROM.</li>
</ul>
<p>Currently this module contains <em>altsyncram</em> instantiations from Altera Megafunction/LPM library. </p>
<h3>decoder</h3>
<p>Decode instruction and addressing mode. </p>
<p>The decoder is an instruction and addressing mode decoder. For instructions it takes as input the ir register from the registers module. The output of the decoder, in this case, is a microcode address of the first microcode word that performs the instruction.</p>
<p>In case of addressing mode decoding, the output is the address of the first microcode word that performs the operand loading or saving. This address is obtained from the currently selected addressing mode saved in the ea_mod and ea_type registers in the registers module. </p>
<h3>condition</h3>
<p>Condition tests. </p>
<p>The condition module implements the condition tests of the MC68000. Its inputs are the condition codes and the currently selected test. The output is binary: the test is true or false. The output of the condition module is an input to the <a class="el" href="classmicrocode__branch.html" title="Select the next microcode word to execute.">microcode_branch</a> module, that decides which microcode word to execute next. </p>
<h3>alu</h3>
<p>Arithmetic and Logic Unit. </p>
<p>The alu module is responsible for performing all of the arithmetic and logic operations of the <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> processor. It operates on two 32-bit registers: operand1 and operand2 from the registers module. The output is saved into a result 32-bit register. This register is located in the alu module.</p>
<p>The alu module also contains the status register (SR) with the condition code register. The microcode decides what operation the alu performs. </p>
<h3><a class="el" href="classmicrocode__branch.html" title="Select the next microcode word to execute.">microcode_branch</a></h3>
<p>Select the next microcode word to execute. </p>
<p>The <a class="el" href="classmicrocode__branch.html" title="Select the next microcode word to execute.">microcode_branch</a> module is responsible for selecting the next microcode word to execute. This decision is based on the value of the current microcode word, the value of the interrupt privilege level, the state of the current bus cycle and other internal signals.</p>
<p>The <a class="el" href="classmicrocode__branch.html" title="Select the next microcode word to execute.">microcode_branch</a> module implements a simple stack for the microcode addresses. This makes it possible to call subroutines inside the microcode. </p>
</div>
<hr class="footer"/><address class="footer"><small>Generated on Sat Dec 11 2010 13:21:12 for ao68000 by 
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
</body>
</html>
Go to most recent revision | Compare with Previous | Blame | View Log