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<h1>IO Ports </h1> </div>
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<h3>WISHBONE IO Ports</h3>
<table width="100%">
<caption align="bottom"><b>Table 1:</b> List of WISHBONE IO ports.</caption>
<tr style="background: #CCCCCC; font-weight: bold;">
<td>Port </td><td>Width </td><td>Direction </td><td>Description </td></tr>
<tr>
<td>CLK_I </td><td>1 </td><td>Input </td><td><p>WISHBONE Clock Input </p>
</td></tr>
<tr>
<td>reset_n </td><td>1 </td><td>Input </td><td><p>Asynchronous Reset Input </p>
</td></tr>
<tr>
<td>CYC_O </td><td>1 </td><td>Output </td><td><p>WISHBONE Master Cycle Output </p>
</td></tr>
<tr>
<td>ADR_O </td><td>30 </td><td>Output </td><td><p>WISHBONE Master Address Output </p>
</td></tr>
<tr>
<td>DAT_O </td><td>32 </td><td>Output </td><td><p>WISHBONE Master Data Output </p>
</td></tr>
<tr>
<td>DAT_I </td><td>32 </td><td>Input </td><td><p>WISHBONE Master Data Input </p>
</td></tr>
<tr>
<td>SEL_O </td><td>4 </td><td>Output </td><td><p>WISHBONE Master Byte Select </p>
</td></tr>
<tr>
<td>STB_O </td><td>1 </td><td>Output </td><td><p>WISHBONE Master Strobe Output </p>
</td></tr>
<tr>
<td>WE_O </td><td>1 </td><td>Output </td><td><p>WISHBONE Master Write Enable Output </p>
</td></tr>
<tr>
<td>ACK_I </td><td>1 </td><td>Input </td><td><p>WISHBONE Master Acknowledge Input:</p>
<ul>
<li>on normal cycle: acknowledge,</li>
<li>on interrupt acknowledge cycle: external vector provided on DAT_I[7:0]. </li>
</ul>
</td></tr>
<tr>
<td>ERR_I </td><td>1 </td><td>Input </td><td><p>WISHBONE Master Error Input</p>
<ul>
<li>on normal cycle: bus error,</li>
<li>on interrupt acknowledge cycle: spurious interrupt. </li>
</ul>
</td></tr>
<tr>
<td>RTY_I </td><td>1 </td><td>Input </td><td><p>WISHBONE Master Retry Input</p>
<ul>
<li>on normal cycle: retry bus cycle,</li>
<li>on interrupt acknowledge: use auto-vector. </li>
</ul>
</td></tr>
<tr>
<td>SGL_O </td><td>1 </td><td>Output </td><td><p>WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Single Bus Cycle. </p>
</td></tr>
<tr>
<td>BLK_O </td><td>1 </td><td>Output </td><td><p>WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Block Bus Cycle. </p>
</td></tr>
<tr>
<td>RMW_O </td><td>1 </td><td>Output </td><td><p>WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Read-Modify-Write Cycle. </p>
</td></tr>
<tr>
<td>CTI_O </td><td>3 </td><td>Output </td><td><p>WISHBONE Address Tag, TAG_TYPE: TGA_O, Cycle Type Identifier, Incrementing Bus Cycle or End-of-Burst Cycle. </p>
</td></tr>
<tr>
<td>BTE_O </td><td>2 </td><td>Output </td><td><p>WISHBONE Address Tag, TAG_TYPE: TGA_O, Burst Type Extension, always Linear Burst. </p>
</td></tr>
<tr>
<td>fc_o </td><td>3 </td><td>Output </td><td><p>Custom TAG_TYPE: TGC_O, Cycle Tag, Processor Function Code:</p>
<ul>
<li>1 - user data,</li>
<li>2 - user program,</li>
<li>5 - supervisor data : all exception vector entries except reset,</li>
<li>6 - supervisor program : exception vector for reset,</li>
<li>7 - cpu space: interrupt acknowledge. </li>
</ul>
</td></tr>
</table>
<h3>Other IO Ports</h3>
<table width="100%">
<caption align="bottom"><b>Table 2:</b> List of Other IO ports.</caption>
<tr style="background: #CCCCCC; font-weight: bold;">
<td>Port </td><td>Width </td><td>Direction </td><td>Description </td></tr>
<tr>
<td>ipl_i </td><td>3 </td><td>Input </td><td><p>Interrupt Priority Level Interrupt acknowledge cycle:</p>
<ul>
<li>ACK_I: interrupt vector on DAT_I[7:0],</li>
<li>ERR_I: spurious interrupt,</li>
<li>RTY_I: auto-vector. </li>
</ul>
</td></tr>
<tr>
<td>reset_o </td><td>1 </td><td>Output </td><td><p>External device reset. Output high when processing the RESET instruction. </p>
</td></tr>
<tr>
<td>blocked_o</td><td>1 </td><td>Output </td><td><p>Processor blocked indicator. The processor is blocked after a double bus error. </p>
</td></tr>
</table>
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