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<h1>ocs_control Module Reference</h1>  </div>
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<p><p>OCS system control implementation with WISHBONE slave interface. </p>
 
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Always Constructs</h2></td></tr>
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Inputs</h2></td></tr>
 <tr><td colspan="2"><div class="groupHeader">Clock and reset</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a78eebaf1d7122debfc56eebb02678f7c">clk_30</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td colspan="2"><div class="groupHeader">WISHBONE slave</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a2b96a7c9eef58084d7c25b4cda2c4ed8">CYC_I</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Not aligned register access on a 32-bit WISHBONE bus</div></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Internal OCS ports: global registers and blitter signals</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a02b5f619bee718ffca6c320ab96bda12">blitter_busy</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Internal OCS ports: interrupts</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#ae645835ecd291e80d3f61ec700e0ef83">blitter_irq</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a0c63e4bdbce5abb540b08a7e92f212a6">cia_a_irq</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#aec4f636beb542cf2eba96883a664a736">audio_irq</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
<tr><td colspan="2"><h2><a name="Outputs"></a>
Outputs</h2></td></tr>
 <tr><td colspan="2"><div class="groupHeader">WISHBONE slave</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a4c36d95eefa6d567b8b4e8d476cd3a96">slave_DAT_O</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td colspan="2"><div class="groupHeader">Not aligned register access on a 32-bit WISHBONE bus</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a0e6ee6c6aa45013963dd74c65dc37bc6">na_pot0dat_read</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td colspan="2"><div class="groupHeader">Internal OCS ports: beam counters</div></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Internal OCS ports: clock pulses for CIA and audio</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a0197eedf5b87ff26b0b2035e18b8c1c1">pulse_709379_hz</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b>  </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#ac0fa0cd71802281503990be9fd87f900">pulse_color</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td colspan="2"><div class="groupHeader">Internal OCS ports: global registers and blitter signals</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a2ef3aff81fd20f8ae91d3e66c046fffe">dma_con</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">10</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#ad1c254c7e4551d7f373b552e40652f5f">adk_con</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">14</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
<tr><td colspan="2"><div class="groupHeader">Internal OCS ports: interrupts</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#aa8d13b23544f041f1f633c8237e0ad03">interrupt</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
<tr><td colspan="2"><h2><a name="Signals"></a>
Signals</h2></td></tr>
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</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>OCS system control implementation with WISHBONE slave interface. </p>
 <p>List of system control registers: </p>
<div class="fragment"><pre class="fragment">
Implemented:
     [DDFSTOP      094  W   A     Display bitplane data fetch stop              
                                  (horiz. position)                             write not implemented here]
    DMACON       096  W   ADP     DMA control write (clear or set)              write not implemented here
 
    DMACONR     *002  R   AP      DMA control (and blitter status) read
    VPOSR       *004  R   A( E )  Read vert most signif. bit (and frame flop)
    VHPOSR      *006  R   A       Read vert and horiz. position of beam
 
    ADKCON       09E  W   P       Audio, disk, UART control
 
    ADKCONR     *010  R   P       Audio, disk control register read
     [POT0DAT   *012  R   P( E )  Pot counter pair 0 data (vert,horiz)          read implemented here]
 
    INTENAR     *01C  R   P       Interrupt enable bits read
    INTREQR     *01E  R   P       Interrupt request bits read
 
     [CLXCON     098  W   D       Collision control                             write not implemented here]
    INTENA       09A  W   P       Interrupt enable bits (clear or set bits)     write not implemented here
    INTREQ       09C  W   P       Interrupt request bits (clear or set bits)
 
Not implemented:
    REFPTR    &amp; *028  W   A       Refresh pointer                               
    VPOSW       *02A  W   A       Write vert most signif. bit (and frame flop)  
    VHPOSW      *02C  W   A       Write vert and horiz position of beam
 
    STREQU    &amp; *038  S   D       Strobe for horiz sync with VB and EQU
    STRVBL    &amp; *03A  S   D       Strobe for horiz sync with VB (vert. blank)
    STRHOR    &amp; *03C  S   DP      Strobe for horiz sync
    STRLONG   &amp; *03E  S   D( E )  Strobe for identification of long horiz. line.
 
    RESERVED     1110X
    RESERVED     1111X
    NO-OP(NULL)  1FE
</pre></div> 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00069">69</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
<hr/><h2>Member Function Documentation</h2>
<a class="anchor" id="a941900ef0da9240ac0c4925bcc5c72b0"></a><!-- doxytag: member="ocs_control::ALWAYS_40" ref="a941900ef0da9240ac0c4925bcc5c72b0" args="clk_30, reset_n" -->
<div class="memitem">
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      <table class="memname">
        <tr>
          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_40          <td></td>
          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classocs__control.html#a78eebaf1d7122debfc56eebb02678f7c">clk_30</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classocs__control.html#a246ab8bc07755c51fdd905891ec461e7">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
        </tr>
<code> [Always Construct]</code></td>
        </tr>
      </table>
</div>
<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00182">182</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
</div>
<a class="anchor" id="a457e5455cd5940e951513a66fcb55270"></a><!-- doxytag: member="ocs_control::ALWAYS_41" ref="a457e5455cd5940e951513a66fcb55270" args="clk_30, reset_n" -->
<div class="memitem">
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      <table class="memname">
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          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_41          <td></td>
          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classocs__control.html#a78eebaf1d7122debfc56eebb02678f7c">clk_30</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classocs__control.html#a246ab8bc07755c51fdd905891ec461e7">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
        </tr>
<code> [Always Construct]</code></td>
        </tr>
      </table>
</div>
<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00272">272</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
</div>
<a class="anchor" id="a896ae4138df87842bae2e3beddb07953"></a><!-- doxytag: member="ocs_control::ALWAYS_42" ref="a896ae4138df87842bae2e3beddb07953" args="clk_30, reset_n" -->
<div class="memitem">
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      <table class="memname">
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          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_42          <td></td>
          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classocs__control.html#a78eebaf1d7122debfc56eebb02678f7c">clk_30</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classocs__control.html#a246ab8bc07755c51fdd905891ec461e7">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
        </tr>
<code> [Always Construct]</code></td>
        </tr>
      </table>
</div>
<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00297">297</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
</div>
<a class="anchor" id="a42a3550bb1bca3965ecb62d3653ed6b6"></a><!-- doxytag: member="ocs_control::ALWAYS_43" ref="a42a3550bb1bca3965ecb62d3653ed6b6" args="clk_30, reset_n" -->
<div class="memitem">
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      <table class="memname">
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          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_43          <td></td>
          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classocs__control.html#a78eebaf1d7122debfc56eebb02678f7c">clk_30</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classocs__control.html#a246ab8bc07755c51fdd905891ec461e7">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
        </tr>
<code> [Always Construct]</code></td>
        </tr>
      </table>
</div>
<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00306">306</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
</div>
<hr/><h2>Member Data Documentation</h2>
<a class="anchor" id="a78eebaf1d7122debfc56eebb02678f7c"></a><!-- doxytag: member="ocs_control::clk_30" ref="a78eebaf1d7122debfc56eebb02678f7c" args="" -->
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      <table class="memname">
        <tr>
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a78eebaf1d7122debfc56eebb02678f7c">clk_30</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
        </tr>
      </table>
</div>
<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00072">72</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
</div>
<a class="anchor" id="a246ab8bc07755c51fdd905891ec461e7"></a><!-- doxytag: member="ocs_control::reset_n" ref="a246ab8bc07755c51fdd905891ec461e7" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a246ab8bc07755c51fdd905891ec461e7">reset_n</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
        </tr>
      </table>
</div>
<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00073">73</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
</div>
<a class="anchor" id="a2b96a7c9eef58084d7c25b4cda2c4ed8"></a><!-- doxytag: member="ocs_control::CYC_I" ref="a2b96a7c9eef58084d7c25b4cda2c4ed8" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a2b96a7c9eef58084d7c25b4cda2c4ed8">CYC_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
        </tr>
      </table>
</div>
<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00078">78</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
</div>
<a class="anchor" id="a26071b95b282cb6ff3aac96128f0737a"></a><!-- doxytag: member="ocs_control::STB_I" ref="a26071b95b282cb6ff3aac96128f0737a" args="" -->
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      <table class="memname">
        <tr>
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a26071b95b282cb6ff3aac96128f0737a">STB_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
        </tr>
      </table>
</div>
<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00079">79</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
</div>
<a class="anchor" id="ac7648944e0726e364b9509f1a0b81c12"></a><!-- doxytag: member="ocs_control::WE_I" ref="ac7648944e0726e364b9509f1a0b81c12" args="" -->
<div class="memitem">
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      <table class="memname">
        <tr>
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#ac7648944e0726e364b9509f1a0b81c12">WE_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
        </tr>
      </table>
</div>
<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00080">80</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
</div>
<a class="anchor" id="a5287d0f0371bd2793e15feb3e1871bbd"></a><!-- doxytag: member="ocs_control::ADR_I" ref="a5287d0f0371bd2793e15feb3e1871bbd" args="" -->
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<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a5287d0f0371bd2793e15feb3e1871bbd">ADR_I</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">8</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
        </tr>
      </table>
</div>
<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00081">81</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
</div>
<a class="anchor" id="a6eb7afa02ef30b83f4553c2710cb219d"></a><!-- doxytag: member="ocs_control::SEL_I" ref="a6eb7afa02ef30b83f4553c2710cb219d" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a6eb7afa02ef30b83f4553c2710cb219d">SEL_I</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
        </tr>
      </table>
</div>
<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00082">82</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
</div>
<a class="anchor" id="a8a577d05f486a2b93a18f90ae5a08646"></a><!-- doxytag: member="ocs_control::slave_DAT_I" ref="a8a577d05f486a2b93a18f90ae5a08646" args="" -->
<div class="memitem">
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      <table class="memname">
        <tr>
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a8a577d05f486a2b93a18f90ae5a08646">slave_DAT_I</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
        </tr>
      </table>
</div>
<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00083">83</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
</div>
<a class="anchor" id="a4c36d95eefa6d567b8b4e8d476cd3a96"></a><!-- doxytag: member="ocs_control::slave_DAT_O" ref="a4c36d95eefa6d567b8b4e8d476cd3a96" args="" -->
<div class="memitem">
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      <table class="memname">
        <tr>
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a4c36d95eefa6d567b8b4e8d476cd3a96">slave_DAT_O</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
        </tr>
      </table>
</div>
<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00084">84</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
</div>
<a class="anchor" id="a8f9ec718b2729125a55d8befe1f27435"></a><!-- doxytag: member="ocs_control::ACK_O" ref="a8f9ec718b2729125a55d8befe1f27435" args="" -->
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      <table class="memname">
        <tr>
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a8f9ec718b2729125a55d8befe1f27435">ACK_O</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
        </tr>
      </table>
</div>
<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00085">85</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
</div>
<a class="anchor" id="a0dcd453ed628f5b00f790f2ab89803db"></a><!-- doxytag: member="ocs_control::na_int_ena_write" ref="a0dcd453ed628f5b00f790f2ab89803db" args="" -->
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      <table class="memname">
        <tr>
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a0dcd453ed628f5b00f790f2ab89803db">na_int_ena_write</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
        </tr>
      </table>
</div>
<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00091">91</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
</div>
<a class="anchor" id="aa45b061fb9026b2d2ea62770ba1516af"></a><!-- doxytag: member="ocs_control::na_int_ena" ref="aa45b061fb9026b2d2ea62770ba1516af" args="" -->
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      <table class="memname">
        <tr>
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#aa45b061fb9026b2d2ea62770ba1516af">na_int_ena</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
        </tr>
      </table>
</div>
<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00092">92</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
</div>
<a class="anchor" id="ab60aa15fd32a27bc713a6e03259b8b9c"></a><!-- doxytag: member="ocs_control::na_int_ena_sel" ref="ab60aa15fd32a27bc713a6e03259b8b9c" args="" -->
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      <table class="memname">
        <tr>
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#ab60aa15fd32a27bc713a6e03259b8b9c">na_int_ena_sel</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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      </table>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00093">93</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
</div>
<a class="anchor" id="a8672e719439586f796599c61a9edf765"></a><!-- doxytag: member="ocs_control::na_dma_con_write" ref="a8672e719439586f796599c61a9edf765" args="" -->
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      <table class="memname">
        <tr>
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a8672e719439586f796599c61a9edf765">na_dma_con_write</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
        </tr>
      </table>
</div>
<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00095">95</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
</div>
<a class="anchor" id="a253a44d8f5bba8b2a5a1988e73059626"></a><!-- doxytag: member="ocs_control::na_dma_con" ref="a253a44d8f5bba8b2a5a1988e73059626" args="" -->
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        <tr>
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a253a44d8f5bba8b2a5a1988e73059626">na_dma_con</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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      </table>
</div>
<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00096">96</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
</div>
<a class="anchor" id="abf6f4b5c6a572ec5a8a35f4d20485566"></a><!-- doxytag: member="ocs_control::na_dma_con_sel" ref="abf6f4b5c6a572ec5a8a35f4d20485566" args="" -->
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      <table class="memname">
        <tr>
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#abf6f4b5c6a572ec5a8a35f4d20485566">na_dma_con_sel</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00097">97</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
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<a class="anchor" id="a0e6ee6c6aa45013963dd74c65dc37bc6"></a><!-- doxytag: member="ocs_control::na_pot0dat_read" ref="a0e6ee6c6aa45013963dd74c65dc37bc6" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a0e6ee6c6aa45013963dd74c65dc37bc6">na_pot0dat_read</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00099">99</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
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<a class="anchor" id="aa0f199c211813332f0988a4b8a6a3a02"></a><!-- doxytag: member="ocs_control::na_pot0dat" ref="aa0f199c211813332f0988a4b8a6a3a02" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#aa0f199c211813332f0988a4b8a6a3a02">na_pot0dat</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00100">100</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
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<a class="anchor" id="af98b6d9d326d8dd116b3b7969a720247"></a><!-- doxytag: member="ocs_control::line_start" ref="af98b6d9d326d8dd116b3b7969a720247" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#af98b6d9d326d8dd116b3b7969a720247">line_start</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00105">105</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
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<a class="anchor" id="ada98b4d5917ec047013fdc76570c6a8e"></a><!-- doxytag: member="ocs_control::line_pre_start" ref="ada98b4d5917ec047013fdc76570c6a8e" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#ada98b4d5917ec047013fdc76570c6a8e">line_pre_start</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00106">106</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
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<a class="anchor" id="a4550e00911796d007466de7625bd0b2a"></a><!-- doxytag: member="ocs_control::line_number" ref="a4550e00911796d007466de7625bd0b2a" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a4550e00911796d007466de7625bd0b2a">line_number</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">8</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00107">107</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
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<a class="anchor" id="a91b282041c78283ad2fd1a333cf3fdc4"></a><!-- doxytag: member="ocs_control::column_number" ref="a91b282041c78283ad2fd1a333cf3fdc4" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a91b282041c78283ad2fd1a333cf3fdc4">column_number</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">8</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00108">108</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
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<a class="anchor" id="a0197eedf5b87ff26b0b2035e18b8c1c1"></a><!-- doxytag: member="ocs_control::pulse_709379_hz" ref="a0197eedf5b87ff26b0b2035e18b8c1c1" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a0197eedf5b87ff26b0b2035e18b8c1c1">pulse_709379_hz</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00113">113</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
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<a class="anchor" id="ac0fa0cd71802281503990be9fd87f900"></a><!-- doxytag: member="ocs_control::pulse_color" ref="ac0fa0cd71802281503990be9fd87f900" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#ac0fa0cd71802281503990be9fd87f900">pulse_color</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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      </table>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00114">114</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
</div>
<a class="anchor" id="a2ef3aff81fd20f8ae91d3e66c046fffe"></a><!-- doxytag: member="ocs_control::dma_con" ref="a2ef3aff81fd20f8ae91d3e66c046fffe" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a2ef3aff81fd20f8ae91d3e66c046fffe">dma_con</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">10</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00119">119</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
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<a class="anchor" id="ad1c254c7e4551d7f373b552e40652f5f"></a><!-- doxytag: member="ocs_control::adk_con" ref="ad1c254c7e4551d7f373b552e40652f5f" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#ad1c254c7e4551d7f373b552e40652f5f">adk_con</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">14</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00120">120</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
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<a class="anchor" id="a02b5f619bee718ffca6c320ab96bda12"></a><!-- doxytag: member="ocs_control::blitter_busy" ref="a02b5f619bee718ffca6c320ab96bda12" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a02b5f619bee718ffca6c320ab96bda12">blitter_busy</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00122">122</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
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<a class="anchor" id="aa7ea7fc799ab33140366bd1015496a8d"></a><!-- doxytag: member="ocs_control::blitter_zero" ref="aa7ea7fc799ab33140366bd1015496a8d" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#aa7ea7fc799ab33140366bd1015496a8d">blitter_zero</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00123">123</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
</div>
<a class="anchor" id="ae645835ecd291e80d3f61ec700e0ef83"></a><!-- doxytag: member="ocs_control::blitter_irq" ref="ae645835ecd291e80d3f61ec700e0ef83" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#ae645835ecd291e80d3f61ec700e0ef83">blitter_irq</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00128">128</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
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</div>
<a class="anchor" id="a0c63e4bdbce5abb540b08a7e92f212a6"></a><!-- doxytag: member="ocs_control::cia_a_irq" ref="a0c63e4bdbce5abb540b08a7e92f212a6" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a0c63e4bdbce5abb540b08a7e92f212a6">cia_a_irq</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00129">129</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
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<a class="anchor" id="afe3687249cafab6be582a087418a3398"></a><!-- doxytag: member="ocs_control::cia_b_irq" ref="afe3687249cafab6be582a087418a3398" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#afe3687249cafab6be582a087418a3398">cia_b_irq</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00130">130</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
</div>
<a class="anchor" id="a16bb90760ecef8bb189641ef3966630d"></a><!-- doxytag: member="ocs_control::floppy_syn_irq" ref="a16bb90760ecef8bb189641ef3966630d" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a16bb90760ecef8bb189641ef3966630d">floppy_syn_irq</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00131">131</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
</div>
<a class="anchor" id="a09d4c03109cf00edd231085ce18ab92c"></a><!-- doxytag: member="ocs_control::floppy_blk_irq" ref="a09d4c03109cf00edd231085ce18ab92c" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a09d4c03109cf00edd231085ce18ab92c">floppy_blk_irq</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00132">132</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
</div>
<a class="anchor" id="a5ec8650f5638dbfa0f0672a36fad69db"></a><!-- doxytag: member="ocs_control::serial_rbf_irq" ref="a5ec8650f5638dbfa0f0672a36fad69db" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a5ec8650f5638dbfa0f0672a36fad69db">serial_rbf_irq</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00133">133</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
</div>
<a class="anchor" id="a6ed777016a820616ed38f063c8578317"></a><!-- doxytag: member="ocs_control::serial_tbe_irq" ref="a6ed777016a820616ed38f063c8578317" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a6ed777016a820616ed38f063c8578317">serial_tbe_irq</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00134">134</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
</div>
<a class="anchor" id="aec4f636beb542cf2eba96883a664a736"></a><!-- doxytag: member="ocs_control::audio_irq" ref="aec4f636beb542cf2eba96883a664a736" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#aec4f636beb542cf2eba96883a664a736">audio_irq</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00135">135</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
</div>
<a class="anchor" id="aa8d13b23544f041f1f633c8237e0ad03"></a><!-- doxytag: member="ocs_control::interrupt" ref="aa8d13b23544f041f1f633c8237e0ad03" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#aa8d13b23544f041f1f633c8237e0ad03">interrupt</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00137">137</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
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</div>
<a class="anchor" id="a50bcd8b53c850440d22c18a40f5a3255"></a><!-- doxytag: member="ocs_control::new_int_req" ref="a50bcd8b53c850440d22c18a40f5a3255" args="wire[14:0]" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a50bcd8b53c850440d22c18a40f5a3255">new_int_req</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[14:0]]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00159">159</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
</div>
<a class="anchor" id="a3525e0a8a3eada445af773a732dd0469"></a><!-- doxytag: member="ocs_control::int_ena" ref="a3525e0a8a3eada445af773a732dd0469" args="reg[14:0]" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a3525e0a8a3eada445af773a732dd0469">int_ena</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg[14:0]]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00175">175</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
</div>
<a class="anchor" id="a37d5b61b43de582a29e66d99937762db"></a><!-- doxytag: member="ocs_control::int_req" ref="a37d5b61b43de582a29e66d99937762db" args="reg[14:0]" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a37d5b61b43de582a29e66d99937762db">int_req</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg[14:0]]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00176">176</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
 
</div>
</div>
<a class="anchor" id="a30b9ec3d0a2504a8d4ce0c4f38bbe122"></a><!-- doxytag: member="ocs_control::column_counter" ref="a30b9ec3d0a2504a8d4ce0c4f38bbe122" args="reg[10:0]" -->
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<hr/>The documentation for this class was generated from the following file:<ul>
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