Subversion Repositories async_sdm_noc

// Verilog model for ibctl 
// Generated by petrify 4.2 (compiled 15-Oct-03 at 3:06 PM)
// CPU time for synthesis (host <unknown>): 0.07 seconds
// Estimated area = 8.00
 
// The circuit is self-resetting and does not need reset pin.
 
module ibctl_net (
    dec,
    do,
    doa,
    eof,
    dia,
    eofa,
    deca
);
 
input dec;
input do;
input doa;
input eof;
 
output dia;
output eofa;
output deca;
 
 
// Functions not mapped into library gates:
// ----------------------------------------
 
// Equation: dia = eof + do
or _U0 (dia, do, eof);
 
// Equation: eofa = eof' eofa + doa'
not _U1 (_X0, doa);
not _U2 (_X1, eof);
and _U3 (_X2, _X1, eofa);
or _U4 (eofa, _X0, _X2);
 
// Equation: deca = eof' eofa + doa'
not _U5 (_X3, doa);
not _U6 (_X4, eof);
and _U7 (_X5, _X4, eofa);
or _U8 (deca, _X3, _X5);
 
 
// signal values at the initial state:
//     !dec !do !doa !eof !dia eofa deca
endmodule