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--------------------------------------------------------------------------------
Release 11.1 Trace  (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.

C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise
C:/EDAptability/coremultiplier/reference/avr/ise/ise_s3_cm2_one_syneda/ise_s3_cm2_one_syneda/ise_s3_cm2_one_syneda.ise
-intstyle ise -v 3 -s 4 -fastpaths -xml avr_core_cm2_top.twx
avr_core_cm2_top.ncd -o avr_core_cm2_top.twr avr_core_cm2_top.pcf -ucf
avr_core_cm2_top.ucf

Design file:              avr_core_cm2_top.ncd
Physical constraint file: avr_core_cm2_top.pcf
Device,package,speed:     xc3s200a,fg320,-4 (PRODUCTION 1.41 2009-03-03)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: TS_cp2 = PERIOD TIMEGRP "cp2" 14 ns HIGH 50%;

 593372 paths analyzed, 2656 endpoints analyzed, 23 failing endpoints
 23 timing errors detected. (23 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is  14.933ns.
--------------------------------------------------------------------------------
Slack (setup path):     -0.933ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nirq_st0 (FF)
  Destination:          AVR_Core_cm2_Inst/ALU_Inst/swap_out_cml_1_4 (FF)
  Requirement:          14.000ns
  Data Path Delay:      14.763ns (Levels of Logic = 11)
  Clock Path Skew:      -0.170ns (0.544 - 0.714)
  Source Clock:         cp2_BUFGP rising at 0.000ns
  Destination Clock:    cp2_BUFGP rising at 14.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nirq_st0 to AVR_Core_cm2_Inst/ALU_Inst/swap_out_cml_1_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X25Y36.YQ      Tcko                  0.580   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nirq_st0
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nirq_st0
    SLICE_X23Y31.F4      net (fanout=2)        0.900   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nirq_st0
    SLICE_X23Y31.COUT    Topcyf                1.195   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_lut<2>
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<2>
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
    SLICE_X21Y24.F3      net (fanout=6)        1.145   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
    SLICE_X21Y24.X       Tilo                  0.643   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<5>1
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<5>1_1
    SLICE_X20Y24.G3      net (fanout=9)        0.146   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<5>1
    SLICE_X20Y24.Y       Tilo                  0.707   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/N72
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/idc_cbi_cmp_eq0000111
    SLICE_X20Y24.F4      net (fanout=3)        0.097   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/N178
    SLICE_X20Y24.X       Tilo                  0.692   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/N72
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/idc_ret_cmp_eq000011
    SLICE_X21Y25.G4      net (fanout=5)        0.080   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/N72
    SLICE_X21Y25.Y       Tilo                  0.648   AVR_Core_cm2_Inst/ALU_Inst/idc_adiw_cml_1
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/reg_rd_adr_int_or00011
    SLICE_X20Y20.G1      net (fanout=11)       0.625   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/idc_adiw_cmp_eq00001
    SLICE_X20Y20.Y       Tilo                  0.707   AVR_Core_cm2_Inst/GPRF_Inst/reg_rd_adr_cml_1<4>
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/reg_rd_adr<4>66
    SLICE_X16Y19.G4      net (fanout=18)       0.997   AVR_Core_cm2_Inst/reg_rd_adr<4>
    SLICE_X16Y19.Y       Tilo                  0.707   AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31<7>215
                                                       AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31_int<0>1141
    SLICE_X14Y10.G3      net (fanout=64)       1.287   AVR_Core_cm2_Inst/GPRF_Inst/N209
    SLICE_X14Y10.Y       Tilo                  0.707   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/dbusout_0_or0003122
                                                       AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31<0>77_SW0
    SLICE_X14Y11.G4      net (fanout=1)        0.106   N423
    SLICE_X14Y11.Y       Tilo                  0.707   AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31<0>105
                                                       AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31<0>83
    SLICE_X14Y11.F3      net (fanout=1)        0.043   AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31<0>83/O
    SLICE_X14Y11.X       Tilo                  0.692   AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31<0>105
                                                       AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31<0>105
    SLICE_X15Y17.G2      net (fanout=1)        0.625   AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31<0>105
    SLICE_X15Y17.CLK     Tgck                  0.727   AVR_Core_cm2_Inst/ALU_Inst/swap_out_cml_1<5>
                                                       AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31<0>282
                                                       AVR_Core_cm2_Inst/ALU_Inst/swap_out_cml_1_4
    -------------------------------------------------  ---------------------------
    Total                                     14.763ns (8.712ns logic, 6.051ns route)
                                                       (59.0% logic, 41.0% route)

--------------------------------------------------------------------------------
Slack (setup path):     -0.933ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nreti_st0 (FF)
  Destination:          AVR_Core_cm2_Inst/ALU_Inst/swap_out_cml_1_4 (FF)
  Requirement:          14.000ns
  Data Path Delay:      14.715ns (Levels of Logic = 11)
  Clock Path Skew:      -0.218ns (0.544 - 0.762)
  Source Clock:         cp2_BUFGP rising at 0.000ns
  Destination Clock:    cp2_BUFGP rising at 14.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nreti_st0 to AVR_Core_cm2_Inst/ALU_Inst/swap_out_cml_1_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X22Y32.YQ      Tcko                  0.676   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/reti_st3
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nreti_st0
    SLICE_X23Y31.G3      net (fanout=2)        0.773   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nreti_st0
    SLICE_X23Y31.COUT    Topcyg                1.178   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_lut<3>
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
    SLICE_X21Y24.F3      net (fanout=6)        1.145   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
    SLICE_X21Y24.X       Tilo                  0.643   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<5>1
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<5>1_1
    SLICE_X20Y24.G3      net (fanout=9)        0.146   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<5>1
    SLICE_X20Y24.Y       Tilo                  0.707   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/N72
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/idc_cbi_cmp_eq0000111
    SLICE_X20Y24.F4      net (fanout=3)        0.097   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/N178
    SLICE_X20Y24.X       Tilo                  0.692   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/N72
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/idc_ret_cmp_eq000011
    SLICE_X21Y25.G4      net (fanout=5)        0.080   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/N72
    SLICE_X21Y25.Y       Tilo                  0.648   AVR_Core_cm2_Inst/ALU_Inst/idc_adiw_cml_1
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/reg_rd_adr_int_or00011
    SLICE_X20Y20.G1      net (fanout=11)       0.625   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/idc_adiw_cmp_eq00001
    SLICE_X20Y20.Y       Tilo                  0.707   AVR_Core_cm2_Inst/GPRF_Inst/reg_rd_adr_cml_1<4>
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/reg_rd_adr<4>66
    SLICE_X16Y19.G4      net (fanout=18)       0.997   AVR_Core_cm2_Inst/reg_rd_adr<4>
    SLICE_X16Y19.Y       Tilo                  0.707   AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31<7>215
                                                       AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31_int<0>1141
    SLICE_X14Y10.G3      net (fanout=64)       1.287   AVR_Core_cm2_Inst/GPRF_Inst/N209
    SLICE_X14Y10.Y       Tilo                  0.707   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/dbusout_0_or0003122
                                                       AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31<0>77_SW0
    SLICE_X14Y11.G4      net (fanout=1)        0.106   N423
    SLICE_X14Y11.Y       Tilo                  0.707   AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31<0>105
                                                       AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31<0>83
    SLICE_X14Y11.F3      net (fanout=1)        0.043   AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31<0>83/O
    SLICE_X14Y11.X       Tilo                  0.692   AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31<0>105
                                                       AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31<0>105
    SLICE_X15Y17.G2      net (fanout=1)        0.625   AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31<0>105
    SLICE_X15Y17.CLK     Tgck                  0.727   AVR_Core_cm2_Inst/ALU_Inst/swap_out_cml_1<5>
                                                       AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31<0>282
                                                       AVR_Core_cm2_Inst/ALU_Inst/swap_out_cml_1_4
    -------------------------------------------------  ---------------------------
    Total                                     14.715ns (8.791ns logic, 5.924ns route)
                                                       (59.7% logic, 40.3% route)

--------------------------------------------------------------------------------
Slack (setup path):     -0.812ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nreti_st0 (FF)
  Destination:          AVR_Core_cm2_Inst/ALU_Inst/swap_out_cml_1_4 (FF)
  Requirement:          14.000ns
  Data Path Delay:      14.594ns (Levels of Logic = 11)
  Clock Path Skew:      -0.218ns (0.544 - 0.762)
  Source Clock:         cp2_BUFGP rising at 0.000ns
  Destination Clock:    cp2_BUFGP rising at 14.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nreti_st0 to AVR_Core_cm2_Inst/ALU_Inst/swap_out_cml_1_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X22Y32.YQ      Tcko                  0.676   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/reti_st3
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nreti_st0
    SLICE_X23Y31.G3      net (fanout=2)        0.773   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nreti_st0
    SLICE_X23Y31.COUT    Topcyg                1.178   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_lut<3>
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
    SLICE_X21Y24.F3      net (fanout=6)        1.145   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
    SLICE_X21Y24.X       Tilo                  0.643   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<5>1
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<5>1_1
    SLICE_X20Y24.G3      net (fanout=9)        0.146   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<5>1
    SLICE_X20Y24.Y       Tilo                  0.707   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/N72
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/idc_cbi_cmp_eq0000111
    SLICE_X20Y24.F4      net (fanout=3)        0.097   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/N178
    SLICE_X20Y24.X       Tilo                  0.692   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/N72
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/idc_ret_cmp_eq000011
    SLICE_X21Y25.G4      net (fanout=5)        0.080   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/N72
    SLICE_X21Y25.Y       Tilo                  0.648   AVR_Core_cm2_Inst/ALU_Inst/idc_adiw_cml_1
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/reg_rd_adr_int_or00011
    SLICE_X20Y20.G1      net (fanout=11)       0.625   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/idc_adiw_cmp_eq00001
    SLICE_X20Y20.Y       Tilo                  0.707   AVR_Core_cm2_Inst/GPRF_Inst/reg_rd_adr_cml_1<4>
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/reg_rd_adr<4>66
    SLICE_X16Y22.G4      net (fanout=18)       0.970   AVR_Core_cm2_Inst/reg_rd_adr<4>
    SLICE_X16Y22.Y       Tilo                  0.707   AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31<6>26
                                                       AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31_int<0>1181
    SLICE_X15Y10.F3      net (fanout=60)       1.319   AVR_Core_cm2_Inst/GPRF_Inst/N221
    SLICE_X15Y10.X       Tilo                  0.643   AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31<0>82
                                                       AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31<0>82
    SLICE_X14Y11.G3      net (fanout=1)        0.044   AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31<0>82
    SLICE_X14Y11.Y       Tilo                  0.707   AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31<0>105
                                                       AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31<0>83
    SLICE_X14Y11.F3      net (fanout=1)        0.043   AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31<0>83/O
    SLICE_X14Y11.X       Tilo                  0.692   AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31<0>105
                                                       AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31<0>105
    SLICE_X15Y17.G2      net (fanout=1)        0.625   AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31<0>105
    SLICE_X15Y17.CLK     Tgck                  0.727   AVR_Core_cm2_Inst/ALU_Inst/swap_out_cml_1<5>
                                                       AVR_Core_cm2_Inst/GPRF_Inst/sg_tmp_rd_data_31<0>282
                                                       AVR_Core_cm2_Inst/ALU_Inst/swap_out_cml_1_4
    -------------------------------------------------  ---------------------------
    Total                                     14.594ns (8.727ns logic, 5.867ns route)
                                                       (59.8% logic, 40.2% route)

--------------------------------------------------------------------------------

Hold Paths: TS_cp2 = PERIOD TIMEGRP "cp2" 14 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack (hold path):      0.830ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AVR_Core_cm2_Inst/GPRF_Inst/register_file_4_1 (FF)
  Destination:          AVR_Core_cm2_Inst/GPRF_Inst/register_file_cml_1_4_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.943ns (Levels of Logic = 0)
  Clock Path Skew:      0.113ns (0.375 - 0.262)
  Source Clock:         cp2_BUFGP rising at 14.000ns
  Destination Clock:    cp2_BUFGP rising at 14.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: AVR_Core_cm2_Inst/GPRF_Inst/register_file_4_1 to AVR_Core_cm2_Inst/GPRF_Inst/register_file_cml_1_4_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X7Y3.XQ        Tcko                  0.473   AVR_Core_cm2_Inst/GPRF_Inst/register_file_4_1
                                                       AVR_Core_cm2_Inst/GPRF_Inst/register_file_4_1
    SLICE_X5Y1.BX        net (fanout=4)        0.381   AVR_Core_cm2_Inst/GPRF_Inst/register_file_4_1
    SLICE_X5Y1.CLK       Tckdi       (-Th)    -0.089   AVR_Core_cm2_Inst/GPRF_Inst/register_file_cml_1_4_1
                                                       AVR_Core_cm2_Inst/GPRF_Inst/register_file_cml_1_4_1
    -------------------------------------------------  ---------------------------
    Total                                      0.943ns (0.562ns logic, 0.381ns route)
                                                       (59.6% logic, 40.4% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.880ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AVR_Core_cm2_Inst/GPRF_Inst/r29h_3 (FF)
  Destination:          AVR_Core_cm2_Inst/GPRF_Inst/r29h_cml_1_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.970ns (Levels of Logic = 0)
  Clock Path Skew:      0.090ns (0.337 - 0.247)
  Source Clock:         cp2_BUFGP rising at 14.000ns
  Destination Clock:    cp2_BUFGP rising at 14.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: AVR_Core_cm2_Inst/GPRF_Inst/r29h_3 to AVR_Core_cm2_Inst/GPRF_Inst/r29h_cml_1_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X0Y54.XQ       Tcko                  0.505   AVR_Core_cm2_Inst/GPRF_Inst/r29h<3>
                                                       AVR_Core_cm2_Inst/GPRF_Inst/r29h_3
    SLICE_X3Y55.BX       net (fanout=4)        0.376   AVR_Core_cm2_Inst/GPRF_Inst/r29h<3>
    SLICE_X3Y55.CLK      Tckdi       (-Th)    -0.089   AVR_Core_cm2_Inst/GPRF_Inst/r29h_cml_1<3>
                                                       AVR_Core_cm2_Inst/GPRF_Inst/r29h_cml_1_3
    -------------------------------------------------  ---------------------------
    Total                                      0.970ns (0.594ns logic, 0.376ns route)
                                                       (61.2% logic, 38.8% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.894ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AVR_Core_cm2_Inst/GPRF_Inst/register_file_4_0 (FF)
  Destination:          AVR_Core_cm2_Inst/GPRF_Inst/register_file_cml_1_4_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.007ns (Levels of Logic = 0)
  Clock Path Skew:      0.113ns (0.375 - 0.262)
  Source Clock:         cp2_BUFGP rising at 14.000ns
  Destination Clock:    cp2_BUFGP rising at 14.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: AVR_Core_cm2_Inst/GPRF_Inst/register_file_4_0 to AVR_Core_cm2_Inst/GPRF_Inst/register_file_cml_1_4_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X7Y3.YQ        Tcko                  0.464   AVR_Core_cm2_Inst/GPRF_Inst/register_file_4_1
                                                       AVR_Core_cm2_Inst/GPRF_Inst/register_file_4_0
    SLICE_X5Y1.BY        net (fanout=4)        0.403   AVR_Core_cm2_Inst/GPRF_Inst/register_file_4_0
    SLICE_X5Y1.CLK       Tckdi       (-Th)    -0.140   AVR_Core_cm2_Inst/GPRF_Inst/register_file_cml_1_4_1
                                                       AVR_Core_cm2_Inst/GPRF_Inst/register_file_cml_1_4_0
    -------------------------------------------------  ---------------------------
    Total                                      1.007ns (0.604ns logic, 0.403ns route)
                                                       (60.0% logic, 40.0% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cp2 = PERIOD TIMEGRP "cp2" 14 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 10.796ns (period - (min low pulse limit / (low pulse / period)))
  Period: 14.000ns
  Low pulse: 7.000ns
  Low pulse limit: 1.602ns (Trpw)
  Physical resource: AVR_Core_cm2_Inst/IORegs_Inst/spl<2>/SR
  Logical resource: AVR_Core_cm2_Inst/IORegs_Inst/spl_2/SR
  Location pin: SLICE_X30Y57.SR
  Clock network: ireset_IBUF
--------------------------------------------------------------------------------
Slack: 10.796ns (period - (min high pulse limit / (high pulse / period)))
  Period: 14.000ns
  High pulse: 7.000ns
  High pulse limit: 1.602ns (Trpw)
  Physical resource: AVR_Core_cm2_Inst/IORegs_Inst/spl<2>/SR
  Logical resource: AVR_Core_cm2_Inst/IORegs_Inst/spl_2/SR
  Location pin: SLICE_X30Y57.SR
  Clock network: ireset_IBUF
--------------------------------------------------------------------------------
Slack: 10.796ns (period - (min low pulse limit / (low pulse / period)))
  Period: 14.000ns
  Low pulse: 7.000ns
  Low pulse limit: 1.602ns (Trpw)
  Physical resource: AVR_Core_cm2_Inst/IORegs_Inst/spl<3>/SR
  Logical resource: AVR_Core_cm2_Inst/IORegs_Inst/spl_3/SR
  Location pin: SLICE_X30Y55.SR
  Clock network: ireset_IBUF
--------------------------------------------------------------------------------


1 constraint not met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock cp2
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
cp2            |   14.933|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 23  Score: 11259  (Setup/Max: 11259, Hold: 0)

Constraints cover 593372 paths, 0 nets, and 8686 connections

Design statistics:
   Minimum period:  14.933ns{1}   (Maximum frequency:  66.966MHz)


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Wed Oct 06 22:22:03 2010 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 154 MB