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--------------------------------------------------------------------------------
Release 11.1 Trace  (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.

C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise
C:/EDAptability/coremultiplier/reference/avr/ise/ise_s3_cm3_one_syneda/ise_s3_cm3_one_syneda/ise_s3_cm3_one_syneda.ise
-intstyle ise -v 3 -s 4 -fastpaths -xml avr_core_cm3_top.twx
avr_core_cm3_top.ncd -o avr_core_cm3_top.twr avr_core_cm3_top.pcf -ucf
avr_core_cm3_top.ucf

Design file:              avr_core_cm3_top.ncd
Physical constraint file: avr_core_cm3_top.pcf
Device,package,speed:     xc3s200a,fg320,-4 (PRODUCTION 1.41 2009-03-03)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: TS_cp2 = PERIOD TIMEGRP "cp2" 10 ns HIGH 50%;

 203315 paths analyzed, 3358 endpoints analyzed, 877 failing endpoints
 877 timing errors detected. (877 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is  12.532ns.
--------------------------------------------------------------------------------
Slack (setup path):     -2.532ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_7_cml_1_7 (FF)
  Destination:          AVR_Core_cm3_Inst/pm_fetch_dec_Inst/bit_test_op_out_cml_2 (FF)
  Requirement:          10.000ns
  Data Path Delay:      12.400ns (Levels of Logic = 9)
  Clock Path Skew:      -0.132ns (0.555 - 0.687)
  Source Clock:         cp2_BUFGP rising at 0.000ns
  Destination Clock:    cp2_BUFGP rising at 10.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_7_cml_1_7 to AVR_Core_cm3_Inst/pm_fetch_dec_Inst/bit_test_op_out_cml_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X15Y35.XQ      Tcko                  0.591   AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_7_cml_1<7>
                                                       AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_7_cml_1_7
    SLICE_X20Y18.F3      net (fanout=1)        1.251   AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_7_cml_1<7>
    SLICE_X20Y18.X       Tilo                  0.692   N507
                                                       AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_31<7>86_SW0
    SLICE_X29Y16.G4      net (fanout=1)        1.137   N507
    SLICE_X29Y16.Y       Tilo                  0.648   AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_31<7>87
                                                       AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_31<7>86
    SLICE_X29Y16.F3      net (fanout=1)        0.043   AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_31<7>86/O
    SLICE_X29Y16.X       Tilo                  0.643   AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_31<7>87
                                                       AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_31<7>87
    SLICE_X29Y18.G4      net (fanout=1)        0.330   AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_31<7>87
    SLICE_X29Y18.X       Tif5x                 0.924   AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_31<7>104
                                                       AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_31<7>104_F
                                                       AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_31<7>104
    SLICE_X25Y22.G2      net (fanout=1)        0.741   AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_31<7>104
    SLICE_X25Y22.Y       Tilo                  0.648   AVR_Core_cm3_Inst/ALU_Inst/swap_out_cml_2<3>
                                                       AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_31<7>170
    SLICE_X25Y22.F3      net (fanout=1)        0.043   AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_31<7>170/O
    SLICE_X25Y22.X       Tilo                  0.643   AVR_Core_cm3_Inst/ALU_Inst/swap_out_cml_2<3>
                                                       AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_31<7>236
    SLICE_X14Y13.G4      net (fanout=11)       1.312   AVR_Core_cm3_Inst/reg_rd_out<7>
    SLICE_X14Y13.Y       Tilo                  0.707   N288
                                                       AVR_Core_cm3_Inst/BP_Inst/bit_test_mux_out_7_mux000012
    SLICE_X15Y12.BX      net (fanout=2)        0.446   AVR_Core_cm3_Inst/BP_Inst/bit_test_mux_out_7_mux000012
    SLICE_X15Y12.X       Tbxx                  0.756   N289
                                                       AVR_Core_cm3_Inst/BP_Inst/bit_test_mux_out_7_mux0000294_SW1
    SLICE_X15Y13.F2      net (fanout=1)        0.123   N289
    SLICE_X15Y13.CLK     Tfck                  0.722   AVR_Core_cm3_Inst/pm_fetch_dec_Inst/bit_test_op_out_cml_2
                                                       AVR_Core_cm3_Inst/BP_Inst/bit_test_op_out281
                                                       AVR_Core_cm3_Inst/pm_fetch_dec_Inst/bit_test_op_out_cml_2
    -------------------------------------------------  ---------------------------
    Total                                     12.400ns (6.974ns logic, 5.426ns route)
                                                       (56.2% logic, 43.8% route)

--------------------------------------------------------------------------------
Slack (setup path):     -2.487ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AVR_Core_cm3_Inst/ALU_Inst/idc_adiw_cml_2 (FF)
  Destination:          AVR_Core_cm3_Inst/pm_fetch_dec_Inst/nirq_st0 (FF)
  Requirement:          10.000ns
  Data Path Delay:      12.424ns (Levels of Logic = 9)
  Clock Path Skew:      -0.063ns (0.666 - 0.729)
  Source Clock:         cp2_BUFGP rising at 0.000ns
  Destination Clock:    cp2_BUFGP rising at 10.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: AVR_Core_cm3_Inst/ALU_Inst/idc_adiw_cml_2 to AVR_Core_cm3_Inst/pm_fetch_dec_Inst/nirq_st0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X13Y22.XQ      Tcko                  0.591   AVR_Core_cm3_Inst/ALU_Inst/idc_adiw_cml_2
                                                       AVR_Core_cm3_Inst/ALU_Inst/idc_adiw_cml_2
    SLICE_X25Y19.G4      net (fanout=8)        1.082   AVR_Core_cm3_Inst/ALU_Inst/idc_adiw_cml_2
    SLICE_X25Y19.Y       Tilo                  0.648   AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_0_or0000
                                                       AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_0_or000020
    SLICE_X25Y19.F2      net (fanout=1)        0.430   AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_0_or000020/O
    SLICE_X25Y19.X       Tilo                  0.643   AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_0_or0000
                                                       AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_0_or000030
    SLICE_X26Y14.G3      net (fanout=8)        0.829   AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_0_or0000
    SLICE_X26Y14.Y       Tilo                  0.707   AVR_Core_cm3_Inst/alu_data_out<6>
                                                       AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_6_or000038
    SLICE_X26Y14.F4      net (fanout=1)        0.060   AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_6_or000038/O
    SLICE_X26Y14.X       Tilo                  0.692   AVR_Core_cm3_Inst/alu_data_out<6>
                                                       AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_6_or000046
    SLICE_X24Y15.F4      net (fanout=2)        0.363   AVR_Core_cm3_Inst/alu_data_out<6>
    SLICE_X24Y15.X       Tilo                  0.692   AVR_Core_cm3_Inst/ALU_Inst/alu_z_flag_out_int_cmp_eq000025
                                                       AVR_Core_cm3_Inst/ALU_Inst/alu_z_flag_out_int_cmp_eq000025
    SLICE_X13Y20.G2      net (fanout=2)        1.032   AVR_Core_cm3_Inst/ALU_Inst/alu_z_flag_out_int_cmp_eq000025
    SLICE_X13Y20.Y       Tilo                  0.648   AVR_Core_cm3_Inst/pm_fetch_dec_Inst/skip_inst_start
                                                       AVR_Core_cm3_Inst/ALU_Inst/alu_z_flag_out_cml_out
    SLICE_X13Y20.F3      net (fanout=2)        0.059   AVR_Core_cm3_Inst/alu_z_flag_out
    SLICE_X13Y20.X       Tilo                  0.643   AVR_Core_cm3_Inst/pm_fetch_dec_Inst/skip_inst_start
                                                       AVR_Core_cm3_Inst/pm_fetch_dec_Inst/skip_inst_start
    SLICE_X9Y22.G4       net (fanout=3)        0.670   AVR_Core_cm3_Inst/pm_fetch_dec_Inst/skip_inst_start
    SLICE_X9Y22.Y        Tilo                  0.648   AVR_Core_cm3_Inst/pm_fetch_dec_Inst/pc_for_interrupt<9>
                                                       AVR_Core_cm3_Inst/pm_fetch_dec_Inst/pc_for_interrupt_mux0002<0>141
    SLICE_X8Y33.G3       net (fanout=19)       1.170   AVR_Core_cm3_Inst/pm_fetch_dec_Inst/N12
    SLICE_X8Y33.CLK      Tgck                  0.817   AVR_Core_cm3_Inst/pm_fetch_dec_Inst/nicall_st0
                                                       AVR_Core_cm3_Inst/pm_fetch_dec_Inst/nirq_st0_mux00011
                                                       AVR_Core_cm3_Inst/pm_fetch_dec_Inst/nirq_st0
    -------------------------------------------------  ---------------------------
    Total                                     12.424ns (6.729ns logic, 5.695ns route)
                                                       (54.2% logic, 45.8% route)

--------------------------------------------------------------------------------
Slack (setup path):     -2.468ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AVR_Core_cm3_Inst/ALU_Inst/idc_cpse_cml_2 (FF)
  Destination:          AVR_Core_cm3_Inst/pm_fetch_dec_Inst/nirq_st0 (FF)
  Requirement:          10.000ns
  Data Path Delay:      12.429ns (Levels of Logic = 9)
  Clock Path Skew:      -0.039ns (0.666 - 0.705)
  Source Clock:         cp2_BUFGP rising at 0.000ns
  Destination Clock:    cp2_BUFGP rising at 10.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: AVR_Core_cm3_Inst/ALU_Inst/idc_cpse_cml_2 to AVR_Core_cm3_Inst/pm_fetch_dec_Inst/nirq_st0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y21.XQ      Tcko                  0.631   AVR_Core_cm3_Inst/ALU_Inst/idc_cpse_cml_2
                                                       AVR_Core_cm3_Inst/ALU_Inst/idc_cpse_cml_2
    SLICE_X12Y22.F1      net (fanout=2)        0.763   AVR_Core_cm3_Inst/ALU_Inst/idc_cpse_cml_2
    SLICE_X12Y22.X       Tilo                  0.692   AVR_Core_cm3_Inst/pm_fetch_dec_Inst/sbiw_st
                                                       AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_0_or000015
    SLICE_X25Y19.F4      net (fanout=1)        0.670   AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_0_or000015
    SLICE_X25Y19.X       Tilo                  0.643   AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_0_or0000
                                                       AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_0_or000030
    SLICE_X26Y14.G3      net (fanout=8)        0.829   AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_0_or0000
    SLICE_X26Y14.Y       Tilo                  0.707   AVR_Core_cm3_Inst/alu_data_out<6>
                                                       AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_6_or000038
    SLICE_X26Y14.F4      net (fanout=1)        0.060   AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_6_or000038/O
    SLICE_X26Y14.X       Tilo                  0.692   AVR_Core_cm3_Inst/alu_data_out<6>
                                                       AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_6_or000046
    SLICE_X24Y15.F4      net (fanout=2)        0.363   AVR_Core_cm3_Inst/alu_data_out<6>
    SLICE_X24Y15.X       Tilo                  0.692   AVR_Core_cm3_Inst/ALU_Inst/alu_z_flag_out_int_cmp_eq000025
                                                       AVR_Core_cm3_Inst/ALU_Inst/alu_z_flag_out_int_cmp_eq000025
    SLICE_X13Y20.G2      net (fanout=2)        1.032   AVR_Core_cm3_Inst/ALU_Inst/alu_z_flag_out_int_cmp_eq000025
    SLICE_X13Y20.Y       Tilo                  0.648   AVR_Core_cm3_Inst/pm_fetch_dec_Inst/skip_inst_start
                                                       AVR_Core_cm3_Inst/ALU_Inst/alu_z_flag_out_cml_out
    SLICE_X13Y20.F3      net (fanout=2)        0.059   AVR_Core_cm3_Inst/alu_z_flag_out
    SLICE_X13Y20.X       Tilo                  0.643   AVR_Core_cm3_Inst/pm_fetch_dec_Inst/skip_inst_start
                                                       AVR_Core_cm3_Inst/pm_fetch_dec_Inst/skip_inst_start
    SLICE_X9Y22.G4       net (fanout=3)        0.670   AVR_Core_cm3_Inst/pm_fetch_dec_Inst/skip_inst_start
    SLICE_X9Y22.Y        Tilo                  0.648   AVR_Core_cm3_Inst/pm_fetch_dec_Inst/pc_for_interrupt<9>
                                                       AVR_Core_cm3_Inst/pm_fetch_dec_Inst/pc_for_interrupt_mux0002<0>141
    SLICE_X8Y33.G3       net (fanout=19)       1.170   AVR_Core_cm3_Inst/pm_fetch_dec_Inst/N12
    SLICE_X8Y33.CLK      Tgck                  0.817   AVR_Core_cm3_Inst/pm_fetch_dec_Inst/nicall_st0
                                                       AVR_Core_cm3_Inst/pm_fetch_dec_Inst/nirq_st0_mux00011
                                                       AVR_Core_cm3_Inst/pm_fetch_dec_Inst/nirq_st0
    -------------------------------------------------  ---------------------------
    Total                                     12.429ns (6.813ns logic, 5.616ns route)
                                                       (54.8% logic, 45.2% route)

--------------------------------------------------------------------------------

Hold Paths: TS_cp2 = PERIOD TIMEGRP "cp2" 10 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack (hold path):      0.656ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AVR_Core_cm3_Inst/GPRF_Inst/register_file_6_6 (FF)
  Destination:          AVR_Core_cm3_Inst/GPRF_Inst/Mshreg_register_file_cml_2_6_6/SRL16E (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.722ns (Levels of Logic = 1)
  Clock Path Skew:      0.066ns (0.383 - 0.317)
  Source Clock:         cp2_BUFGP rising at 10.000ns
  Destination Clock:    cp2_BUFGP rising at 10.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: AVR_Core_cm3_Inst/GPRF_Inst/register_file_6_6 to AVR_Core_cm3_Inst/GPRF_Inst/Mshreg_register_file_cml_2_6_6/SRL16E
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X29Y41.YQ      Tcko                  0.464   AVR_Core_cm3_Inst/GPRF_Inst/register_file_6_7
                                                       AVR_Core_cm3_Inst/GPRF_Inst/register_file_6_6
    SLICE_X30Y40.BY      net (fanout=4)        0.384   AVR_Core_cm3_Inst/GPRF_Inst/register_file_6_6
    SLICE_X30Y40.CLK     Tdh         (-Th)     0.126   AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_2_6_7
                                                       AVR_Core_cm3_Inst/GPRF_Inst/Mshreg_register_file_cml_2_6_6/SRL16E
    -------------------------------------------------  ---------------------------
    Total                                      0.722ns (0.338ns logic, 0.384ns route)
                                                       (46.8% logic, 53.2% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.657ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AVR_Core_cm3_Inst/pm_fetch_dec_Inst/irqackad_int_1 (FF)
  Destination:          AVR_Core_cm3_Inst/pm_fetch_dec_Inst/Mshreg_irqackad_int_cml_2_1/SRL16E (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.670ns (Levels of Logic = 1)
  Clock Path Skew:      0.013ns (0.090 - 0.077)
  Source Clock:         cp2_BUFGP rising at 10.000ns
  Destination Clock:    cp2_BUFGP rising at 10.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: AVR_Core_cm3_Inst/pm_fetch_dec_Inst/irqackad_int_1 to AVR_Core_cm3_Inst/pm_fetch_dec_Inst/Mshreg_irqackad_int_cml_2_1/SRL16E
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X29Y6.XQ       Tcko                  0.473   AVR_Core_cm3_Inst/pm_fetch_dec_Inst/irqackad_int<1>
                                                       AVR_Core_cm3_Inst/pm_fetch_dec_Inst/irqackad_int_1
    SLICE_X28Y7.BX       net (fanout=1)        0.343   AVR_Core_cm3_Inst/pm_fetch_dec_Inst/irqackad_int<1>
    SLICE_X28Y7.CLK      Tdh         (-Th)     0.146   AVR_Core_cm3_Inst/pm_fetch_dec_Inst/irqackad_int_cml_2<1>
                                                       AVR_Core_cm3_Inst/pm_fetch_dec_Inst/Mshreg_irqackad_int_cml_2_1/SRL16E
    -------------------------------------------------  ---------------------------
    Total                                      0.670ns (0.327ns logic, 0.343ns route)
                                                       (48.8% logic, 51.2% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.659ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AVR_Core_cm3_Inst/pm_fetch_dec_Inst/program_counter_tmp_7 (FF)
  Destination:          AVR_Core_cm3_Inst/pm_fetch_dec_Inst/Mshreg_program_counter_tmp_cml_2_7/SRL16E (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.670ns (Levels of Logic = 1)
  Clock Path Skew:      0.011ns (0.078 - 0.067)
  Source Clock:         cp2_BUFGP rising at 10.000ns
  Destination Clock:    cp2_BUFGP rising at 10.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: AVR_Core_cm3_Inst/pm_fetch_dec_Inst/program_counter_tmp_7 to AVR_Core_cm3_Inst/pm_fetch_dec_Inst/Mshreg_program_counter_tmp_cml_2_7/SRL16E
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X5Y8.XQ        Tcko                  0.473   AVR_Core_cm3_Inst/pm_fetch_dec_Inst/program_counter_tmp<7>
                                                       AVR_Core_cm3_Inst/pm_fetch_dec_Inst/program_counter_tmp_7
    SLICE_X4Y9.BX        net (fanout=1)        0.343   AVR_Core_cm3_Inst/pm_fetch_dec_Inst/program_counter_tmp<7>
    SLICE_X4Y9.CLK       Tdh         (-Th)     0.146   AVR_Core_cm3_Inst/pm_fetch_dec_Inst/program_counter_tmp_cml_2<7>
                                                       AVR_Core_cm3_Inst/pm_fetch_dec_Inst/Mshreg_program_counter_tmp_cml_2_7/SRL16E
    -------------------------------------------------  ---------------------------
    Total                                      0.670ns (0.327ns logic, 0.343ns route)
                                                       (48.8% logic, 51.2% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cp2 = PERIOD TIMEGRP "cp2" 10 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 6.796ns (period - (min low pulse limit / (low pulse / period)))
  Period: 10.000ns
  Low pulse: 5.000ns
  Low pulse limit: 1.602ns (Trpw)
  Physical resource: AVR_Core_cm3_Inst/pm_fetch_dec_Inst/sts_st/SR
  Logical resource: AVR_Core_cm3_Inst/pm_fetch_dec_Inst/sts_st/SR
  Location pin: SLICE_X8Y42.SR
  Clock network: ireset_IBUF
--------------------------------------------------------------------------------
Slack: 6.796ns (period - (min high pulse limit / (high pulse / period)))
  Period: 10.000ns
  High pulse: 5.000ns
  High pulse limit: 1.602ns (Trpw)
  Physical resource: AVR_Core_cm3_Inst/pm_fetch_dec_Inst/sts_st/SR
  Logical resource: AVR_Core_cm3_Inst/pm_fetch_dec_Inst/sts_st/SR
  Location pin: SLICE_X8Y42.SR
  Clock network: ireset_IBUF
--------------------------------------------------------------------------------
Slack: 6.796ns (period - (min low pulse limit / (low pulse / period)))
  Period: 10.000ns
  Low pulse: 5.000ns
  Low pulse limit: 1.602ns (Trpw)
  Physical resource: AVR_Core_cm3_Inst/GPRF_Inst/r27h<6>/SR
  Logical resource: AVR_Core_cm3_Inst/GPRF_Inst/r27h_6/SR
  Location pin: SLICE_X18Y47.SR
  Clock network: ireset_IBUF
--------------------------------------------------------------------------------


1 constraint not met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock cp2
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
cp2            |   12.532|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 877  Score: 991383  (Setup/Max: 991383, Hold: 0)

Constraints cover 203315 paths, 0 nets, and 9716 connections

Design statistics:
   Minimum period:  12.532ns{1}   (Maximum frequency:  79.796MHz)


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Mon Oct 04 22:47:51 2010 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 160 MB