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--------------------------------------------------------------------------------
Release 11.1 Trace  (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.

C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise
C:/EDAptability/coremultiplier/reference/avr/ise/ise_s3_cm4_one_syneda/ise_s3_cm4_one_syneda/ise_s3_cm4_one_syneda.ise
-intstyle ise -v 3 -s 4 -fastpaths -xml avr_core_cm4_top.twx
avr_core_cm4_top.ncd -o avr_core_cm4_top.twr avr_core_cm4_top.pcf -ucf
avr_core_cm4_top.ucf

Design file:              avr_core_cm4_top.ncd
Physical constraint file: avr_core_cm4_top.pcf
Device,package,speed:     xc3s200a,fg320,-4 (PRODUCTION 1.41 2009-03-03)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: TS_cp2 = PERIOD TIMEGRP "cp2" 11.5 ns HIGH 50%;

 145500 paths analyzed, 3279 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is  11.446ns.
--------------------------------------------------------------------------------
Slack (setup path):     0.054ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0 (FF)
  Destination:          AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1_0 (FF)
  Requirement:          11.500ns
  Data Path Delay:      11.290ns (Levels of Logic = 8)
  Clock Path Skew:      -0.156ns (0.566 - 0.722)
  Source Clock:         cp2_BUFGP rising at 0.000ns
  Destination Clock:    cp2_BUFGP rising at 11.500ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0 to AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X19Y23.XQ      Tcko                  0.591   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0
    SLICE_X21Y28.G4      net (fanout=2)        1.177   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0
    SLICE_X21Y28.COUT    Topcyg                1.178   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_lut<1>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
    SLICE_X21Y29.CIN     net (fanout=1)        0.000   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
    SLICE_X21Y29.COUT    Tbyp                  0.130   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<2>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
    SLICE_X21Y30.CIN     net (fanout=1)        0.000   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
    SLICE_X21Y30.COUT    Tbyp                  0.130   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<4>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<5>
    SLICE_X18Y20.G3      net (fanout=51)       1.520   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st
    SLICE_X18Y20.Y       Tilo                  0.707   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N69
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_icall_cmp_eq0000111
    SLICE_X18Y20.F4      net (fanout=2)        0.131   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N104
    SLICE_X18Y20.X       Tilo                  0.692   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N69
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_icall_cmp_eq000011
    SLICE_X19Y20.G4      net (fanout=7)        0.130   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N69
    SLICE_X19Y20.Y       Tilo                  0.648   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_adiw_cml_1
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr_int_or00011
    SLICE_X17Y18.G4      net (fanout=7)        0.391   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_adiw_cmp_eq00001
    SLICE_X17Y18.Y       Tilo                  0.648   AVR_Core_cm4_Inst/reg_rd_adr<3>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr<3>47_SW0
    SLICE_X17Y18.F3      net (fanout=1)        0.043   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr<3>47_SW0/O
    SLICE_X17Y18.X       Tilo                  0.643   AVR_Core_cm4_Inst/reg_rd_adr<3>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr<3>47
    SLICE_X15Y8.SR       net (fanout=33)       1.664   AVR_Core_cm4_Inst/reg_rd_adr<3>
    SLICE_X15Y8.CLK      Tsrck                 0.867   AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1<1>
                                                       AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1_0
    -------------------------------------------------  ---------------------------
    Total                                     11.290ns (6.234ns logic, 5.056ns route)
                                                       (55.2% logic, 44.8% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.054ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0 (FF)
  Destination:          AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1_1 (FF)
  Requirement:          11.500ns
  Data Path Delay:      11.290ns (Levels of Logic = 8)
  Clock Path Skew:      -0.156ns (0.566 - 0.722)
  Source Clock:         cp2_BUFGP rising at 0.000ns
  Destination Clock:    cp2_BUFGP rising at 11.500ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0 to AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X19Y23.XQ      Tcko                  0.591   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0
    SLICE_X21Y28.G4      net (fanout=2)        1.177   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0
    SLICE_X21Y28.COUT    Topcyg                1.178   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_lut<1>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
    SLICE_X21Y29.CIN     net (fanout=1)        0.000   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
    SLICE_X21Y29.COUT    Tbyp                  0.130   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<2>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
    SLICE_X21Y30.CIN     net (fanout=1)        0.000   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
    SLICE_X21Y30.COUT    Tbyp                  0.130   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<4>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<5>
    SLICE_X18Y20.G3      net (fanout=51)       1.520   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st
    SLICE_X18Y20.Y       Tilo                  0.707   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N69
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_icall_cmp_eq0000111
    SLICE_X18Y20.F4      net (fanout=2)        0.131   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N104
    SLICE_X18Y20.X       Tilo                  0.692   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N69
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_icall_cmp_eq000011
    SLICE_X19Y20.G4      net (fanout=7)        0.130   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N69
    SLICE_X19Y20.Y       Tilo                  0.648   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_adiw_cml_1
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr_int_or00011
    SLICE_X17Y18.G4      net (fanout=7)        0.391   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_adiw_cmp_eq00001
    SLICE_X17Y18.Y       Tilo                  0.648   AVR_Core_cm4_Inst/reg_rd_adr<3>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr<3>47_SW0
    SLICE_X17Y18.F3      net (fanout=1)        0.043   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr<3>47_SW0/O
    SLICE_X17Y18.X       Tilo                  0.643   AVR_Core_cm4_Inst/reg_rd_adr<3>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr<3>47
    SLICE_X15Y8.SR       net (fanout=33)       1.664   AVR_Core_cm4_Inst/reg_rd_adr<3>
    SLICE_X15Y8.CLK      Tsrck                 0.867   AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1<1>
                                                       AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1_1
    -------------------------------------------------  ---------------------------
    Total                                     11.290ns (6.234ns logic, 5.056ns route)
                                                       (55.2% logic, 44.8% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.061ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0 (FF)
  Destination:          AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1_18 (FF)
  Requirement:          11.500ns
  Data Path Delay:      11.266ns (Levels of Logic = 9)
  Clock Path Skew:      -0.173ns (0.549 - 0.722)
  Source Clock:         cp2_BUFGP rising at 0.000ns
  Destination Clock:    cp2_BUFGP rising at 11.500ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0 to AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1_18
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X19Y23.XQ      Tcko                  0.591   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0
    SLICE_X21Y28.G4      net (fanout=2)        1.177   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0
    SLICE_X21Y28.COUT    Topcyg                1.178   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_lut<1>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
    SLICE_X21Y29.CIN     net (fanout=1)        0.000   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
    SLICE_X21Y29.COUT    Tbyp                  0.130   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<2>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
    SLICE_X21Y30.CIN     net (fanout=1)        0.000   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
    SLICE_X21Y30.COUT    Tbyp                  0.130   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<4>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<5>
    SLICE_X18Y20.G3      net (fanout=51)       1.520   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st
    SLICE_X18Y20.Y       Tilo                  0.707   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N69
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_icall_cmp_eq0000111
    SLICE_X18Y20.F4      net (fanout=2)        0.131   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N104
    SLICE_X18Y20.X       Tilo                  0.692   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N69
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_icall_cmp_eq000011
    SLICE_X19Y20.G4      net (fanout=7)        0.130   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N69
    SLICE_X19Y20.Y       Tilo                  0.648   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_adiw_cml_1
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr_int_or00011
    SLICE_X14Y14.G2      net (fanout=7)        0.855   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_adiw_cmp_eq00001
    SLICE_X14Y14.Y       Tilo                  0.707   AVR_Core_cm4_Inst/reg_rd_adr<0>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr<0>47
    SLICE_X14Y14.F4      net (fanout=3)        0.077   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr<0>47
    SLICE_X14Y14.X       Tilo                  0.692   AVR_Core_cm4_Inst/reg_rd_adr<0>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr<0>56
    SLICE_X11Y15.G1      net (fanout=45)       1.174   AVR_Core_cm4_Inst/reg_rd_adr<0>
    SLICE_X11Y15.CLK     Tgck                  0.727   AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1<19>
                                                       AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_18_cmp_eq000011
                                                       AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1_18
    -------------------------------------------------  ---------------------------
    Total                                     11.266ns (6.202ns logic, 5.064ns route)
                                                       (55.1% logic, 44.9% route)

--------------------------------------------------------------------------------

Hold Paths: TS_cp2 = PERIOD TIMEGRP "cp2" 11.5 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack (hold path):      0.601ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_16_7 (FF)
  Destination:          AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_16_7/SRL16E (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.708ns (Levels of Logic = 1)
  Clock Path Skew:      0.107ns (0.337 - 0.230)
  Source Clock:         cp2_BUFGP rising at 11.500ns
  Destination Clock:    cp2_BUFGP rising at 11.500ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_16_7 to AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_16_7/SRL16E
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X9Y22.XQ       Tcko                  0.473   AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_16_7
                                                       AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_16_7
    SLICE_X6Y23.BX       net (fanout=2)        0.381   AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_16_7
    SLICE_X6Y23.CLK      Tdh         (-Th)     0.146   AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_3_16_7
                                                       AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_16_7/SRL16E
    -------------------------------------------------  ---------------------------
    Total                                      0.708ns (0.327ns logic, 0.381ns route)
                                                       (46.2% logic, 53.8% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.601ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_21_0 (FF)
  Destination:          AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_21_0/SRL16E (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.715ns (Levels of Logic = 1)
  Clock Path Skew:      0.114ns (0.430 - 0.316)
  Source Clock:         cp2_BUFGP rising at 11.500ns
  Destination Clock:    cp2_BUFGP rising at 11.500ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_21_0 to AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_21_0/SRL16E
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X3Y35.YQ       Tcko                  0.464   AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_21_1
                                                       AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_21_0
    SLICE_X0Y34.BY       net (fanout=2)        0.377   AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_21_0
    SLICE_X0Y34.CLK      Tdh         (-Th)     0.126   AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_3_21_1
                                                       AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_21_0/SRL16E
    -------------------------------------------------  ---------------------------
    Total                                      0.715ns (0.338ns logic, 0.377ns route)
                                                       (47.3% logic, 52.7% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.610ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_19_5 (FF)
  Destination:          AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_19_5/SRL16E (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.746ns (Levels of Logic = 1)
  Clock Path Skew:      0.136ns (0.375 - 0.239)
  Source Clock:         cp2_BUFGP rising at 11.500ns
  Destination Clock:    cp2_BUFGP rising at 11.500ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_19_5 to AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_19_5/SRL16E
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X8Y26.XQ       Tcko                  0.505   AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_19_5
                                                       AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_19_5
    SLICE_X6Y26.BX       net (fanout=2)        0.387   AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_19_5
    SLICE_X6Y26.CLK      Tdh         (-Th)     0.146   AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_3_19_5
                                                       AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_19_5/SRL16E
    -------------------------------------------------  ---------------------------
    Total                                      0.746ns (0.359ns logic, 0.387ns route)
                                                       (48.1% logic, 51.9% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cp2 = PERIOD TIMEGRP "cp2" 11.5 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 8.296ns (period - (min low pulse limit / (low pulse / period)))
  Period: 11.500ns
  Low pulse: 5.750ns
  Low pulse limit: 1.602ns (Trpw)
  Physical resource: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ramwe_int/SR
  Logical resource: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ramwe_int/SR
  Location pin: SLICE_X28Y46.SR
  Clock network: ireset_IBUF
--------------------------------------------------------------------------------
Slack: 8.296ns (period - (min high pulse limit / (high pulse / period)))
  Period: 11.500ns
  High pulse: 5.750ns
  High pulse limit: 1.602ns (Trpw)
  Physical resource: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ramwe_int/SR
  Logical resource: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ramwe_int/SR
  Location pin: SLICE_X28Y46.SR
  Clock network: ireset_IBUF
--------------------------------------------------------------------------------
Slack: 8.296ns (period - (min low pulse limit / (low pulse / period)))
  Period: 11.500ns
  Low pulse: 5.750ns
  Low pulse limit: 1.602ns (Trpw)
  Physical resource: AVR_Core_cm4_Inst/GPRF_Inst/r29h<0>/SR
  Logical resource: AVR_Core_cm4_Inst/GPRF_Inst/r29h_0/SR
  Location pin: SLICE_X2Y60.SR
  Clock network: ireset_IBUF
--------------------------------------------------------------------------------


All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock cp2
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
cp2            |   11.446|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 0  Score: 0  (Setup/Max: 0, Hold: 0)

Constraints cover 145500 paths, 0 nets, and 9529 connections

Design statistics:
   Minimum period:  11.446ns{1}   (Maximum frequency:  87.367MHz)


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Sun Oct 03 11:38:16 2010 
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Trace Settings:
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Trace Settings 

Peak Memory Usage: 163 MB