Subversion Repositories avr_hp

--------------------------------------------------------------------------------
Release 11.1 Trace  (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.

C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise
C:/EDAptability/coremultiplier/reference/avr/ise/ise_v5/ise_v5/ise_v5.ise
-intstyle ise -v 3 -s 3 -fastpaths -xml avr_core.twx avr_core.ncd -o
avr_core.twr avr_core.pcf -ucf avr_core.ucf

Design file:              avr_core.ncd
Physical constraint file: avr_core.pcf
Device,package,speed:     xc5vlx50,ff324,-3 (PRODUCTION 1.64 2009-03-03, STEPPING level 0)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: TS_cp2 = PERIOD TIMEGRP "cp2" 8 ns HIGH 50%;

 106838544 paths analyzed, 1535 endpoints analyzed, 170 failing endpoints
 170 timing errors detected. (170 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   9.385ns.
--------------------------------------------------------------------------------
Slack (setup path):     -1.385ns (requirement - (data path - clock path skew + uncertainty))
  Source:               pm_fetch_dec_Inst/ld_st (FF)
  Destination:          pm_fetch_dec_Inst/pc_for_interrupt_6 (FF)
  Requirement:          8.000ns
  Data Path Delay:      9.206ns (Levels of Logic = 13)
  Clock Path Skew:      -0.144ns (1.017 - 1.161)
  Source Clock:         cp2_BUFGP rising at 0.000ns
  Destination Clock:    cp2_BUFGP rising at 8.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: pm_fetch_dec_Inst/ld_st to pm_fetch_dec_Inst/pc_for_interrupt_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X17Y39.AQ      Tcko                  0.326   pm_fetch_dec_Inst/lds_st
                                                       pm_fetch_dec_Inst/ld_st
    SLICE_X17Y45.D1      net (fanout=14)       0.827   pm_fetch_dec_Inst/ld_st
    SLICE_X17Y45.D       Tilo                  0.080   pm_fetch_dec_Inst/sts_st
                                                       pm_fetch_dec_Inst/nop_insert_st46
    SLICE_X16Y41.A3      net (fanout=16)       0.724   pm_fetch_dec_Inst/nop_insert_st46
    SLICE_X16Y41.A       Tilo                  0.080   pm_fetch_dec_Inst/instruction_reg<11>
                                                       pm_fetch_dec_Inst/idc_elpm_cmp_eq000011
    SLICE_X16Y41.D1      net (fanout=28)       0.606   pm_fetch_dec_Inst/N65
    SLICE_X16Y41.D       Tilo                  0.080   pm_fetch_dec_Inst/instruction_reg<11>
                                                       pm_fetch_dec_Inst/reg_rd_adr<2>60_SW2
    SLICE_X14Y37.C4      net (fanout=1)        0.528   N465
    SLICE_X14Y37.C       Tilo                  0.080   GPRF_Inst/register_file_9_not0001
                                                       pm_fetch_dec_Inst/reg_rd_adr<2>60
    SLICE_X14Y35.D6      net (fanout=100)      0.511   reg_rd_adr<2>
    SLICE_X14Y35.CMUX    Topdc                 0.313   GPRF_Inst/sg_tmp_rd_data_31<0>37
                                                       GPRF_Inst/sg_tmp_rd_data_31<0>37_F
                                                       GPRF_Inst/sg_tmp_rd_data_31<0>37
    SLICE_X12Y35.B1      net (fanout=3)        0.682   GPRF_Inst/sg_tmp_rd_data_31<0>37
    SLICE_X12Y35.B       Tilo                  0.080   pm_fetch_dec_Inst/gp_reg_tmp<1>
                                                       GPRF_Inst/sg_tmp_rd_data_31<0>295
    SLICE_X11Y38.B4      net (fanout=26)       0.744   reg_rd_out<0>
    SLICE_X11Y38.B       Tilo                  0.080   N210
                                                       ALU_Inst/neg_op_carry_2_and00001
    SLICE_X11Y38.A5      net (fanout=4)        0.172   ALU_Inst/neg_op_carry<2>
    SLICE_X11Y38.A       Tilo                  0.080   N210
                                                       ALU_Inst/alu_data_out_int_6_or000047
    SLICE_X11Y38.D3      net (fanout=2)        0.466   ALU_Inst/alu_data_out_int_6_or000047
    SLICE_X11Y38.D       Tilo                  0.080   N210
                                                       ALU_Inst/alu_data_out_int_6_or0000174_SW1
    SLICE_X10Y42.C5      net (fanout=2)        0.432   N210
    SLICE_X10Y42.C       Tilo                  0.080   IORegs_Inst/sreg<4>
                                                       ALU_Inst/alu_data_out_int_6_or0000174
    SLICE_X11Y43.A2      net (fanout=2)        0.552   alu_data_out<6>
    SLICE_X11Y43.A       Tilo                  0.080   pm_fetch_dec_Inst/irqack_int
                                                       pm_fetch_dec_Inst/skip_inst_start_SW0
    SLICE_X10Y67.A6      net (fanout=6)        1.012   N198
    SLICE_X10Y67.A       Tilo                  0.080   pm_fetch_dec_Inst/pc_for_interrupt<15>
                                                       pm_fetch_dec_Inst/pc_for_interrupt_not00011
    SLICE_X11Y68.C6      net (fanout=16)       0.401   pm_fetch_dec_Inst/pc_for_interrupt_not0001
    SLICE_X11Y68.CLK     Tas                   0.030   pm_fetch_dec_Inst/pc_for_interrupt<7>
                                                       pm_fetch_dec_Inst/pc_for_interrupt_6_rstpot
                                                       pm_fetch_dec_Inst/pc_for_interrupt_6
    -------------------------------------------------  ---------------------------
    Total                                      9.206ns (1.549ns logic, 7.657ns route)
                                                       (16.8% logic, 83.2% route)

--------------------------------------------------------------------------------
Slack (setup path):     -1.383ns (requirement - (data path - clock path skew + uncertainty))
  Source:               pm_fetch_dec_Inst/ld_st (FF)
  Destination:          pm_fetch_dec_Inst/pc_for_interrupt_6 (FF)
  Requirement:          8.000ns
  Data Path Delay:      9.204ns (Levels of Logic = 13)
  Clock Path Skew:      -0.144ns (1.017 - 1.161)
  Source Clock:         cp2_BUFGP rising at 0.000ns
  Destination Clock:    cp2_BUFGP rising at 8.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: pm_fetch_dec_Inst/ld_st to pm_fetch_dec_Inst/pc_for_interrupt_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X17Y39.AQ      Tcko                  0.326   pm_fetch_dec_Inst/lds_st
                                                       pm_fetch_dec_Inst/ld_st
    SLICE_X17Y45.D1      net (fanout=14)       0.827   pm_fetch_dec_Inst/ld_st
    SLICE_X17Y45.D       Tilo                  0.080   pm_fetch_dec_Inst/sts_st
                                                       pm_fetch_dec_Inst/nop_insert_st46
    SLICE_X16Y41.A3      net (fanout=16)       0.724   pm_fetch_dec_Inst/nop_insert_st46
    SLICE_X16Y41.A       Tilo                  0.080   pm_fetch_dec_Inst/instruction_reg<11>
                                                       pm_fetch_dec_Inst/idc_elpm_cmp_eq000011
    SLICE_X16Y41.D1      net (fanout=28)       0.606   pm_fetch_dec_Inst/N65
    SLICE_X16Y41.D       Tilo                  0.080   pm_fetch_dec_Inst/instruction_reg<11>
                                                       pm_fetch_dec_Inst/reg_rd_adr<2>60_SW2
    SLICE_X14Y37.C4      net (fanout=1)        0.528   N465
    SLICE_X14Y37.C       Tilo                  0.080   GPRF_Inst/register_file_9_not0001
                                                       pm_fetch_dec_Inst/reg_rd_adr<2>60
    SLICE_X14Y35.C6      net (fanout=100)      0.512   reg_rd_adr<2>
    SLICE_X14Y35.CMUX    Tilo                  0.310   GPRF_Inst/sg_tmp_rd_data_31<0>37
                                                       GPRF_Inst/sg_tmp_rd_data_31<0>37_G
                                                       GPRF_Inst/sg_tmp_rd_data_31<0>37
    SLICE_X12Y35.B1      net (fanout=3)        0.682   GPRF_Inst/sg_tmp_rd_data_31<0>37
    SLICE_X12Y35.B       Tilo                  0.080   pm_fetch_dec_Inst/gp_reg_tmp<1>
                                                       GPRF_Inst/sg_tmp_rd_data_31<0>295
    SLICE_X11Y38.B4      net (fanout=26)       0.744   reg_rd_out<0>
    SLICE_X11Y38.B       Tilo                  0.080   N210
                                                       ALU_Inst/neg_op_carry_2_and00001
    SLICE_X11Y38.A5      net (fanout=4)        0.172   ALU_Inst/neg_op_carry<2>
    SLICE_X11Y38.A       Tilo                  0.080   N210
                                                       ALU_Inst/alu_data_out_int_6_or000047
    SLICE_X11Y38.D3      net (fanout=2)        0.466   ALU_Inst/alu_data_out_int_6_or000047
    SLICE_X11Y38.D       Tilo                  0.080   N210
                                                       ALU_Inst/alu_data_out_int_6_or0000174_SW1
    SLICE_X10Y42.C5      net (fanout=2)        0.432   N210
    SLICE_X10Y42.C       Tilo                  0.080   IORegs_Inst/sreg<4>
                                                       ALU_Inst/alu_data_out_int_6_or0000174
    SLICE_X11Y43.A2      net (fanout=2)        0.552   alu_data_out<6>
    SLICE_X11Y43.A       Tilo                  0.080   pm_fetch_dec_Inst/irqack_int
                                                       pm_fetch_dec_Inst/skip_inst_start_SW0
    SLICE_X10Y67.A6      net (fanout=6)        1.012   N198
    SLICE_X10Y67.A       Tilo                  0.080   pm_fetch_dec_Inst/pc_for_interrupt<15>
                                                       pm_fetch_dec_Inst/pc_for_interrupt_not00011
    SLICE_X11Y68.C6      net (fanout=16)       0.401   pm_fetch_dec_Inst/pc_for_interrupt_not0001
    SLICE_X11Y68.CLK     Tas                   0.030   pm_fetch_dec_Inst/pc_for_interrupt<7>
                                                       pm_fetch_dec_Inst/pc_for_interrupt_6_rstpot
                                                       pm_fetch_dec_Inst/pc_for_interrupt_6
    -------------------------------------------------  ---------------------------
    Total                                      9.204ns (1.546ns logic, 7.658ns route)
                                                       (16.8% logic, 83.2% route)

--------------------------------------------------------------------------------
Slack (setup path):     -1.366ns (requirement - (data path - clock path skew + uncertainty))
  Source:               pm_fetch_dec_Inst/ld_st (FF)
  Destination:          pm_fetch_dec_Inst/pc_for_interrupt_6 (FF)
  Requirement:          8.000ns
  Data Path Delay:      9.187ns (Levels of Logic = 13)
  Clock Path Skew:      -0.144ns (1.017 - 1.161)
  Source Clock:         cp2_BUFGP rising at 0.000ns
  Destination Clock:    cp2_BUFGP rising at 8.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: pm_fetch_dec_Inst/ld_st to pm_fetch_dec_Inst/pc_for_interrupt_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X17Y39.AQ      Tcko                  0.326   pm_fetch_dec_Inst/lds_st
                                                       pm_fetch_dec_Inst/ld_st
    SLICE_X17Y45.D1      net (fanout=14)       0.827   pm_fetch_dec_Inst/ld_st
    SLICE_X17Y45.D       Tilo                  0.080   pm_fetch_dec_Inst/sts_st
                                                       pm_fetch_dec_Inst/nop_insert_st46
    SLICE_X16Y41.A3      net (fanout=16)       0.724   pm_fetch_dec_Inst/nop_insert_st46
    SLICE_X16Y41.A       Tilo                  0.080   pm_fetch_dec_Inst/instruction_reg<11>
                                                       pm_fetch_dec_Inst/idc_elpm_cmp_eq000011
    SLICE_X16Y41.D1      net (fanout=28)       0.606   pm_fetch_dec_Inst/N65
    SLICE_X16Y41.D       Tilo                  0.080   pm_fetch_dec_Inst/instruction_reg<11>
                                                       pm_fetch_dec_Inst/reg_rd_adr<2>60_SW2
    SLICE_X14Y37.C4      net (fanout=1)        0.528   N465
    SLICE_X14Y37.C       Tilo                  0.080   GPRF_Inst/register_file_9_not0001
                                                       pm_fetch_dec_Inst/reg_rd_adr<2>60
    SLICE_X14Y35.D6      net (fanout=100)      0.511   reg_rd_adr<2>
    SLICE_X14Y35.CMUX    Topdc                 0.313   GPRF_Inst/sg_tmp_rd_data_31<0>37
                                                       GPRF_Inst/sg_tmp_rd_data_31<0>37_F
                                                       GPRF_Inst/sg_tmp_rd_data_31<0>37
    SLICE_X12Y35.B1      net (fanout=3)        0.682   GPRF_Inst/sg_tmp_rd_data_31<0>37
    SLICE_X12Y35.B       Tilo                  0.080   pm_fetch_dec_Inst/gp_reg_tmp<1>
                                                       GPRF_Inst/sg_tmp_rd_data_31<0>295
    SLICE_X11Y38.B4      net (fanout=26)       0.744   reg_rd_out<0>
    SLICE_X11Y38.B       Tilo                  0.080   N210
                                                       ALU_Inst/neg_op_carry_2_and00001
    SLICE_X11Y38.A5      net (fanout=4)        0.172   ALU_Inst/neg_op_carry<2>
    SLICE_X11Y38.A       Tilo                  0.080   N210
                                                       ALU_Inst/alu_data_out_int_6_or000047
    SLICE_X10Y38.D3      net (fanout=2)        0.486   ALU_Inst/alu_data_out_int_6_or000047
    SLICE_X10Y38.D       Tilo                  0.080   N209
                                                       ALU_Inst/alu_data_out_int_6_or0000174_SW0
    SLICE_X10Y42.C6      net (fanout=2)        0.393   N209
    SLICE_X10Y42.C       Tilo                  0.080   IORegs_Inst/sreg<4>
                                                       ALU_Inst/alu_data_out_int_6_or0000174
    SLICE_X11Y43.A2      net (fanout=2)        0.552   alu_data_out<6>
    SLICE_X11Y43.A       Tilo                  0.080   pm_fetch_dec_Inst/irqack_int
                                                       pm_fetch_dec_Inst/skip_inst_start_SW0
    SLICE_X10Y67.A6      net (fanout=6)        1.012   N198
    SLICE_X10Y67.A       Tilo                  0.080   pm_fetch_dec_Inst/pc_for_interrupt<15>
                                                       pm_fetch_dec_Inst/pc_for_interrupt_not00011
    SLICE_X11Y68.C6      net (fanout=16)       0.401   pm_fetch_dec_Inst/pc_for_interrupt_not0001
    SLICE_X11Y68.CLK     Tas                   0.030   pm_fetch_dec_Inst/pc_for_interrupt<7>
                                                       pm_fetch_dec_Inst/pc_for_interrupt_6_rstpot
                                                       pm_fetch_dec_Inst/pc_for_interrupt_6
    -------------------------------------------------  ---------------------------
    Total                                      9.187ns (1.549ns logic, 7.638ns route)
                                                       (16.9% logic, 83.1% route)

--------------------------------------------------------------------------------

Hold Paths: TS_cp2 = PERIOD TIMEGRP "cp2" 8 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack (hold path):      0.353ns (requirement - (clock path skew + uncertainty - data path))
  Source:               pm_fetch_dec_Inst/pc_high_0 (FF)
  Destination:          pm_fetch_dec_Inst/program_counter_tmp_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.381ns (Levels of Logic = 0)
  Clock Path Skew:      0.028ns (0.467 - 0.439)
  Source Clock:         cp2_BUFGP rising at 8.000ns
  Destination Clock:    cp2_BUFGP rising at 8.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: pm_fetch_dec_Inst/pc_high_0 to pm_fetch_dec_Inst/program_counter_tmp_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X13Y56.BQ      Tcko                  0.300   pm_fetch_dec_Inst/pc_high<2>
                                                       pm_fetch_dec_Inst/pc_high_0
    SLICE_X15Y57.AX      net (fanout=6)        0.245   pm_fetch_dec_Inst/pc_high<0>
    SLICE_X15Y57.CLK     Tckdi       (-Th)     0.164   pm_fetch_dec_Inst/program_counter_tmp<11>
                                                       pm_fetch_dec_Inst/program_counter_tmp_8
    -------------------------------------------------  ---------------------------
    Total                                      0.381ns (0.136ns logic, 0.245ns route)
                                                       (35.7% logic, 64.3% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.371ns (requirement - (clock path skew + uncertainty - data path))
  Source:               pm_fetch_dec_Inst/ret_st3 (FF)
  Destination:          pm_fetch_dec_Inst/nret_st0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.395ns (Levels of Logic = 1)
  Clock Path Skew:      0.024ns (0.442 - 0.418)
  Source Clock:         cp2_BUFGP rising at 8.000ns
  Destination Clock:    cp2_BUFGP rising at 8.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: pm_fetch_dec_Inst/ret_st3 to pm_fetch_dec_Inst/nret_st0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y48.CQ      Tcko                  0.318   pm_fetch_dec_Inst/ret_st3
                                                       pm_fetch_dec_Inst/ret_st3
    SLICE_X16Y48.D6      net (fanout=2)        0.227   pm_fetch_dec_Inst/ret_st3
    SLICE_X16Y48.CLK     Tah         (-Th)     0.150   pm_fetch_dec_Inst/nret_st0
                                                       pm_fetch_dec_Inst/nret_st0_or00001
                                                       pm_fetch_dec_Inst/nret_st0
    -------------------------------------------------  ---------------------------
    Total                                      0.395ns (0.168ns logic, 0.227ns route)
                                                       (42.5% logic, 57.5% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.377ns (requirement - (clock path skew + uncertainty - data path))
  Source:               pm_fetch_dec_Inst/pc_high_5 (FF)
  Destination:          pm_fetch_dec_Inst/program_counter_high_fr_5 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.389ns (Levels of Logic = 0)
  Clock Path Skew:      0.012ns (0.128 - 0.116)
  Source Clock:         cp2_BUFGP rising at 8.000ns
  Destination Clock:    cp2_BUFGP rising at 8.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: pm_fetch_dec_Inst/pc_high_5 to pm_fetch_dec_Inst/program_counter_high_fr_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y56.CQ      Tcko                  0.318   pm_fetch_dec_Inst/pc_high<6>
                                                       pm_fetch_dec_Inst/pc_high_5
    SLICE_X10Y58.BX      net (fanout=6)        0.248   pm_fetch_dec_Inst/pc_high<5>
    SLICE_X10Y58.CLK     Tckdi       (-Th)     0.177   pm_fetch_dec_Inst/program_counter_high_fr<7>
                                                       pm_fetch_dec_Inst/program_counter_high_fr_5
    -------------------------------------------------  ---------------------------
    Total                                      0.389ns (0.141ns logic, 0.248ns route)
                                                       (36.2% logic, 63.8% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cp2 = PERIOD TIMEGRP "cp2" 8 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 6.450ns (period - (min high pulse limit / (high pulse / period)))
  Period: 8.000ns
  High pulse: 4.000ns
  High pulse limit: 0.775ns (Tospwh)
  Physical resource: pm_fetch_dec_Inst/irqackad_int_0_1/SR
  Logical resource: pm_fetch_dec_Inst/irqackad_int_0_1/SR
  Location pin: OLOGIC_X0Y121.SR
  Clock network: BP_Inst/ireset_inv
--------------------------------------------------------------------------------
Slack: 6.450ns (period - (min high pulse limit / (high pulse / period)))
  Period: 8.000ns
  High pulse: 4.000ns
  High pulse limit: 0.775ns (Tospwh)
  Physical resource: pm_fetch_dec_Inst/irqackad_int_1_1/SR
  Logical resource: pm_fetch_dec_Inst/irqackad_int_1_1/SR
  Location pin: OLOGIC_X0Y130.SR
  Clock network: BP_Inst/ireset_inv
--------------------------------------------------------------------------------
Slack: 6.450ns (period - (min high pulse limit / (high pulse / period)))
  Period: 8.000ns
  High pulse: 4.000ns
  High pulse limit: 0.775ns (Tospwh)
  Physical resource: pm_fetch_dec_Inst/irqackad_int_2_1/SR
  Logical resource: pm_fetch_dec_Inst/irqackad_int_2_1/SR
  Location pin: OLOGIC_X0Y128.SR
  Clock network: BP_Inst/ireset_inv
--------------------------------------------------------------------------------


1 constraint not met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock cp2
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
cp2            |    9.385|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 170  Score: 54513  (Setup/Max: 54513, Hold: 0)

Constraints cover 106838544 paths, 0 nets, and 6316 connections

Design statistics:
   Minimum period:   9.385ns{1}   (Maximum frequency: 106.553MHz)


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Sun Oct 03 11:56:26 2010 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 257 MB