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--------------------------------------------------------------------------------
Release 11.1 Trace  (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.

C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise
C:/EDAptability/coremultiplier/reference/avr/ise/ise_v5_cm2_one_syneda/ise_v5_cm2_one_syneda/ise_v5_cm2_one_syneda.ise
-intstyle ise -v 3 -s 3 -fastpaths -xml avr_core_cm2_top.twx
avr_core_cm2_top.ncd -o avr_core_cm2_top.twr avr_core_cm2_top.pcf -ucf
avr_core_cm2_top.ucf

Design file:              avr_core_cm2_top.ncd
Physical constraint file: avr_core_cm2_top.pcf
Device,package,speed:     xc5vlx50,ff324,-3 (PRODUCTION 1.64 2009-03-03, STEPPING level 0)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: TS_cp2 = PERIOD TIMEGRP "cp2" 5.3 ns HIGH 50%;

 412450 paths analyzed, 2880 endpoints analyzed, 1 failing endpoint
 1 timing error detected. (1 setup error, 0 hold errors, 0 component switching limit errors)
 Minimum period is   5.302ns.
--------------------------------------------------------------------------------
Slack (setup path):     -0.002ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1_13 (FF)
  Destination:          AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nirq_st0 (FF)
  Requirement:          5.300ns
  Data Path Delay:      5.092ns (Levels of Logic = 6)
  Clock Path Skew:      -0.175ns (0.995 - 1.170)
  Source Clock:         cp2_BUFGP rising at 0.000ns
  Destination Clock:    cp2_BUFGP rising at 5.300ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1_13 to AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nirq_st0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X13Y84.AQ      Tcko                  0.326   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1<14>
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1_13
    SLICE_X12Y85.A1      net (fanout=10)       0.835   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1<13>
    SLICE_X12Y85.A       Tilo                  0.080   AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_1_or0000137
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/idc_sleep_cmp_eq00001
    SLICE_X17Y90.A6      net (fanout=41)       0.634   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/N74
    SLICE_X17Y90.A       Tilo                  0.080   AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_2_or0000159
                                                       AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_0_or00011
    SLICE_X16Y86.D2      net (fanout=5)        0.754   AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_0_or0001
    SLICE_X16Y86.D       Tilo                  0.080   AVR_Core_cm2_Inst/alu_data_out<6>
                                                       AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_6_or0000179
    SLICE_X17Y86.D2      net (fanout=2)        0.664   AVR_Core_cm2_Inst/alu_data_out<6>
    SLICE_X17Y86.D       Tilo                  0.080   AVR_Core_cm2_Inst/ALU_Inst/alu_z_flag_out_int
                                                       AVR_Core_cm2_Inst/ALU_Inst/alu_z_flag_out_int_cmp_eq0000
    SLICE_X27Y70.B6      net (fanout=5)        0.981   AVR_Core_cm2_Inst/ALU_Inst/alu_z_flag_out_int
    SLICE_X27Y70.B       Tilo                  0.080   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt<10>
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_mux0002<0>1266
    SLICE_X27Y75.A5      net (fanout=19)       0.470   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/N13
    SLICE_X27Y75.CLK     Tas                   0.028   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nirq_st0
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nirq_st0_mux00011
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nirq_st0
    -------------------------------------------------  ---------------------------
    Total                                      5.092ns (0.754ns logic, 4.338ns route)
                                                       (14.8% logic, 85.2% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.014ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1_13 (FF)
  Destination:          AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_13 (FF)
  Requirement:          5.300ns
  Data Path Delay:      5.053ns (Levels of Logic = 6)
  Clock Path Skew:      -0.198ns (0.972 - 1.170)
  Source Clock:         cp2_BUFGP rising at 0.000ns
  Destination Clock:    cp2_BUFGP rising at 5.300ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1_13 to AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_13
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X13Y84.AQ      Tcko                  0.326   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1<14>
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1_13
    SLICE_X12Y85.A1      net (fanout=10)       0.835   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1<13>
    SLICE_X12Y85.A       Tilo                  0.080   AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_1_or0000137
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/idc_sleep_cmp_eq00001
    SLICE_X17Y90.A6      net (fanout=41)       0.634   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/N74
    SLICE_X17Y90.A       Tilo                  0.080   AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_2_or0000159
                                                       AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_0_or00011
    SLICE_X16Y86.D2      net (fanout=5)        0.754   AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_0_or0001
    SLICE_X16Y86.D       Tilo                  0.080   AVR_Core_cm2_Inst/alu_data_out<6>
                                                       AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_6_or0000179
    SLICE_X17Y86.D2      net (fanout=2)        0.664   AVR_Core_cm2_Inst/alu_data_out<6>
    SLICE_X17Y86.D       Tilo                  0.080   AVR_Core_cm2_Inst/ALU_Inst/alu_z_flag_out_int
                                                       AVR_Core_cm2_Inst/ALU_Inst/alu_z_flag_out_int_cmp_eq0000
    SLICE_X27Y70.B6      net (fanout=5)        0.981   AVR_Core_cm2_Inst/ALU_Inst/alu_z_flag_out_int
    SLICE_X27Y70.B       Tilo                  0.080   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt<10>
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_mux0002<0>1266
    SLICE_X27Y68.C6      net (fanout=19)       0.429   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/N13
    SLICE_X27Y68.CLK     Tas                   0.030   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt<14>
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_mux0002<13>1
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_13
    -------------------------------------------------  ---------------------------
    Total                                      5.053ns (0.756ns logic, 4.297ns route)
                                                       (15.0% logic, 85.0% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.018ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1_13 (FF)
  Destination:          AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_14 (FF)
  Requirement:          5.300ns
  Data Path Delay:      5.049ns (Levels of Logic = 6)
  Clock Path Skew:      -0.198ns (0.972 - 1.170)
  Source Clock:         cp2_BUFGP rising at 0.000ns
  Destination Clock:    cp2_BUFGP rising at 5.300ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1_13 to AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_14
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X13Y84.AQ      Tcko                  0.326   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1<14>
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1_13
    SLICE_X12Y85.A1      net (fanout=10)       0.835   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1<13>
    SLICE_X12Y85.A       Tilo                  0.080   AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_1_or0000137
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/idc_sleep_cmp_eq00001
    SLICE_X17Y90.A6      net (fanout=41)       0.634   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/N74
    SLICE_X17Y90.A       Tilo                  0.080   AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_2_or0000159
                                                       AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_0_or00011
    SLICE_X16Y86.D2      net (fanout=5)        0.754   AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_0_or0001
    SLICE_X16Y86.D       Tilo                  0.080   AVR_Core_cm2_Inst/alu_data_out<6>
                                                       AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_6_or0000179
    SLICE_X17Y86.D2      net (fanout=2)        0.664   AVR_Core_cm2_Inst/alu_data_out<6>
    SLICE_X17Y86.D       Tilo                  0.080   AVR_Core_cm2_Inst/ALU_Inst/alu_z_flag_out_int
                                                       AVR_Core_cm2_Inst/ALU_Inst/alu_z_flag_out_int_cmp_eq0000
    SLICE_X27Y70.B6      net (fanout=5)        0.981   AVR_Core_cm2_Inst/ALU_Inst/alu_z_flag_out_int
    SLICE_X27Y70.B       Tilo                  0.080   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt<10>
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_mux0002<0>1266
    SLICE_X27Y68.D6      net (fanout=19)       0.427   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/N13
    SLICE_X27Y68.CLK     Tas                   0.028   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt<14>
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_mux0002<14>1
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_14
    -------------------------------------------------  ---------------------------
    Total                                      5.049ns (0.754ns logic, 4.295ns route)
                                                       (14.9% logic, 85.1% route)

--------------------------------------------------------------------------------

Hold Paths: TS_cp2 = PERIOD TIMEGRP "cp2" 5.3 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack (hold path):      0.239ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AVR_Core_cm2_Inst/pm_fetch_dec_Inst/rjmp_st (FF)
  Destination:          AVR_Core_cm2_Inst/pm_fetch_dec_Inst/rjmp_st_cml_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.388ns (Levels of Logic = 0)
  Clock Path Skew:      0.149ns (1.200 - 1.051)
  Source Clock:         cp2_BUFGP rising at 5.300ns
  Destination Clock:    cp2_BUFGP rising at 5.300ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/rjmp_st to AVR_Core_cm2_Inst/pm_fetch_dec_Inst/rjmp_st_cml_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y78.AQ      Tcko                  0.318   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/brxx_st
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/rjmp_st
    SLICE_X11Y80.AX      net (fanout=2)        0.234   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/rjmp_st
    SLICE_X11Y80.CLK     Tckdi       (-Th)     0.164   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/brxx_st_cml_1
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/rjmp_st_cml_1
    -------------------------------------------------  ---------------------------
    Total                                      0.388ns (0.154ns logic, 0.234ns route)
                                                       (39.7% logic, 60.3% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.240ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AVR_Core_cm2_Inst/pm_fetch_dec_Inst/program_counter_high_fr_4 (FF)
  Destination:          AVR_Core_cm2_Inst/pm_fetch_dec_Inst/program_counter_high_fr_cml_1_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.247ns (Levels of Logic = 0)
  Clock Path Skew:      0.007ns (0.107 - 0.100)
  Source Clock:         cp2_BUFGP rising at 5.300ns
  Destination Clock:    cp2_BUFGP rising at 5.300ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/program_counter_high_fr_4 to AVR_Core_cm2_Inst/pm_fetch_dec_Inst/program_counter_high_fr_cml_1_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X25Y71.BQ      Tcko                  0.300   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/program_counter_high_fr<6>
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/program_counter_high_fr_4
    SLICE_X24Y71.AX      net (fanout=2)        0.120   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/program_counter_high_fr<4>
    SLICE_X24Y71.CLK     Tckdi       (-Th)     0.173   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/program_counter_high_fr_cml_1<7>
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/program_counter_high_fr_cml_1_4
    -------------------------------------------------  ---------------------------
    Total                                      0.247ns (0.127ns logic, 0.120ns route)
                                                       (51.4% logic, 48.6% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.240ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AVR_Core_cm2_Inst/GPRF_Inst/register_file_7_2 (FF)
  Destination:          AVR_Core_cm2_Inst/GPRF_Inst/register_file_cml_1_7_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.250ns (Levels of Logic = 0)
  Clock Path Skew:      0.010ns (0.144 - 0.134)
  Source Clock:         cp2_BUFGP rising at 5.300ns
  Destination Clock:    cp2_BUFGP rising at 5.300ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: AVR_Core_cm2_Inst/GPRF_Inst/register_file_7_2 to AVR_Core_cm2_Inst/GPRF_Inst/register_file_cml_1_7_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X13Y99.DQ      Tcko                  0.300   AVR_Core_cm2_Inst/GPRF_Inst/register_file_7_2
                                                       AVR_Core_cm2_Inst/GPRF_Inst/register_file_7_2
    SLICE_X12Y99.CX      net (fanout=3)        0.120   AVR_Core_cm2_Inst/GPRF_Inst/register_file_7_2
    SLICE_X12Y99.CLK     Tckdi       (-Th)     0.170   AVR_Core_cm2_Inst/GPRF_Inst/register_file_cml_1_7_3
                                                       AVR_Core_cm2_Inst/GPRF_Inst/register_file_cml_1_7_2
    -------------------------------------------------  ---------------------------
    Total                                      0.250ns (0.130ns logic, 0.120ns route)
                                                       (52.0% logic, 48.0% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cp2 = PERIOD TIMEGRP "cp2" 5.3 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 4.246ns (period - (min low pulse limit / (low pulse / period)))
  Period: 5.300ns
  Low pulse: 2.650ns
  Low pulse limit: 0.527ns (Trpw)
  Physical resource: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/dex_adrreg_d_latched<4>/SR
  Logical resource: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/dex_adrreg_d_latched_4/SR
  Location pin: SLICE_X1Y74.SR
  Clock network: AVR_Core_cm2_Inst/BP_Inst/ireset_inv
--------------------------------------------------------------------------------
Slack: 4.246ns (period - (min high pulse limit / (high pulse / period)))
  Period: 5.300ns
  High pulse: 2.650ns
  High pulse limit: 0.527ns (Trpw)
  Physical resource: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/dex_adrreg_d_latched<4>/SR
  Logical resource: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/dex_adrreg_d_latched_4/SR
  Location pin: SLICE_X1Y74.SR
  Clock network: AVR_Core_cm2_Inst/BP_Inst/ireset_inv
--------------------------------------------------------------------------------
Slack: 4.246ns (period - (min low pulse limit / (low pulse / period)))
  Period: 5.300ns
  Low pulse: 2.650ns
  Low pulse limit: 0.527ns (Trpw)
  Physical resource: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/ramadr_int<15>/SR
  Logical resource: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/ramadr_int_15/SR
  Location pin: SLICE_X2Y69.SR
  Clock network: AVR_Core_cm2_Inst/BP_Inst/ireset_inv
--------------------------------------------------------------------------------


1 constraint not met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock cp2
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
cp2            |    5.302|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 1  Score: 2  (Setup/Max: 2, Hold: 0)

Constraints cover 412450 paths, 0 nets, and 7964 connections

Design statistics:
   Minimum period:   5.302ns{1}   (Maximum frequency: 188.608MHz)


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Thu Oct 07 20:29:46 2010 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 264 MB