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Todo:

Remember to change timing constants in debouncer before real synthesis.
Remember to change timing constants in displayhex before real synthesis.

Remember to remove "hard coded" program in core before real synthesis.


Features to add:
External memory interface (done)
DLL clock (done; have to run at 40MHz 
  for RAM to work right)
Condition register (Z, C, O) (done)
TSTA
CMP XXXX (done)
SZ, SNZ, SC, SNC, SOV, SNO (done)

The UART is hard coded to 57600/8/N/1
You can access it via memory or use it when in load mode to load words (high byte first, then low byte)

Memory map:
FF0 - Switch register (read/write)
FF1 - Actual switches (low 8 bit) + enter key (top bit) (read only)
FFE - UART Status (xmit buf empty, xmit shift empty, frame err, overflow, available, + 11 0 bits)
FFF - Uart character (read/write) on receive, bit 15 is character available flag





Switches:
0 - Reset
1 - Select (cycles LEDs from 0 to 5)
2 - Action (see below)
3 - Enter (see below) [ closest to slide switches]


LEDs:
7 - Q output (was running)
6 - Running (was 7)
5 - Run/Stop entry mode
4 - Step mode
3 - Deposit (Register Select)
2 - Examine (Deposit)
1 - Load PC (Examine)
0 - Register Select (Load PC)

Old version:
State (from LED)        Action          Enter
5                       Run/Stop        Enter
4                       Step            Enter
3                       Select register Enter
2                       Deposit         Enter
1                       Examine         Enter
0                        Load PC         Enter

New version:
State (from LED)        Action          Enter
5                       Run/Stop        Enter
4                       Step            Enter
3                       Deposit         Enter
2                       Examine         Enter
1                       Load PC         Enter
0                        Select register Enter


When enter is held down, regsel is temporarily set to switch
in all modes 
 

Decimal points on display (#4 is leftmost):
4 - IR (PC)
3 - SW (IR)
2 - AC
1 - PC (SW)

F/CP1 - PC -> Z, MAR
F/CP2 - [M] -> IR  (dep/exam sets IR to HLT)
F/CP3 - 1 -> Y
F/CP4 - Y+Z -> PC
F/CP5 - execute
F/CP6 - execute
F/CP7 - execute
F/CP8 - execute


###

Flags 
0=overflow
1=zero
2=carry (set on add and shift)

skip=0x0010+3 bit condition
So 9 = SOV
A=SZ
C=SC
But you can mix these for "or" conditions
So E=SZC  (skip zero OR carry)

if bit 3 is set (+8) then reverse flags
before test, so SZ becomes SNZ

Possible instructions:
INC/DEC (memory)
Call/return with stack or link