Subversion Repositories bustap-jtag

#Please do not modify this file by hand
XmpVersion: 14.3
VerMgmt: 14.3
IntStyle: default
Flow: ise
ModuleSearchPath: ../../../rtl/xilinx/pcores/bustap_jtag_v1_00_a/../../../
MHS File: zynq_bram.mhs
Architecture: zynq
Device: xc7z020
Package: clg484
SpeedGrade: -1
UserCmd1: 
UserCmd1Type: 0
UserCmd2: 
UserCmd2Type: 0
GenSimTB: 0
SdkExportBmmBit: 0
SdkExportDir: SDK/SDK_Export
InsertNoPads: 0
WarnForEAArch: 1
HdlLang: VERILOG
SimModel: BEHAVIORAL
ExternalMemSim: 0
UcfFile: data/zynq_bram.ucf
EnableParTimingError: 1
ShowLicenseDialog: 1
BInfo: 
LockAddr: PL_bram_ctrl,C_S_AXI_BASEADDR
Processor: PS
ElfImp: 
ElfSim: