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[/] [bustap-jtag/] [trunk/] [rtl/] [xilinx/] [pcores/] [bustap_jtag_v1_00_a/] [data/] [bustap_jtag_v2_1_0.mpd] - Rev 18

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###################################################################
##
## Name     : bustap_jtag
## Desc     : Microprocessor Peripheral Description
##          : Automatically generated by PsfUtility
##
###################################################################

BEGIN bustap_jtag

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION STYLE = MIX
OPTION DESC = AXI BUS TAP
OPTION LONG_DESC = AXI BUS TAP JTAG
OPTION HDL = MIXED
OPTION RUN_NGCBUILD = TRUE

## MON_AXI Bus Interfaces
BUS_INTERFACE BUS = MON_AXI, BUS_STD = AXI, BUS_TYPE = MONITOR

## MON_AXI Generics for VHDL or Parameters for Verilog
PARAMETER C_ADDR_WIDTH = 32, DT = integer, ASSIGNMENT = CONSTANT, BUS = MON_AXI
PARAMETER C_DATA_WIDTH = 32, DT = integer, ASSIGNMENT = CONSTANT, BUS = MON_AXI
PARAMETER C_PROTOCOL = AXI4Lite, DT = string, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, BUS = MON_AXI

## MON_AXI Ports
PORT ACLK = "", BUS = MON_AXI, DIR = I, SIGIS = CLK
PORT ARESETN = ARESETN, BUS = MON_AXI, DIR = I, SIGIS = RST
PORT AWADDR = AWADDR, BUS = MON_AXI, DIR = I, VEC = [(C_ADDR_WIDTH-1):0]
PORT AWPROT = AWPROT, BUS = MON_AXI, DIR = I, VEC = [2:0]
PORT AWVALID = AWVALID, BUS = MON_AXI, DIR = I
PORT AWREADY = AWREADY, BUS = MON_AXI, DIR = I
PORT WDATA = WDATA, BUS = MON_AXI, DIR = I, VEC = [(C_DATA_WIDTH-1):0]
PORT WSTRB = WSTRB, BUS = MON_AXI, DIR = I, VEC = [((C_DATA_WIDTH/8) -1):0]
PORT WVALID = WVALID, BUS = MON_AXI, DIR = I
PORT WREADY = WREADY, BUS = MON_AXI, DIR = I
PORT BRESP = BRESP, BUS = MON_AXI, DIR = I, VEC = [1:0]
PORT BVALID = BVALID, BUS = MON_AXI, DIR = I
PORT BREADY = BREADY, BUS = MON_AXI, DIR = I
PORT ARADDR = ARADDR, BUS = MON_AXI, DIR = I, VEC = [(C_ADDR_WIDTH-1):0
PORT ARPROT = ARPROT, BUS = MON_AXI, DIR = I, VEC = [2:0]
PORT ARVALID = ARVALID, BUS = MON_AXI, DIR = I
PORT ARREADY = ARREADY, BUS = MON_AXI, DIR = I
PORT RDATA = RDATA, BUS = MON_AXI, DIR = I, VEC = [(C_DATA_WIDTH-1):0]
PORT RRESP = RRESP, BUS = MON_AXI, DIR = I, VEC = [1:0]
PORT RVALID = RVALID, BUS = MON_AXI, DIR = I
PORT RREADY = RREADY, BUS = MON_AXI, DIR = I

## CHIPSCOPE ICON Ports
PORT CHIPSCOPE_ICON_CONTROL0 = "", DIR = I, VEC = [35:0], ASSIGNMENT = OPTIONAL
PORT CHIPSCOPE_ICON_CONTROL1 = "", DIR = I, VEC = [35:0], ASSIGNMENT = OPTIONAL
PORT CHIPSCOPE_ICON_CONTROL2 = "", DIR = I, VEC = [35:0], ASSIGNMENT = OPTIONAL

END

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