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`include "../bench/timescale.v"
// this key_schedule module
module key_schedule(clk,rst,start,i_ck,busy,done,o_kk);
        input             clk;
        input             rst;
        input             start;
        input  [ 8*8-1:0] i_ck;
        output            busy;
        output            done;
        output [56*8-1:0] o_kk;
 
        reg    [56*8-1:0] o_kk;
        reg    [     2:0] cnt;
 
        wire   [ 8*8-1:0] ik;
        wire   [ 8*8-1:0] okd;
        wire   [ 8*8-1:0] oki;
        reg    [ 8*8-1:0] ok_d;
        reg               done;
        reg               busy;
 
        key_perm kpo(.i_key(ok_d), .o_key(okd));
        key_perm kpi(.i_key(i_ck), .o_key(oki));
 
        always @(posedge clk)
        begin
                done <= 1'h0;
                if(rst)
                begin
                        o_kk <= 448'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
                        cnt  <= 3'h0;
                        ok_d <= 64'h0000000000000000;
                        busy <= 1'h0;
                end
                else 
                begin
                        if(cnt==3'h0 && busy)
                        begin
                                busy <= 1'h0;
                                done <= 1'h1;
                        end
 
 
                        if(start & ~busy)
                        begin
                                cnt  <= 3'h5;
                                o_kk <= {o_kk [(6*8)*8-1:8*0], i_ck};
                                busy <= 1'h1;
                                ok_d <= oki;
                                o_kk <= {o_kk [(6*8)*8-1:8*0],
                                                i_ck ^ 64'h0606060606060606};
                        end
 
                        if(busy)
                        begin
                                o_kk <= {o_kk [(6*8)*8-1:8*0],
                                                ok_d ^ { 
                                                        5'h00, cnt,
                                                        5'h00, cnt,
                                                        5'h00, cnt,
                                                        5'h00, cnt,
                                                        5'h00, cnt,
                                                        5'h00, cnt,
                                                        5'h00, cnt,
                                                        5'h00, cnt 
                                                      } 
                                         };
                                if(cnt!=3'h0)
                                        cnt  <= cnt - 3'h1;
                                ok_d <= okd;
                        end
                end
        end
endmodule