Subversion Repositories ddr2_sdram

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--*****************************************************************************
--   ____  ____
--  /   /\/   /
-- /___/  \  /   Vendor             : Xilinx
-- \   \   \/    Version	    : 3.6.1
--  \   \        Application	    : MIG
--  /   /        Filename           : DDR2_Ram_Core_fifo_0_wr_en_0.vhd
-- /___/   /\    Date Last Modified : $Date: 2010/11/26 18:25:42 $
-- \   \  /  \   Date Created       : Mon May 2 2005
--  \___\/\___\
-- Device      : Spartan-3/3A/3A-DSP
-- Design Name : DDR2 SDRAM
-- Purpose     : This module generate the write enable signal to the fifos,
--               which are driven by posedge of data strobe
--*****************************************************************************
 
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use UNISIM.VCOMPONENTS.all;
 
entity DDR2_Ram_Core_fifo_1_wr_en_0 is
  port (
    clk             : in  std_logic;
    rst_dqs_delay_n : in  std_logic;
    reset           : in  std_logic;
    din             : in  std_logic;
    dout            : out std_logic
    );
end DDR2_Ram_Core_fifo_1_wr_en_0;
 
architecture arc of DDR2_Ram_Core_fifo_1_wr_en_0 is
 
  signal din_delay     : std_ulogic;
  signal tie_high      : std_ulogic;
  signal dout0         : std_ulogic;
  signal rst_dqs_delay : std_logic;
 
begin
 
  rst_dqs_delay <= not rst_dqs_delay_n;
  dout0         <= din and rst_dqs_delay_n;
  dout          <= rst_dqs_delay or din_delay;
  tie_high      <= '1';
 
  delay_ff_1 : FDCE
    port map (
      Q   => din_delay,
      C   => clk,
      CE  => tie_high,
      CLR => reset,
      D   => dout0
      );
 
end arc;