Subversion Repositories ddr2_sdram

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--*****************************************************************************
--   ____  ____
--  /   /\/   /
-- /___/  \  /   Vendor             : Xilinx
-- \   \   \/    Version	    : 3.6.1
--  \   \        Application	    : MIG
--  /   /        Filename           : DDR2_Ram_Core_infrastructure.vhd
-- /___/   /\    Date Last Modified : $Date: 2010/11/26 18:25:42 $
-- \   \  /  \   Date Created       : Mon May 2 2005
--  \___\/\___\
-- Device      : Spartan-3/3A/3A-DSP
-- Design Name : DDR2 SDRAM
-- Purpose     :
--*****************************************************************************
 
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use UNISIM.VCOMPONENTS.all;
 
 
entity DDR2_Ram_Core_infrastructure is
  port(
    delay_sel_val1_val : out std_logic_vector(4 downto 0);
    delay_sel_val      : in  std_logic_vector(4 downto 0);
    rst_calib1         : in  std_logic;
    clk_int            : in  std_logic;
    -- debug signals
    dbg_delay_sel      : out std_logic_vector(4 downto 0);
    dbg_rst_calib      : out std_logic
    );
end DDR2_Ram_Core_infrastructure;
 
architecture arc of DDR2_Ram_Core_infrastructure is
 
  signal delay_sel_val1 : std_logic_vector(4 downto 0);
  signal rst_calib1_r1  : std_logic;
  signal rst_calib1_r2  : std_logic;
 
begin
 
  delay_sel_val1_val <= delay_sel_val1;
  dbg_delay_sel      <= delay_sel_val1;
  dbg_rst_calib      <= rst_calib1_r2;
 
  process(clk_int)
  begin
    if clk_int 'event and clk_int = '0' then
      rst_calib1_r1    <= rst_calib1;
    end if;
  end process;
 
  process(clk_int)
  begin
    if clk_int 'event and clk_int = '1' then
      rst_calib1_r2    <= rst_calib1_r1;
    end if;
  end process;
 
  process(clk_int)
  begin
    if clk_int 'event and clk_int = '1' then
      if (rst_calib1_r2 = '0') then
        delay_sel_val1 <= delay_sel_val;
      else
        delay_sel_val1 <= delay_sel_val1;
      end if;
    end if;
  end process;
 
end arc;