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[/] [dma_axi/] [trunk/] [src/] [dma_axi32/] [dma_axi32_core0_axim_timeout.v] - Rev 4
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///////////////////////////////////////////////////////////////////// //// //// //// Author: Eyal Hochberg //// //// eyal@provartec.com //// //// //// //// Downloaded from: http://www.opencores.org //// ///////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2010 Provartec LTD //// //// www.provartec.com //// //// info@provartec.com //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer.//// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation.//// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more//// //// details. http://www.gnu.org/licenses/lgpl.html //// //// //// ///////////////////////////////////////////////////////////////////// //--------------------------------------------------------- //-- File generated by RobustVerilog parser //-- Version: 1.0 //-- Invoked Fri Mar 25 23:34:52 2011 //-- //-- Source file: dma_core_axim_timeout.v //--------------------------------------------------------- module dma_axi32_core0_axim_timeout(clk,reset,VALID,READY,ID,axim_timeout_num,axim_timeout); input clk; input reset; input VALID; input READY; input [`CMD_BITS-1:0] ID; output [2:0] axim_timeout_num; output axim_timeout; reg [`TIMEOUT_BITS-1:0] counter; assign axim_timeout_num = ID[2:0]; assign axim_timeout = (counter == 'd0); always @(posedge clk or posedge reset) if (reset) counter <= #1 {`TIMEOUT_BITS{1'b1}}; else if (VALID & READY) counter <= #1 {`TIMEOUT_BITS{1'b1}}; else if (VALID) counter <= #1 counter - 1'b1; endmodule