Subversion Repositories dmt_tx

 
from myhdl import *
 
def cadd(a_re, a_im, b_re, b_im, y_re, y_im, overflow, width=8):
  '''Complex add
 
  I/O pins:
  =========
  a         : input a
  b         : input b
  y         : output a + b
  overflow  : signal overflow
 
  parameter:
  ==========
  width : data width for input and output
  '''
  @always_comb
  def logic():
    m = 2**(width-1)
 
    #
    # Real value calculation
    if (a_re + b_re) >= m:
      y_re.next = m-1
      ovfl_re = True
 
    elif (a_re + b_re) < -m:
      y_re.next = -m
      ovfl_re = True
 
    else:
      y_re.next = a_re + b_re
      ovfl_re = False
 
    #
    # Imaginary add
    if (a_im + b_im) >= m:
      y_im.next = m-1
      ovfl_im = True
 
    elif (a_im + b_im) < -m:
      y_im.next = -m
      ovfl_im = True
 
    else:
      y_im.next = a_im + b_im
      ovfl_im = False
 
    overflow.next = ovfl_re or ovfl_im
 
  return instances()
 
 
def csub(a_re, a_im, b_re, b_im, y_re, y_im, overflow, width=8):
 
  @always_comb
  def logic():
    m = 2**(width-1)
 
    #
    # Real value calculation
    if (a_re - b_re) >= m:
      y_re.next = m-1
      ovfl_re = True
 
    elif (a_re - b_re) < -m:
      y_re.next = -m
      ovfl_re = True
 
    else:
      y_re.next = a_re - b_re
      ovfl_re = False
 
    #
    # Imaginary add
    if (a_im - b_im) >= m:
      y_im.next = m-1
      ovfl_im = True
 
    elif (a_im - b_im) < -m:
      y_im.next = -m
      ovfl_im = True
 
    else:
      y_im.next = a_im - b_im
      ovfl_im = False
 
    overflow.next = ovfl_re or ovfl_im
 
  return instances()