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[/] [fluid_core_2/] [trunk/] [bench/] [tb_Test_Bed.v] - Rev 3
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////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2014-2015 Azmath Moosa //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 3 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// `timescale 1ns / 1ps module tb_Test_Bed; // Inputs reg Clk; reg RST; reg [0:3] Interrupt; // Instantiate the Unit Under Test (UUT) Test_Bed uut ( .Clk(Clk), .RST(RST), .Interrupt(Interrupt) ); initial begin // Initialize Inputs Clk = 0; RST = 1; Interrupt = 0; // Wait 100 ns for global reset to finish #60; RST = 0; // Add stimulus here end always begin #50 Clk = ~Clk; end // always begin // #3400 Interrupt[1] <= 1; // #100 Interrupt[1] <= 0; // end endmodule