Subversion Repositories fluid_core_2

Release 14.5 - xst P.58f (nt64)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.41 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.42 secs
 
--> Reading design: FluidCore.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
        9.1) Device utilization summary
        9.2) Partition Resource Summary
        9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "FluidCore.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "FluidCore"
Output Format                      : NGC
Target Device                      : xc3s500e-4-fg320

---- Source Options
Top Module Name                    : FluidCore
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : Yes
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : Yes
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : LUT
Automatic Register Balancing       : Yes

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 24
Register Duplication               : YES
Move First FlipFlop Stage          : YES
Move Last FlipFlop Stage           : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : True
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 2
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "Shifter.v" in library work
Compiling verilog include file "Configuration.v"
Compiling verilog file "int_ALU.v" in library work
Compiling verilog include file "Configuration.v"
Module <Shifter> compiled
Compiling verilog file "WB_Stage.v" in library work
Compiling verilog include file "Configuration.v"
Module <int_ALU> compiled
Compiling verilog file "uOP_Store.v" in library work
Compiling verilog include file "Configuration.v"
Module <WB_Stage> compiled
Compiling verilog file "Staller.v" in library work
Compiling verilog include file "Configuration.v"
Module <uOP_Store> compiled
Compiling verilog file "Reg_Hist.v" in library work
Compiling verilog include file "Configuration.v"
Module <Staller> compiled
Compiling verilog file "Reg_File.v" in library work
Compiling verilog include file "Configuration.v"
Module <Reg_Hist> compiled
Compiling verilog file "P_Reg.v" in library work
Compiling verilog include file "Configuration.v"
Module <Reg_File> compiled
Compiling verilog file "MEM_Stage.v" in library work
Compiling verilog include file "Configuration.v"
Module <P_Reg> compiled
Compiling verilog file "interrupt_unit.v" in library work
Compiling verilog include file "Configuration.v"
Module <MEM_Stage> compiled
Compiling verilog file "IF_Stage.v" in library work
Compiling verilog include file "Configuration.v"
Module <interrupt_unit> compiled
Compiling verilog file "ID_Stage.v" in library work
Compiling verilog include file "Configuration.v"
Module <IF_Stage> compiled
Compiling verilog file "EX_Stage.v" in library work
Compiling verilog include file "Configuration.v"
Module <ID_Stage> compiled
Compiling verilog file "FluidCore.v" in library work
Compiling verilog include file "Configuration.v"
Module <EX_Stage> compiled
Module <FluidCore> compiled
No errors in compilation
Analysis of file <"FluidCore.prj"> succeeded.
 

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for module <FluidCore> in library <work>.

Analyzing hierarchy for module <Staller> in library <work>.

Analyzing hierarchy for module <P_Reg> in library <work> with parameters.
        p_reg_w = "00000000000000000000000000001111"

Analyzing hierarchy for module <P_Reg> in library <work> with parameters.
        p_reg_w = "00000000000000000000000001110110"

Analyzing hierarchy for module <P_Reg> in library <work> with parameters.
        p_reg_w = "00000000000000000000000001001000"

Analyzing hierarchy for module <P_Reg> in library <work> with parameters.
        p_reg_w = "00000000000000000000000000100110"

Analyzing hierarchy for module <IF_Stage> in library <work>.

Analyzing hierarchy for module <Reg_File> in library <work>.

Analyzing hierarchy for module <Reg_Hist> in library <work>.

Analyzing hierarchy for module <ID_Stage> in library <work>.

Analyzing hierarchy for module <uOP_Store> in library <work>.

Analyzing hierarchy for module <EX_Stage> in library <work>.

Analyzing hierarchy for module <MEM_Stage> in library <work>.

Analyzing hierarchy for module <WB_Stage> in library <work>.

Analyzing hierarchy for module <interrupt_unit> in library <work>.

Analyzing hierarchy for module <int_ALU> in library <work>.

Analyzing hierarchy for module <Shifter> in library <work>.


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <FluidCore>.
Module <FluidCore> is correct for synthesis.
 
Analyzing module <Staller> in library <work>.
Module <Staller> is correct for synthesis.
 
Analyzing module <P_Reg.1> in library <work>.
        p_reg_w = 32'sb00000000000000000000000000001111
Module <P_Reg.1> is correct for synthesis.
 
Analyzing module <P_Reg.2> in library <work>.
        p_reg_w = 32'sb00000000000000000000000001110110
Module <P_Reg.2> is correct for synthesis.
 
Analyzing module <P_Reg.3> in library <work>.
        p_reg_w = 32'sb00000000000000000000000001001000
Module <P_Reg.3> is correct for synthesis.
 
Analyzing module <P_Reg.4> in library <work>.
        p_reg_w = 32'sb00000000000000000000000000100110
Module <P_Reg.4> is correct for synthesis.
 
Analyzing module <IF_Stage> in library <work>.
Module <IF_Stage> is correct for synthesis.
 
Analyzing module <Reg_File> in library <work>.
Module <Reg_File> is correct for synthesis.
 
Analyzing module <Reg_Hist> in library <work>.
Module <Reg_Hist> is correct for synthesis.
 
Analyzing module <ID_Stage> in library <work>.
Module <ID_Stage> is correct for synthesis.
 
Analyzing module <uOP_Store> in library <work>.
Module <uOP_Store> is correct for synthesis.
 
Analyzing module <EX_Stage> in library <work>.
Module <EX_Stage> is correct for synthesis.
 
Analyzing module <int_ALU> in library <work>.
Module <int_ALU> is correct for synthesis.
 
Analyzing module <Shifter> in library <work>.
Module <Shifter> is correct for synthesis.
 
Analyzing module <MEM_Stage> in library <work>.
Module <MEM_Stage> is correct for synthesis.
 
Analyzing module <WB_Stage> in library <work>.
Module <WB_Stage> is correct for synthesis.
 
Analyzing module <interrupt_unit> in library <work>.
        Calling function <log2>.
        Calling function <log2>.
INFO:Xst:1607 - Contents of array <isr_vectors> may be accessed with an index that does not cover the full array size.
Module <interrupt_unit> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <Staller>.
    Related source file is "Staller.v".
    Found 9-bit register for signal <bubble_reg>.
    Found 1-bit register for signal <stall_reg>.
    Summary:
        inferred  10 D-type flip-flop(s).
Unit <Staller> synthesized.


Synthesizing Unit <P_Reg_1>.
    Related source file is "P_Reg.v".
    Found 16-bit register for signal <pipeline_register>.
    Summary:
        inferred  16 D-type flip-flop(s).
Unit <P_Reg_1> synthesized.


Synthesizing Unit <P_Reg_2>.
    Related source file is "P_Reg.v".
    Found 119-bit register for signal <pipeline_register>.
    Summary:
        inferred 119 D-type flip-flop(s).
Unit <P_Reg_2> synthesized.


Synthesizing Unit <P_Reg_3>.
    Related source file is "P_Reg.v".
    Found 73-bit register for signal <pipeline_register>.
    Summary:
        inferred  73 D-type flip-flop(s).
Unit <P_Reg_3> synthesized.


Synthesizing Unit <P_Reg_4>.
    Related source file is "P_Reg.v".
    Found 39-bit register for signal <pipeline_register>.
    Summary:
        inferred  39 D-type flip-flop(s).
Unit <P_Reg_4> synthesized.


Synthesizing Unit <IF_Stage>.
    Related source file is "IF_Stage.v".
    Found 4-bit tristate buffer for signal <stkFlag>.
    Found 10-bit 4-to-1 multiplexer for signal <$varindex0000> created at line 63.
    Found 6-bit adder carry out for signal <add0000$addsub0000> created at line 47.
    Found 1-bit register for signal <HLT>.
    Found 16-bit register for signal <IR>.
    Found 6-bit register for signal <PC>.
    Found 6-bit adder for signal <PC$addsub0000> created at line 55.
    Found 40-bit register for signal <PCStack>.
    Found 2-bit updown counter for signal <PCStackPtr>.
    Found 2-bit adder for signal <PCStackPtr$add0000> created at line 43.
    Summary:
        inferred   1 Counter(s).
        inferred  63 D-type flip-flop(s).
        inferred   3 Adder/Subtractor(s).
        inferred  10 Multiplexer(s).
        inferred   4 Tristate(s).
Unit <IF_Stage> synthesized.


Synthesizing Unit <Reg_File>.
    Related source file is "Reg_File.v".
WARNING:Xst:647 - Input <RST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 256-bit register for signal <registers>.
INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred for signal <registers>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time.
    Summary:
        inferred 256 D-type flip-flop(s).
        inferred  64 Multiplexer(s).
Unit <Reg_File> synthesized.


Synthesizing Unit <Reg_Hist>.
    Related source file is "Reg_Hist.v".
    Found 1-bit xor2 for signal <reg_src_a_1$xor0000> created at line 25.
    Found 1-bit xor2 for signal <reg_src_a_1$xor0001> created at line 25.
    Found 1-bit xor2 for signal <reg_src_a_1$xor0002> created at line 25.
    Found 1-bit xor2 for signal <reg_src_a_2$xor0000> created at line 26.
    Found 1-bit xor2 for signal <reg_src_a_2$xor0001> created at line 26.
    Found 1-bit xor2 for signal <reg_src_a_2$xor0002> created at line 26.
    Found 1-bit xor2 for signal <reg_src_b_1$xor0000> created at line 27.
    Found 1-bit xor2 for signal <reg_src_b_1$xor0001> created at line 27.
    Found 1-bit xor2 for signal <reg_src_b_1$xor0002> created at line 27.
    Found 1-bit xor2 for signal <reg_src_b_2$xor0000> created at line 28.
    Found 1-bit xor2 for signal <reg_src_b_2$xor0001> created at line 28.
    Found 1-bit xor2 for signal <reg_src_b_2$xor0002> created at line 28.
    Found 1-bit xor2 for signal <st_src_1$xor0000> created at line 29.
    Found 1-bit xor2 for signal <st_src_1$xor0001> created at line 29.
    Found 1-bit xor2 for signal <st_src_1$xor0002> created at line 29.
    Found 1-bit xor2 for signal <st_src_2$xor0000> created at line 30.
    Found 1-bit xor2 for signal <st_src_2$xor0001> created at line 30.
    Found 1-bit xor2 for signal <st_src_2$xor0002> created at line 30.
Unit <Reg_Hist> synthesized.


Synthesizing Unit <ID_Stage>.
    Related source file is "ID_Stage.v".
WARNING:Xst:647 - Input <RST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:737 - Found 32-bit latch for signal <buff_op_a>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <buff_op_b>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Unit <ID_Stage> synthesized.


Synthesizing Unit <uOP_Store>.
    Related source file is "uOP_Store.v".
    Found 338-bit register for signal <uOP_rom>.
INFO:Xst:738 - HDL ADVISOR - 338 flip-flops were inferred for signal <uOP_rom>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time.
    Summary:
        inferred 338 D-type flip-flop(s).
        inferred  13 Multiplexer(s).
Unit <uOP_Store> synthesized.


Synthesizing Unit <MEM_Stage>.
    Related source file is "MEM_Stage.v".
WARNING:Xst:647 - Input <RST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:737 - Found 1-bit latch for signal <ret>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
    Found 32-bit tristate buffer for signal <ex_mem_data>.
    Found 6-bit tristate buffer for signal <branch_target>.
    Found 1-bit tristate buffer for signal <mem_Clk>.
    Found 1-bit adder for signal <bc$addsub0000>.
    Found 1-bit adder for signal <bc$addsub0001> created at line 52.
    Found 1-bit adder for signal <bc$addsub0002> created at line 55.
    Found 1-bit xor2 for signal <bc$xor0000> created at line 52.
    Summary:
        inferred   3 Adder/Subtractor(s).
        inferred  39 Tristate(s).
Unit <MEM_Stage> synthesized.


Synthesizing Unit <WB_Stage>.
    Related source file is "WB_Stage.v".
WARNING:Xst:647 - Input <RST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 5-bit tristate buffer for signal <wb_dst>.
    Found 32-bit tristate buffer for signal <wb_data>.
    Summary:
        inferred  37 Tristate(s).
Unit <WB_Stage> synthesized.


Synthesizing Unit <interrupt_unit>.
    Related source file is "interrupt_unit.v".
    Found 5x6-bit dual-port RAM <Mram_isr_vectors> for signal <isr_vectors>.
WARNING:Xst:737 - Found 2-bit latch for signal <vctr_inx>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
    Found 6-bit tristate buffer for signal <vector>.
    Found 4-bit register for signal <masks>.
    Found 1-bit register for signal <temp_unblock>.
    Summary:
        inferred   1 RAM(s).
        inferred   5 D-type flip-flop(s).
        inferred   6 Tristate(s).
Unit <interrupt_unit> synthesized.


Synthesizing Unit <int_ALU>.
    Related source file is "int_ALU.v".
WARNING:Xst:647 - Input <prev_Flag<1:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:737 - Found 32-bit latch for signal <result_buff>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <C>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <S>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <O>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Z>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
    Found 32-bit tristate buffer for signal <Result>.
    Found 32-bit adder carry out for signal <AUX_15$addsub0000> created at line 32.
    Found 32-bit adder carry out for signal <AUX_16$addsub0000> created at line 33.
    Found 1-bit xor4 for signal <O$xor0000> created at line 42.
    Found 32-bit adder for signal <OP1_>.
    Found 32-bit 8-to-1 multiplexer for signal <result_buff$mux0000> created at line 31.
    Found 32-bit xor2 for signal <result_buff$xor0000> created at line 38.
    Summary:
        inferred   5 Adder/Subtractor(s).
        inferred  32 Multiplexer(s).
        inferred   1 Xor(s).
        inferred  32 Tristate(s).
Unit <int_ALU> synthesized.


Synthesizing Unit <Shifter>.
    Related source file is "Shifter.v".
WARNING:Xst:737 - Found 32-bit latch for signal <Result_buff>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
    Found 32-bit tristate buffer for signal <Result>.
    Found 32-bit shifter logical left for signal <Result_buff$shift0002> created at line 19.
    Found 32-bit shifter logical right for signal <Result_buff$shift0003> created at line 20.
    Summary:
        inferred   2 Combinational logic shifter(s).
        inferred  32 Tristate(s).
Unit <Shifter> synthesized.


Synthesizing Unit <EX_Stage>.
    Related source file is "EX_Stage.v".
WARNING:Xst:647 - Input <RST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1780 - Signal <OP3> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
    Found 4-bit tristate buffer for signal <stkFlag>.
    Found 32-bit register for signal <bb_MEM_WB_reg>.
    Found 32-bit tristate buffer for signal <E0>.
    Found 4-bit register for signal <prev_Flag>.
    Summary:
        inferred  36 D-type flip-flop(s).
        inferred  36 Tristate(s).
Unit <EX_Stage> synthesized.


Synthesizing Unit <FluidCore>.
    Related source file is "FluidCore.v".
WARNING:Xst:1780 - Signal <t_IF_ID_reg> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <adm> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Unit <FluidCore> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 1
 5x6-bit dual-port RAM                                 : 1
# Adders/Subtractors                                   : 11
 1-bit adder                                           : 3
 2-bit adder                                           : 1
 32-bit adder                                          : 1
 32-bit adder carry out                                : 2
 33-bit adder                                          : 2
 6-bit adder                                           : 1
 6-bit adder carry out                                 : 1
# Counters                                             : 1
 2-bit updown counter                                  : 1
# Registers                                            : 51
 1-bit register                                        : 3
 10-bit register                                       : 4
 119-bit register                                      : 1
 13-bit register                                       : 26
 16-bit register                                       : 2
 32-bit register                                       : 9
 39-bit register                                       : 1
 4-bit register                                        : 2
 6-bit register                                        : 1
 73-bit register                                       : 1
 9-bit register                                        : 1
# Latches                                              : 10
 1-bit latch                                           : 5
 2-bit latch                                           : 1
 32-bit latch                                          : 4
# Multiplexers                                         : 5
 10-bit 4-to-1 multiplexer                             : 1
 13-bit 26-to-1 multiplexer                            : 1
 32-bit 8-to-1 multiplexer                             : 3
# Logic shifters                                       : 2
 32-bit shifter logical left                           : 1
 32-bit shifter logical right                          : 1
# Tristates                                            : 11
 1-bit tristate buffer                                 : 1
 32-bit tristate buffer                                : 5
 4-bit tristate buffer                                 : 2
 5-bit tristate buffer                                 : 1
 6-bit tristate buffer                                 : 2
# Xors                                                 : 21
 1-bit xor2                                            : 19
 1-bit xor4                                            : 1
 32-bit xor2                                           : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

WARNING:Xst:1710 - FF/Latch <bubble_reg_0> (without init value) has a constant value of 1 in block <Staller_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <bubble_reg_1> (without init value) has a constant value of 1 in block <Staller_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <bubble_reg_2> (without init value) has a constant value of 1 in block <Staller_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <bubble_reg_3> (without init value) has a constant value of 1 in block <Staller_inst>. This FF/Latch will be trimmed during the optimization process.

Synthesizing (advanced) Unit <interrupt_unit>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_isr_vectors> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 5-word x 6-bit                      |          |
    |     clkA           | connected to signal <Clk>           | rise     |
    |     weA            | connected to signal <_cmp_eq0000_0> | low      |
    |     addrA          | connected to signal <intr_inx>      |          |
    |     diA            | connected to signal <new_vector>    |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 5-word x 6-bit                      |          |
    |     addrB          | connected to signal <vctr_inx>      |          |
    |     doB            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <interrupt_unit> synthesized (advanced).
WARNING:Xst:2677 - Node <PCStack_3_5> of sequential type is unconnected in block <IF_Stage>.
WARNING:Xst:2677 - Node <PCStack_3_4> of sequential type is unconnected in block <IF_Stage>.
WARNING:Xst:2677 - Node <PCStack_3_3> of sequential type is unconnected in block <IF_Stage>.
WARNING:Xst:2677 - Node <PCStack_3_2> of sequential type is unconnected in block <IF_Stage>.
WARNING:Xst:2677 - Node <PCStack_3_1> of sequential type is unconnected in block <IF_Stage>.
WARNING:Xst:2677 - Node <PCStack_3_0> of sequential type is unconnected in block <IF_Stage>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 1
 5x6-bit dual-port distributed RAM                     : 1
# Adders/Subtractors                                   : 11
 1-bit adder                                           : 3
 2-bit adder                                           : 1
 32-bit adder                                          : 1
 32-bit adder carry out                                : 2
 33-bit adder                                          : 2
 6-bit adder                                           : 1
 6-bit adder carry out                                 : 1
# Counters                                             : 1
 2-bit updown counter                                  : 1
# Registers                                            : 949
 Flip-Flops                                            : 949
# Latches                                              : 10
 1-bit latch                                           : 5
 2-bit latch                                           : 1
 32-bit latch                                          : 4
# Multiplexers                                         : 70
 1-bit 4-to-1 multiplexer                              : 4
 1-bit 8-to-1 multiplexer                              : 64
 13-bit 26-to-1 multiplexer                            : 1
 32-bit 8-to-1 multiplexer                             : 1
# Logic shifters                                       : 2
 32-bit shifter logical left                           : 1
 32-bit shifter logical right                          : 1
# Xors                                                 : 21
 1-bit xor2                                            : 19
 1-bit xor4                                            : 1
 32-bit xor2                                           : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch <bubble_reg_0> (without init value) has a constant value of 1 in block <Staller>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <bubble_reg_1> (without init value) has a constant value of 1 in block <Staller>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <bubble_reg_2> (without init value) has a constant value of 1 in block <Staller>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <bubble_reg_3> (without init value) has a constant value of 1 in block <Staller>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2042 - Unit FluidCore: 6 internal tristates are replaced by logic (pull-up yes): branch_target<0>, branch_target<1>, branch_target<2>, branch_target<3>, branch_target<4>, branch_target<5>.
WARNING:Xst:2042 - Unit EX_Stage: 36 internal tristates are replaced by logic (pull-up yes): E0<0>, E0<10>, E0<11>, E0<12>, E0<13>, E0<14>, E0<15>, E0<16>, E0<17>, E0<18>, E0<19>, E0<1>, E0<20>, E0<21>, E0<22>, E0<23>, E0<24>, E0<25>, E0<26>, E0<27>, E0<28>, E0<29>, E0<2>, E0<30>, E0<31>, E0<3>, E0<4>, E0<5>, E0<6>, E0<7>, E0<8>, E0<9>, stkFlag<0>, stkFlag<1>, stkFlag<2>, stkFlag<3>.
WARNING:Xst:2042 - Unit interrupt_unit: 6 internal tristates are replaced by logic (pull-up yes): vector<0>, vector<1>, vector<2>, vector<3>, vector<4>, vector<5>.
WARNING:Xst:2042 - Unit WB_Stage: 37 internal tristates are replaced by logic (pull-up yes): wb_data<0>, wb_data<10>, wb_data<11>, wb_data<12>, wb_data<13>, wb_data<14>, wb_data<15>, wb_data<16>, wb_data<17>, wb_data<18>, wb_data<19>, wb_data<1>, wb_data<20>, wb_data<21>, wb_data<22>, wb_data<23>, wb_data<24>, wb_data<25>, wb_data<26>, wb_data<27>, wb_data<28>, wb_data<29>, wb_data<2>, wb_data<30>, wb_data<31>, wb_data<3>, wb_data<4>, wb_data<5>, wb_data<6>, wb_data<7>, wb_data<8>, wb_data<9>, wb_dst<0>, wb_dst<1>, wb_dst<2>, wb_dst<3>, wb_dst<4>.
WARNING:Xst:2042 - Unit IF_Stage: 4 internal tristates are replaced by logic (pull-up yes): stkFlag<0>, stkFlag<1>, stkFlag<2>, stkFlag<3>.
WARNING:Xst:2042 - Unit Shifter: 32 internal tristates are replaced by logic (pull-up yes): Result<0>, Result<10>, Result<11>, Result<12>, Result<13>, Result<14>, Result<15>, Result<16>, Result<17>, Result<18>, Result<19>, Result<1>, Result<20>, Result<21>, Result<22>, Result<23>, Result<24>, Result<25>, Result<26>, Result<27>, Result<28>, Result<29>, Result<2>, Result<30>, Result<31>, Result<3>, Result<4>, Result<5>, Result<6>, Result<7>, Result<8>, Result<9>.
WARNING:Xst:2042 - Unit int_ALU: 32 internal tristates are replaced by logic (pull-up yes): Result<0>, Result<10>, Result<11>, Result<12>, Result<13>, Result<14>, Result<15>, Result<16>, Result<17>, Result<18>, Result<19>, Result<1>, Result<20>, Result<21>, Result<22>, Result<23>, Result<24>, Result<25>, Result<26>, Result<27>, Result<28>, Result<29>, Result<2>, Result<30>, Result<31>, Result<3>, Result<4>, Result<5>, Result<6>, Result<7>, Result<8>, Result<9>.

Optimizing unit <FluidCore> ...

Optimizing unit <Staller> ...

Optimizing unit <P_Reg_1> ...

Optimizing unit <P_Reg_2> ...

Optimizing unit <P_Reg_3> ...

Optimizing unit <P_Reg_4> ...

Optimizing unit <Reg_File> ...

Optimizing unit <uOP_Store> ...

Optimizing unit <WB_Stage> ...

Optimizing unit <ID_Stage> ...

Optimizing unit <interrupt_unit> ...
WARNING:Xst:2677 - Node <MEM_WB_reg/pipeline_register_1> of sequential type is unconnected in block <FluidCore>.
WARNING:Xst:1293 - FF/Latch <uOP_Store_inst/uOP_rom_12_0> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_12_1> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_12_2> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_12_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_12_4> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_12_5> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_12_6> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_12_7> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_12_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_12_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_12_10> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_12_11> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_12_12> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_11_0> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_11_1> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_11_2> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_11_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_11_4> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_11_5> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_11_6> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_11_7> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_11_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_11_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_11_10> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_11_11> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_11_12> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_15_0> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_15_1> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_15_2> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_15_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_15_4> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_15_5> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_15_6> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_15_7> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_15_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_15_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_15_10> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_15_11> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_15_12> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_14_0> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_14_1> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_14_2> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_14_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_14_4> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_14_5> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_14_6> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_14_7> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_14_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_14_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_14_10> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_14_11> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_14_12> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_9_0> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_9_1> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_9_2> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_9_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_9_4> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_9_5> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_9_6> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_9_7> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_9_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_9_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_9_10> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_9_11> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_9_12> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_8_0> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_8_1> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_8_2> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_8_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_8_4> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_8_5> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_8_6> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_8_7> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_8_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_8_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_8_10> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_8_11> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_8_12> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_13_0> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_13_1> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_13_2> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_13_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_13_4> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_13_5> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_13_6> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_13_7> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_13_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_13_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_13_10> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_13_11> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_13_12> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_10_0> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_10_1> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_10_2> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_10_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_10_4> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_10_5> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_10_6> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_10_7> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_10_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_10_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_10_10> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_10_11> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_10_12> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_23_0> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_23_1> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_23_2> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_23_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_23_4> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_23_5> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_23_6> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_23_7> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_23_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_23_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_23_10> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_23_11> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_23_12> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_19_0> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_19_1> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_19_2> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_19_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_19_4> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_19_5> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_19_6> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_19_7> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_19_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_19_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_19_10> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_19_11> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_19_12> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_22_0> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_22_1> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_22_2> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_22_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_22_4> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_22_5> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_22_6> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_22_7> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_22_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_22_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_22_10> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_22_11> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_22_12> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_21_0> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_21_1> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_21_2> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_21_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_21_4> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_21_5> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_21_6> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_21_7> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_21_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_21_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_21_10> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_21_11> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_21_12> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_17_0> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_17_1> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_17_2> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_17_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_17_4> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_17_5> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_17_6> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_17_7> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_17_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_17_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_17_10> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_17_11> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_17_12> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_16_0> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_16_1> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_16_2> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_16_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_16_4> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_16_5> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_16_6> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_16_7> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_16_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_16_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_16_10> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_16_11> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_16_12> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_18_0> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_18_1> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_18_2> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_18_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_18_4> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_18_5> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_18_6> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_18_7> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_18_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_18_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_18_10> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_18_11> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_18_12> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_20_0> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_20_1> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_20_2> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_20_3> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_20_4> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_20_5> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_20_6> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_20_7> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_20_8> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_20_9> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_20_10> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_20_11> has a constant value of 0 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <uOP_Store_inst/uOP_rom_20_12> has a constant value of 1 in block <FluidCore>. This FF/Latch will be trimmed during the optimization process.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block FluidCore, actual ratio is 23.
INFO:Xst:2261 - The FF/Latch <ID_EX_reg/pipeline_register_118> in Unit <FluidCore> is equivalent to the following FF/Latch, which will be removed : <ID_EX_reg/pipeline_register_115_BRB3> 
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <ID_EX_reg/pipeline_register_3_BRB0> is unconnected in block <FluidCore>.

Pipelining and Register Balancing Report ...

Processing Unit <FluidCore> :
        Register(s) EX_MEM_reg/pipeline_register_7 EX_MEM_reg/pipeline_register_8 has(ve) been forward balanced into : MEM_Stage_inst/branch12211_FRB.
        Register(s) EX_MEM_reg/pipeline_register_8 EX_MEM_reg/pipeline_register_7 has(ve) been forward balanced into : MEM_Stage_inst/branch1121_FRB.
        Register(s) MEM_Stage_inst/branch12211_FRB EX_MEM_reg/pipeline_register_6 EX_MEM_reg/pipeline_register_5 has(ve) been forward balanced into : MEM_Stage_inst/bc_cmp_eq00011_FRB.
        Register(s) EX_MEM_reg/pipeline_register_2 has(ve) been backward balanced into : EX_MEM_reg/pipeline_register_2_BRB0 EX_MEM_reg/pipeline_register_2_BRB1 EX_MEM_reg/pipeline_register_2_BRB2.
        Register(s) EX_MEM_reg/pipeline_register_3 has(ve) been backward balanced into : EX_MEM_reg/pipeline_register_3_BRB1 EX_MEM_reg/pipeline_register_3_BRB2 .
        Register(s) ID_EX_reg/pipeline_register_100 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_100_BRB1.
        Register(s) ID_EX_reg/pipeline_register_101 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_101_BRB1.
        Register(s) ID_EX_reg/pipeline_register_102 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_102_BRB1.
        Register(s) ID_EX_reg/pipeline_register_103 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_103_BRB1.
        Register(s) ID_EX_reg/pipeline_register_104 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_104_BRB1 ID_EX_reg/pipeline_register_104_BRB2 ID_EX_reg/pipeline_register_104_BRB3.
        Register(s) ID_EX_reg/pipeline_register_105 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_105_BRB1 ID_EX_reg/pipeline_register_105_BRB2 .
        Register(s) ID_EX_reg/pipeline_register_106 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_106_BRB1 ID_EX_reg/pipeline_register_106_BRB2 .
        Register(s) ID_EX_reg/pipeline_register_107 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_107_BRB1 ID_EX_reg/pipeline_register_107_BRB2.
        Register(s) ID_EX_reg/pipeline_register_108 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_108_BRB1 ID_EX_reg/pipeline_register_108_BRB2.
        Register(s) ID_EX_reg/pipeline_register_109 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_109_BRB1 ID_EX_reg/pipeline_register_109_BRB2.
        Register(s) ID_EX_reg/pipeline_register_110 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_110_BRB2 ID_EX_reg/pipeline_register_110_BRB3.
        Register(s) ID_EX_reg/pipeline_register_111 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_111_BRB0 ID_EX_reg/pipeline_register_111_BRB1 ID_EX_reg/pipeline_register_111_BRB4 ID_EX_reg/pipeline_register_111_BRB5 ID_EX_reg/pipeline_register_111_BRB6 ID_EX_reg/pipeline_register_111_BRB7 ID_EX_reg/pipeline_register_111_BRB8 .
        Register(s) ID_EX_reg/pipeline_register_112 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_112_BRB3.
        Register(s) ID_EX_reg/pipeline_register_113 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_113_BRB0 ID_EX_reg/pipeline_register_113_BRB1 ID_EX_reg/pipeline_register_113_BRB2 ID_EX_reg/pipeline_register_113_BRB4 ID_EX_reg/pipeline_register_113_BRB5 ID_EX_reg/pipeline_register_113_BRB6 ID_EX_reg/pipeline_register_113_BRB7 ID_EX_reg/pipeline_register_113_BRB8 ID_EX_reg/pipeline_register_113_BRB9 ID_EX_reg/pipeline_register_113_BRB10 ID_EX_reg/pipeline_register_113_BRB11.
        Register(s) ID_EX_reg/pipeline_register_114 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_114_BRB0 ID_EX_reg/pipeline_register_114_BRB1 ID_EX_reg/pipeline_register_114_BRB2.
        Register(s) ID_EX_reg/pipeline_register_115 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_115_BRB0 ID_EX_reg/pipeline_register_115_BRB1 ID_EX_reg/pipeline_register_115_BRB2 .
        Register(s) ID_EX_reg/pipeline_register_116 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_116_BRB1 ID_EX_reg/pipeline_register_116_BRB2 .
        Register(s) ID_EX_reg/pipeline_register_117 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_117_BRB0 .
        Register(s) ID_EX_reg/pipeline_register_14 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_14_BRB0 .
        Register(s) ID_EX_reg/pipeline_register_2 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_2_BRB0 ID_EX_reg/pipeline_register_2_BRB1 ID_EX_reg/pipeline_register_2_BRB4 .
        Register(s) ID_EX_reg/pipeline_register_3 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_3_BRB1 ID_EX_reg/pipeline_register_3_BRB2 .
        Register(s) ID_EX_reg/pipeline_register_46 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_46_BRB0 ID_EX_reg/pipeline_register_46_BRB1.
        Register(s) ID_EX_reg/pipeline_register_47 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_47_BRB1.
        Register(s) ID_EX_reg/pipeline_register_48 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_48_BRB1.
        Register(s) ID_EX_reg/pipeline_register_49 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_49_BRB1.
        Register(s) ID_EX_reg/pipeline_register_50 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_50_BRB1.
        Register(s) ID_EX_reg/pipeline_register_51 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_51_BRB1.
        Register(s) ID_EX_reg/pipeline_register_52 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_52_BRB1.
        Register(s) ID_EX_reg/pipeline_register_53 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_53_BRB1.
        Register(s) ID_EX_reg/pipeline_register_54 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_54_BRB1.
        Register(s) ID_EX_reg/pipeline_register_55 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_55_BRB1.
        Register(s) ID_EX_reg/pipeline_register_56 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_56_BRB1.
        Register(s) ID_EX_reg/pipeline_register_57 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_57_BRB1.
        Register(s) ID_EX_reg/pipeline_register_58 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_58_BRB1.
        Register(s) ID_EX_reg/pipeline_register_59 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_59_BRB1.
        Register(s) ID_EX_reg/pipeline_register_60 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_60_BRB1.
        Register(s) ID_EX_reg/pipeline_register_61 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_61_BRB1.
        Register(s) ID_EX_reg/pipeline_register_62 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_62_BRB1.
        Register(s) ID_EX_reg/pipeline_register_63 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_63_BRB1.
        Register(s) ID_EX_reg/pipeline_register_64 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_64_BRB1.
        Register(s) ID_EX_reg/pipeline_register_65 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_65_BRB1.
        Register(s) ID_EX_reg/pipeline_register_66 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_66_BRB1.
        Register(s) ID_EX_reg/pipeline_register_67 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_67_BRB1.
        Register(s) ID_EX_reg/pipeline_register_68 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_68_BRB1.
        Register(s) ID_EX_reg/pipeline_register_69 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_69_BRB1.
        Register(s) ID_EX_reg/pipeline_register_70 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_70_BRB1.
        Register(s) ID_EX_reg/pipeline_register_71 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_71_BRB1.
        Register(s) ID_EX_reg/pipeline_register_72 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_72_BRB1.
        Register(s) ID_EX_reg/pipeline_register_73 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_73_BRB1.
        Register(s) ID_EX_reg/pipeline_register_74 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_74_BRB1.
        Register(s) ID_EX_reg/pipeline_register_75 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_75_BRB1.
        Register(s) ID_EX_reg/pipeline_register_76 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_76_BRB1.
        Register(s) ID_EX_reg/pipeline_register_77 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_77_BRB1.
        Register(s) ID_EX_reg/pipeline_register_78 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_78_BRB0 ID_EX_reg/pipeline_register_78_BRB1.
        Register(s) ID_EX_reg/pipeline_register_79 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_79_BRB1.
        Register(s) ID_EX_reg/pipeline_register_80 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_80_BRB1.
        Register(s) ID_EX_reg/pipeline_register_81 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_81_BRB1.
        Register(s) ID_EX_reg/pipeline_register_82 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_82_BRB1.
        Register(s) ID_EX_reg/pipeline_register_83 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_83_BRB1.
        Register(s) ID_EX_reg/pipeline_register_84 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_84_BRB1.
        Register(s) ID_EX_reg/pipeline_register_85 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_85_BRB1.
        Register(s) ID_EX_reg/pipeline_register_86 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_86_BRB1.
        Register(s) ID_EX_reg/pipeline_register_87 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_87_BRB1.
        Register(s) ID_EX_reg/pipeline_register_88 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_88_BRB1.
        Register(s) ID_EX_reg/pipeline_register_89 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_89_BRB1.
        Register(s) ID_EX_reg/pipeline_register_90 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_90_BRB1.
        Register(s) ID_EX_reg/pipeline_register_91 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_91_BRB1.
        Register(s) ID_EX_reg/pipeline_register_92 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_92_BRB1.
        Register(s) ID_EX_reg/pipeline_register_93 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_93_BRB1.
        Register(s) ID_EX_reg/pipeline_register_94 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_94_BRB1.
        Register(s) ID_EX_reg/pipeline_register_95 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_95_BRB1.
        Register(s) ID_EX_reg/pipeline_register_96 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_96_BRB1.
        Register(s) ID_EX_reg/pipeline_register_97 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_97_BRB1.
        Register(s) ID_EX_reg/pipeline_register_98 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_98_BRB1.
        Register(s) ID_EX_reg/pipeline_register_99 has(ve) been backward balanced into : ID_EX_reg/pipeline_register_99_BRB1.
        Register(s) ID_Stage_inst/buff_op_a_0 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_0_BRB1 ID_Stage_inst/buff_op_a_0_BRB2 ID_Stage_inst/buff_op_a_0_BRB7 ID_Stage_inst/buff_op_a_0_BRB8 ID_Stage_inst/buff_op_a_0_BRB9 ID_Stage_inst/buff_op_a_0_BRB10 ID_Stage_inst/buff_op_a_0_BRB11 ID_Stage_inst/buff_op_a_0_BRB12.
        Register(s) ID_Stage_inst/buff_op_a_1 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_1_BRB1 ID_Stage_inst/buff_op_a_1_BRB2 ID_Stage_inst/buff_op_a_1_BRB7 ID_Stage_inst/buff_op_a_1_BRB8 ID_Stage_inst/buff_op_a_1_BRB9 ID_Stage_inst/buff_op_a_1_BRB10 ID_Stage_inst/buff_op_a_1_BRB11 ID_Stage_inst/buff_op_a_1_BRB12.
        Register(s) ID_Stage_inst/buff_op_a_10 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_10_BRB1 ID_Stage_inst/buff_op_a_10_BRB2 ID_Stage_inst/buff_op_a_10_BRB7 ID_Stage_inst/buff_op_a_10_BRB8 ID_Stage_inst/buff_op_a_10_BRB9 ID_Stage_inst/buff_op_a_10_BRB10 ID_Stage_inst/buff_op_a_10_BRB11 ID_Stage_inst/buff_op_a_10_BRB12.
        Register(s) ID_Stage_inst/buff_op_a_11 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_11_BRB1 ID_Stage_inst/buff_op_a_11_BRB2 ID_Stage_inst/buff_op_a_11_BRB7 ID_Stage_inst/buff_op_a_11_BRB8 ID_Stage_inst/buff_op_a_11_BRB9 ID_Stage_inst/buff_op_a_11_BRB10 ID_Stage_inst/buff_op_a_11_BRB11 ID_Stage_inst/buff_op_a_11_BRB12.
        Register(s) ID_Stage_inst/buff_op_a_12 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_12_BRB1 ID_Stage_inst/buff_op_a_12_BRB2 ID_Stage_inst/buff_op_a_12_BRB7 ID_Stage_inst/buff_op_a_12_BRB8 ID_Stage_inst/buff_op_a_12_BRB9 ID_Stage_inst/buff_op_a_12_BRB10 ID_Stage_inst/buff_op_a_12_BRB11 ID_Stage_inst/buff_op_a_12_BRB12.
        Register(s) ID_Stage_inst/buff_op_a_13 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_13_BRB1 ID_Stage_inst/buff_op_a_13_BRB2 ID_Stage_inst/buff_op_a_13_BRB7 ID_Stage_inst/buff_op_a_13_BRB8 ID_Stage_inst/buff_op_a_13_BRB9 ID_Stage_inst/buff_op_a_13_BRB10 ID_Stage_inst/buff_op_a_13_BRB11 ID_Stage_inst/buff_op_a_13_BRB12.
        Register(s) ID_Stage_inst/buff_op_a_14 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_14_BRB1 ID_Stage_inst/buff_op_a_14_BRB2 ID_Stage_inst/buff_op_a_14_BRB7 ID_Stage_inst/buff_op_a_14_BRB8 ID_Stage_inst/buff_op_a_14_BRB9 ID_Stage_inst/buff_op_a_14_BRB10 ID_Stage_inst/buff_op_a_14_BRB11 ID_Stage_inst/buff_op_a_14_BRB12.
        Register(s) ID_Stage_inst/buff_op_a_15 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_15_BRB1 ID_Stage_inst/buff_op_a_15_BRB2 ID_Stage_inst/buff_op_a_15_BRB7 ID_Stage_inst/buff_op_a_15_BRB8 ID_Stage_inst/buff_op_a_15_BRB9 ID_Stage_inst/buff_op_a_15_BRB10 ID_Stage_inst/buff_op_a_15_BRB11 ID_Stage_inst/buff_op_a_15_BRB12.
        Register(s) ID_Stage_inst/buff_op_a_16 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_16_BRB1 ID_Stage_inst/buff_op_a_16_BRB2 ID_Stage_inst/buff_op_a_16_BRB7 ID_Stage_inst/buff_op_a_16_BRB8 ID_Stage_inst/buff_op_a_16_BRB9 ID_Stage_inst/buff_op_a_16_BRB10 ID_Stage_inst/buff_op_a_16_BRB11 ID_Stage_inst/buff_op_a_16_BRB12.
        Register(s) ID_Stage_inst/buff_op_a_17 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_17_BRB1 ID_Stage_inst/buff_op_a_17_BRB2 ID_Stage_inst/buff_op_a_17_BRB7 ID_Stage_inst/buff_op_a_17_BRB8 ID_Stage_inst/buff_op_a_17_BRB9 ID_Stage_inst/buff_op_a_17_BRB10 ID_Stage_inst/buff_op_a_17_BRB11 ID_Stage_inst/buff_op_a_17_BRB12.
        Register(s) ID_Stage_inst/buff_op_a_18 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_18_BRB1 ID_Stage_inst/buff_op_a_18_BRB2 ID_Stage_inst/buff_op_a_18_BRB7 ID_Stage_inst/buff_op_a_18_BRB8 ID_Stage_inst/buff_op_a_18_BRB9 ID_Stage_inst/buff_op_a_18_BRB10 ID_Stage_inst/buff_op_a_18_BRB11 ID_Stage_inst/buff_op_a_18_BRB12.
        Register(s) ID_Stage_inst/buff_op_a_19 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_19_BRB1 ID_Stage_inst/buff_op_a_19_BRB2 ID_Stage_inst/buff_op_a_19_BRB7 ID_Stage_inst/buff_op_a_19_BRB8 ID_Stage_inst/buff_op_a_19_BRB9 ID_Stage_inst/buff_op_a_19_BRB10 ID_Stage_inst/buff_op_a_19_BRB11 ID_Stage_inst/buff_op_a_19_BRB12.
        Register(s) ID_Stage_inst/buff_op_a_2 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_2_BRB1 ID_Stage_inst/buff_op_a_2_BRB2 ID_Stage_inst/buff_op_a_2_BRB7 ID_Stage_inst/buff_op_a_2_BRB8 ID_Stage_inst/buff_op_a_2_BRB9 ID_Stage_inst/buff_op_a_2_BRB10 ID_Stage_inst/buff_op_a_2_BRB11 ID_Stage_inst/buff_op_a_2_BRB12.
        Register(s) ID_Stage_inst/buff_op_a_20 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_20_BRB1 ID_Stage_inst/buff_op_a_20_BRB2 ID_Stage_inst/buff_op_a_20_BRB7 ID_Stage_inst/buff_op_a_20_BRB8 ID_Stage_inst/buff_op_a_20_BRB9 ID_Stage_inst/buff_op_a_20_BRB10 ID_Stage_inst/buff_op_a_20_BRB11 ID_Stage_inst/buff_op_a_20_BRB12.
        Register(s) ID_Stage_inst/buff_op_a_21 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_21_BRB1 ID_Stage_inst/buff_op_a_21_BRB2 ID_Stage_inst/buff_op_a_21_BRB7 ID_Stage_inst/buff_op_a_21_BRB8 ID_Stage_inst/buff_op_a_21_BRB9 ID_Stage_inst/buff_op_a_21_BRB10 ID_Stage_inst/buff_op_a_21_BRB11 ID_Stage_inst/buff_op_a_21_BRB12.
        Register(s) ID_Stage_inst/buff_op_a_22 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_22_BRB1 ID_Stage_inst/buff_op_a_22_BRB2 ID_Stage_inst/buff_op_a_22_BRB7 ID_Stage_inst/buff_op_a_22_BRB8 ID_Stage_inst/buff_op_a_22_BRB9 ID_Stage_inst/buff_op_a_22_BRB10 ID_Stage_inst/buff_op_a_22_BRB11 ID_Stage_inst/buff_op_a_22_BRB12.
        Register(s) ID_Stage_inst/buff_op_a_23 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_23_BRB1 ID_Stage_inst/buff_op_a_23_BRB2 ID_Stage_inst/buff_op_a_23_BRB7 ID_Stage_inst/buff_op_a_23_BRB8 ID_Stage_inst/buff_op_a_23_BRB9 ID_Stage_inst/buff_op_a_23_BRB10 ID_Stage_inst/buff_op_a_23_BRB11 ID_Stage_inst/buff_op_a_23_BRB12.
        Register(s) ID_Stage_inst/buff_op_a_24 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_24_BRB1 ID_Stage_inst/buff_op_a_24_BRB2 ID_Stage_inst/buff_op_a_24_BRB7 ID_Stage_inst/buff_op_a_24_BRB8 ID_Stage_inst/buff_op_a_24_BRB9 ID_Stage_inst/buff_op_a_24_BRB10 ID_Stage_inst/buff_op_a_24_BRB11 ID_Stage_inst/buff_op_a_24_BRB12.
        Register(s) ID_Stage_inst/buff_op_a_25 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_25_BRB1 ID_Stage_inst/buff_op_a_25_BRB2 ID_Stage_inst/buff_op_a_25_BRB7 ID_Stage_inst/buff_op_a_25_BRB8 ID_Stage_inst/buff_op_a_25_BRB9 ID_Stage_inst/buff_op_a_25_BRB10 ID_Stage_inst/buff_op_a_25_BRB11 ID_Stage_inst/buff_op_a_25_BRB12.
        Register(s) ID_Stage_inst/buff_op_a_26 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_26_BRB1 ID_Stage_inst/buff_op_a_26_BRB2 ID_Stage_inst/buff_op_a_26_BRB7 ID_Stage_inst/buff_op_a_26_BRB8 ID_Stage_inst/buff_op_a_26_BRB9 ID_Stage_inst/buff_op_a_26_BRB10 ID_Stage_inst/buff_op_a_26_BRB11 ID_Stage_inst/buff_op_a_26_BRB12.
        Register(s) ID_Stage_inst/buff_op_a_27 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_27_BRB1 ID_Stage_inst/buff_op_a_27_BRB2 ID_Stage_inst/buff_op_a_27_BRB7 ID_Stage_inst/buff_op_a_27_BRB8 ID_Stage_inst/buff_op_a_27_BRB9 ID_Stage_inst/buff_op_a_27_BRB10 ID_Stage_inst/buff_op_a_27_BRB11 ID_Stage_inst/buff_op_a_27_BRB12.
        Register(s) ID_Stage_inst/buff_op_a_28 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_28_BRB1 ID_Stage_inst/buff_op_a_28_BRB2 ID_Stage_inst/buff_op_a_28_BRB7 ID_Stage_inst/buff_op_a_28_BRB8 ID_Stage_inst/buff_op_a_28_BRB9 ID_Stage_inst/buff_op_a_28_BRB10 ID_Stage_inst/buff_op_a_28_BRB11 ID_Stage_inst/buff_op_a_28_BRB12.
        Register(s) ID_Stage_inst/buff_op_a_29 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_29_BRB1 ID_Stage_inst/buff_op_a_29_BRB2 ID_Stage_inst/buff_op_a_29_BRB7 ID_Stage_inst/buff_op_a_29_BRB8 ID_Stage_inst/buff_op_a_29_BRB9 ID_Stage_inst/buff_op_a_29_BRB10 ID_Stage_inst/buff_op_a_29_BRB11 ID_Stage_inst/buff_op_a_29_BRB12.
        Register(s) ID_Stage_inst/buff_op_a_3 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_3_BRB1 ID_Stage_inst/buff_op_a_3_BRB2 ID_Stage_inst/buff_op_a_3_BRB7 ID_Stage_inst/buff_op_a_3_BRB8 ID_Stage_inst/buff_op_a_3_BRB9 ID_Stage_inst/buff_op_a_3_BRB10 ID_Stage_inst/buff_op_a_3_BRB11 ID_Stage_inst/buff_op_a_3_BRB12.
        Register(s) ID_Stage_inst/buff_op_a_30 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_30_BRB1 ID_Stage_inst/buff_op_a_30_BRB2 ID_Stage_inst/buff_op_a_30_BRB7 ID_Stage_inst/buff_op_a_30_BRB8 ID_Stage_inst/buff_op_a_30_BRB9 ID_Stage_inst/buff_op_a_30_BRB10 ID_Stage_inst/buff_op_a_30_BRB11 ID_Stage_inst/buff_op_a_30_BRB12.
        Register(s) ID_Stage_inst/buff_op_a_31 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_31_BRB2 ID_Stage_inst/buff_op_a_31_BRB4 ID_Stage_inst/buff_op_a_31_BRB5 ID_Stage_inst/buff_op_a_31_BRB6 ID_Stage_inst/buff_op_a_31_BRB7 ID_Stage_inst/buff_op_a_31_BRB8 ID_Stage_inst/buff_op_a_31_BRB9 ID_Stage_inst/buff_op_a_31_BRB10 ID_Stage_inst/buff_op_a_31_BRB11 ID_Stage_inst/buff_op_a_31_BRB12 ID_Stage_inst/buff_op_a_31_BRB13 ID_Stage_inst/buff_op_a_31_BRB14 ID_Stage_inst/buff_op_a_31_BRB15 ID_Stage_inst/buff_op_a_31_BRB16 ID_Stage_inst/buff_op_a_31_BRB18 ID_Stage_inst/buff_op_a_31_BRB19 .
        Register(s) ID_Stage_inst/buff_op_a_4 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_4_BRB1 ID_Stage_inst/buff_op_a_4_BRB2 ID_Stage_inst/buff_op_a_4_BRB7 ID_Stage_inst/buff_op_a_4_BRB8 ID_Stage_inst/buff_op_a_4_BRB9 ID_Stage_inst/buff_op_a_4_BRB10 ID_Stage_inst/buff_op_a_4_BRB11 ID_Stage_inst/buff_op_a_4_BRB12.
        Register(s) ID_Stage_inst/buff_op_a_5 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_5_BRB1 ID_Stage_inst/buff_op_a_5_BRB2 ID_Stage_inst/buff_op_a_5_BRB7 ID_Stage_inst/buff_op_a_5_BRB8 ID_Stage_inst/buff_op_a_5_BRB9 ID_Stage_inst/buff_op_a_5_BRB10 ID_Stage_inst/buff_op_a_5_BRB11 ID_Stage_inst/buff_op_a_5_BRB12.
        Register(s) ID_Stage_inst/buff_op_a_6 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_6_BRB1 ID_Stage_inst/buff_op_a_6_BRB2 ID_Stage_inst/buff_op_a_6_BRB7 ID_Stage_inst/buff_op_a_6_BRB8 ID_Stage_inst/buff_op_a_6_BRB9 ID_Stage_inst/buff_op_a_6_BRB10 ID_Stage_inst/buff_op_a_6_BRB11 ID_Stage_inst/buff_op_a_6_BRB12.
        Register(s) ID_Stage_inst/buff_op_a_7 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_7_BRB1 ID_Stage_inst/buff_op_a_7_BRB2 ID_Stage_inst/buff_op_a_7_BRB7 ID_Stage_inst/buff_op_a_7_BRB8 ID_Stage_inst/buff_op_a_7_BRB9 ID_Stage_inst/buff_op_a_7_BRB10 ID_Stage_inst/buff_op_a_7_BRB11 ID_Stage_inst/buff_op_a_7_BRB12.
        Register(s) ID_Stage_inst/buff_op_a_8 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_8_BRB1 ID_Stage_inst/buff_op_a_8_BRB2 ID_Stage_inst/buff_op_a_8_BRB7 ID_Stage_inst/buff_op_a_8_BRB8 ID_Stage_inst/buff_op_a_8_BRB9 ID_Stage_inst/buff_op_a_8_BRB10 ID_Stage_inst/buff_op_a_8_BRB11 ID_Stage_inst/buff_op_a_8_BRB12.
        Register(s) ID_Stage_inst/buff_op_a_9 has(ve) been backward balanced into : ID_Stage_inst/buff_op_a_9_BRB1 ID_Stage_inst/buff_op_a_9_BRB2 ID_Stage_inst/buff_op_a_9_BRB7 ID_Stage_inst/buff_op_a_9_BRB8 ID_Stage_inst/buff_op_a_9_BRB9 ID_Stage_inst/buff_op_a_9_BRB10 ID_Stage_inst/buff_op_a_9_BRB11 ID_Stage_inst/buff_op_a_9_BRB12.
        Register(s) ID_Stage_inst/buff_op_b_31 has(ve) been backward balanced into : ID_Stage_inst/buff_op_b_31_BRB1 ID_Stage_inst/buff_op_b_31_BRB2 ID_Stage_inst/buff_op_b_31_BRB8 ID_Stage_inst/buff_op_b_31_BRB10 .
        Register(s) Staller_inst/bubble_reg_4 has(ve) been backward balanced into : Staller_inst/bubble_reg_4_BRB0 Staller_inst/bubble_reg_4_BRB1 Staller_inst/bubble_reg_4_BRB2 Staller_inst/bubble_reg_4_BRB3.
        Register(s) Staller_inst/bubble_reg_5 has(ve) been backward balanced into : Staller_inst/bubble_reg_5_BRB1 .
        Register(s) Staller_inst/bubble_reg_6 has(ve) been backward balanced into : Staller_inst/bubble_reg_6_BRB1 .
        Register(s) Staller_inst/bubble_reg_7 has(ve) been backward balanced into : Staller_inst/bubble_reg_7_BRB1 .
        Register(s) Staller_inst/bubble_reg_8 has(ve) been backward balanced into : Staller_inst/bubble_reg_8_BRB1 .
        Register(s) Staller_inst/stall_reg has(ve) been backward balanced into : Staller_inst/stall_reg_BRB0 Staller_inst/stall_reg_BRB1 Staller_inst/stall_reg_BRB2 Staller_inst/stall_reg_BRB5 Staller_inst/stall_reg_BRB6 Staller_inst/stall_reg_BRB7 Staller_inst/stall_reg_BRB8 Staller_inst/stall_reg_BRB9 Staller_inst/stall_reg_BRB10.
Unit <FluidCore> processed.
Replicating register EX_MEM_reg/pipeline_register_37 to handle IOB=TRUE attribute
Replicating register EX_MEM_reg/pipeline_register_38 to handle IOB=TRUE attribute
Replicating register EX_MEM_reg/pipeline_register_39 to handle IOB=TRUE attribute
Replicating register EX_MEM_reg/pipeline_register_40 to handle IOB=TRUE attribute
Replicating register EX_MEM_reg/pipeline_register_69 to handle IOB=TRUE attribute
Replicating register EX_MEM_reg/pipeline_register_70 to handle IOB=TRUE attribute
Replicating register EX_MEM_reg/pipeline_register_71 to handle IOB=TRUE attribute
Replicating register EX_MEM_reg/pipeline_register_72 to handle IOB=TRUE attribute
Replicating register IF_Stage_inst/PC_0 to handle IOB=TRUE attribute
Replicating register IF_Stage_inst/PC_1 to handle IOB=TRUE attribute
Replicating register IF_Stage_inst/PC_2 to handle IOB=TRUE attribute
Replicating register IF_Stage_inst/PC_3 to handle IOB=TRUE attribute
Replicating register IF_Stage_inst/PC_4 to handle IOB=TRUE attribute
Replicating register IF_Stage_inst/PC_5 to handle IOB=TRUE attribute

FlipFlop ID_EX_reg/pipeline_register_118 has been replicated 1 time(s)
FlipFlop IF_ID_reg/pipeline_register_2 has been replicated 1 time(s)
FlipFlop IF_ID_reg/pipeline_register_3 has been replicated 2 time(s)
FlipFlop IF_Stage_inst/PCStackPtr_0 has been replicated 1 time(s)

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 757
 Flip-Flops                                            : 757

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : FluidCore.ngr
Top Level Output File Name         : FluidCore
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : No

Design Statistics
# IOs                              : 66

Cell Usage :
# BELS                             : 2562
#      GND                         : 1
#      INV                         : 11
#      LUT1                        : 79
#      LUT2                        : 91
#      LUT2_D                      : 1
#      LUT2_L                      : 5
#      LUT3                        : 838
#      LUT3_D                      : 1
#      LUT3_L                      : 5
#      LUT4                        : 796
#      LUT4_D                      : 11
#      LUT4_L                      : 7
#      MUXCY                       : 174
#      MUXF5                       : 312
#      MUXF6                       : 54
#      MUXF7                       : 13
#      VCC                         : 1
#      XORCY                       : 162
# FlipFlops/Latches                : 1096
#      FD                          : 44
#      FDE                         : 502
#      FDR                         : 38
#      FDRE                        : 171
#      FDSE                        : 2
#      LD                          : 68
#      LD_1                        : 268
#      LDC                         : 1
#      LDCP                        : 2
# RAMS                             : 6
#      RAM16X1D                    : 6
# Clock Buffers                    : 5
#      BUFG                        : 5
# IO Buffers                       : 66
#      IBUF                        : 22
#      IOBUF                       : 32
#      OBUF                        : 11
#      OBUFT                       : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s500efg320-4 

 Number of Slices:                     1057  out of   4656    22%  
 Number of Slice Flip Flops:           1043  out of   9312    11%  
 Number of 4 input LUTs:               1857  out of   9312    19%  
    Number used as logic:              1845
    Number used as RAMs:                 12
 Number of IOs:                          66
 Number of bonded IOBs:                  66  out of    232    28%  
    IOB Flip Flops:                      53
 Number of GCLKs:                         5  out of     24    20%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
----------------------------------------------------------------------------------------------------------------+---------------------------------------------------------+-------+
Clock Signal                                                                                                    | Clock buffer(FF name)                                   | Load  |
----------------------------------------------------------------------------------------------------------------+---------------------------------------------------------+-------+
MEM_Stage_inst/ret_cmp_eq0000(MEM_Stage_inst/ret_cmp_eq00001:O)                                                 | NONE(*)(MEM_Stage_inst/ret)                             | 1     |
Clk                                                                                                             | IBUF+BUFG                                               | 741   |
EX_Stage_inst/barrel_shifter_inst/Result_buff_not00021(EX_Stage_inst/barrel_shifter_inst/Result_buff_not00021:O)| BUFG(*)(EX_Stage_inst/barrel_shifter_inst/Result_buff_0)| 32    |
EX_Stage_inst/int_ALU_inst/en1(EX_Stage_inst/int_ALU_inst/en1:O)                                                | BUFG(*)(EX_Stage_inst/int_ALU_inst/Z)                   | 36    |
EX_MEM_reg/Clk_RST1(Staller_inst/Clk_RST1:O)                                                                    | BUFG(*)(IF_ID_reg/pipeline_register_0)                  | 290   |
Interrupt<3>                                                                                                    | IBUF+BUFG                                               | 2     |
----------------------------------------------------------------------------------------------------------------+---------------------------------------------------------+-------+
(*) These 4 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
----------------------------------------------------------------------------------+-------------------------------------+-------+
Control Signal                                                                    | Buffer(FF name)                     | Load  |
----------------------------------------------------------------------------------+-------------------------------------+-------+
Interrupt<1>                                                                      | IBUF                                | 1     |
Interrupt<2>                                                                      | IBUF                                | 1     |
MEM_Stage_inst/ret_0_not0000(fw_c_211:O)                                          | NONE(MEM_Stage_inst/ret)            | 1     |
interrupt_unit_inst/vctr_inx_0__or0000(interrupt_unit_inst/vctr_inx_0__or00001:O) | NONE(interrupt_unit_inst/vctr_inx_0)| 1     |
interrupt_unit_inst/vctr_inx_1__or0000(interrupt_unit_inst/vctr_inx_Q_1_or00001:O)| NONE(interrupt_unit_inst/vctr_inx_1)| 1     |
----------------------------------------------------------------------------------+-------------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 7.402ns (Maximum Frequency: 135.099MHz)
   Minimum input arrival time before clock: 8.336ns
   Maximum output required time after clock: 7.270ns
   Maximum combinational path delay: 6.878ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'Clk'
  Clock period: 7.402ns (frequency: 135.099MHz)
  Total number of paths / destination ports: 1285 / 379
-------------------------------------------------------------------------
Delay:               7.402ns (Levels of Logic = 4)
  Source:            interrupt_unit_inst/masks_1 (FF)
  Destination:       IF_Stage_inst/PCStack_1_0 (FF)
  Source Clock:      Clk rising
  Destination Clock: Clk rising

  Data Path: interrupt_unit_inst/masks_1 to IF_Stage_inst/PCStack_1_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              1   0.591   0.455  interrupt_unit_inst/masks_1 (interrupt_unit_inst/masks_1)
     LUT4_D:I2->O          2   0.704   0.482  interrupt_unit_inst/intr4 (interrupt_unit_inst/intr4)
     LUT3:I2->O           17   0.704   1.055  interrupt_unit_inst/intr18 (intr)
     LUT4_D:I3->O          3   0.704   0.566  IF_Stage_inst/PCStack_0_not00012 (N60)
     LUT3:I2->O           10   0.704   0.882  IF_Stage_inst/PCStack_2_not00011 (IF_Stage_inst/PCStack_2_not0001)
     FDE:CE                    0.555          IF_Stage_inst/PCStack_2_9
    ----------------------------------------
    Total                      7.402ns (3.962ns logic, 3.440ns route)
                                       (53.5% logic, 46.5% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'EX_Stage_inst/int_ALU_inst/en1'
  Clock period: 3.624ns (frequency: 275.938MHz)
  Total number of paths / destination ports: 69 / 36
-------------------------------------------------------------------------
Delay:               3.624ns (Levels of Logic = 2)
  Source:            EX_Stage_inst/int_ALU_inst/C (LATCH)
  Destination:       EX_Stage_inst/int_ALU_inst/C (LATCH)
  Source Clock:      EX_Stage_inst/int_ALU_inst/en1 falling
  Destination Clock: EX_Stage_inst/int_ALU_inst/en1 falling

  Data Path: EX_Stage_inst/int_ALU_inst/C to EX_Stage_inst/int_ALU_inst/C
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               5   0.676   0.808  EX_Stage_inst/int_ALU_inst/C (EX_Stage_inst/int_ALU_inst/C)
     LUT4:I0->O            1   0.704   0.424  EX_Stage_inst/int_ALU_inst/C_mux000017 (EX_Stage_inst/int_ALU_inst/C_mux000017)
     LUT4:I3->O            1   0.704   0.000  EX_Stage_inst/int_ALU_inst/C_mux000085 (EX_Stage_inst/int_ALU_inst/C_mux0000)
     LD:D                      0.308          EX_Stage_inst/int_ALU_inst/C
    ----------------------------------------
    Total                      3.624ns (2.392ns logic, 1.232ns route)
                                       (66.0% logic, 34.0% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'EX_MEM_reg/Clk_RST1'
  Clock period: 7.090ns (frequency: 141.044MHz)
  Total number of paths / destination ports: 4974 / 619
-------------------------------------------------------------------------
Delay:               7.090ns (Levels of Logic = 7)
  Source:            IF_ID_reg/pipeline_register_3_2 (FF)
  Destination:       ID_EX_reg/pipeline_register_118 (FF)
  Source Clock:      EX_MEM_reg/Clk_RST1 rising
  Destination Clock: EX_MEM_reg/Clk_RST1 rising

  Data Path: IF_ID_reg/pipeline_register_3_2 to ID_EX_reg/pipeline_register_118
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q            15   0.591   1.052  IF_ID_reg/pipeline_register_3_2 (IF_ID_reg/pipeline_register_3_2)
     LUT3:I2->O            1   0.704   0.000  uOP_Store_inst/Mmux__COND_14_92 (uOP_Store_inst/Mmux__COND_14_92)
     MUXF5:I1->O           1   0.321   0.000  uOP_Store_inst/Mmux__COND_14_8_f5_0 (uOP_Store_inst/Mmux__COND_14_8_f51)
     MUXF6:I1->O           1   0.521   0.000  uOP_Store_inst/Mmux__COND_14_7_f6 (uOP_Store_inst/Mmux__COND_14_7_f6)
     MUXF7:I0->O           5   0.521   0.808  uOP_Store_inst/Mmux__COND_14_5_f7 (uOP_Store_inst/Mmux__COND_14_5_f7)
     LUT4:I0->O            1   0.704   0.000  fw_c_11_F (N2538)
     MUXF5:I0->O           3   0.321   0.535  fw_c_11 (fw_c_1)
     LUT4:I3->O            2   0.704   0.000  Reg_Hist_inst/load_hazard_abs_and00021 (load_hazard_abs<2>)
     FDRE:D                    0.308          ID_EX_reg/pipeline_register_118
    ----------------------------------------
    Total                      7.090ns (4.695ns logic, 2.395ns route)
                                       (66.2% logic, 33.8% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Clk'
  Total number of paths / destination ports: 2109 / 906
-------------------------------------------------------------------------
Offset:              8.336ns (Levels of Logic = 5)
  Source:            Interrupt<1> (PAD)
  Destination:       IF_Stage_inst/PCStack_1_0 (FF)
  Destination Clock: Clk rising

  Data Path: Interrupt<1> to IF_Stage_inst/PCStack_1_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             4   1.218   0.762  Interrupt_1_IBUF (Interrupt_1_IBUF)
     LUT4_D:I0->O          2   0.704   0.482  interrupt_unit_inst/intr4 (interrupt_unit_inst/intr4)
     LUT3:I2->O           17   0.704   1.055  interrupt_unit_inst/intr18 (intr)
     LUT4_D:I3->O          3   0.704   0.566  IF_Stage_inst/PCStack_0_not00012 (N60)
     LUT3:I2->O           10   0.704   0.882  IF_Stage_inst/PCStack_2_not00011 (IF_Stage_inst/PCStack_2_not0001)
     FDE:CE                    0.555          IF_Stage_inst/PCStack_2_9
    ----------------------------------------
    Total                      8.336ns (4.589ns logic, 3.747ns route)
                                       (55.1% logic, 44.9% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'EX_MEM_reg/Clk_RST1'
  Total number of paths / destination ports: 224 / 224
-------------------------------------------------------------------------
Offset:              5.554ns (Levels of Logic = 2)
  Source:            RST (PAD)
  Destination:       EX_MEM_reg/pipeline_register_0 (FF)
  Destination Clock: EX_MEM_reg/Clk_RST1 rising

  Data Path: RST to EX_MEM_reg/pipeline_register_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            44   1.218   1.441  RST_IBUF (RST_IBUF)
     LUT2:I0->O           87   0.704   1.280  EX_MEM_reg/zero1 (EX_MEM_reg/zero)
     FDRE:R                    0.911          EX_MEM_reg/pipeline_register_72
    ----------------------------------------
    Total                      5.554ns (2.833ns logic, 2.721ns route)
                                       (51.0% logic, 49.0% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Interrupt<3>'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              3.237ns (Levels of Logic = 2)
  Source:            Interrupt<2> (PAD)
  Destination:       interrupt_unit_inst/vctr_inx_0 (LATCH)
  Destination Clock: Interrupt<3> falling

  Data Path: Interrupt<2> to interrupt_unit_inst/vctr_inx_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             4   1.218   0.587  Interrupt_2_IBUF (Interrupt_2_IBUF)
     INV:I->O              1   0.704   0.420  interrupt_unit_inst/vctr_inx_mux0000<1>1_INV_0 (interrupt_unit_inst/vctr_inx_mux0000<1>)
     LDCP:D                    0.308          interrupt_unit_inst/vctr_inx_0
    ----------------------------------------
    Total                      3.237ns (2.230ns logic, 1.007ns route)
                                       (68.9% logic, 31.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'EX_MEM_reg/Clk_RST1'
  Total number of paths / destination ports: 104 / 38
-------------------------------------------------------------------------
Offset:              7.270ns (Levels of Logic = 2)
  Source:            EX_MEM_reg/pipeline_register_1 (FF)
  Destination:       exMemoryData<0> (PAD)
  Source Clock:      EX_MEM_reg/Clk_RST1 rising

  Data Path: EX_MEM_reg/pipeline_register_1 to exMemoryData<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q            44   0.591   1.441  EX_MEM_reg/pipeline_register_1 (EX_MEM_reg/pipeline_register_1)
     LUT2:I0->O           32   0.704   1.262  MEM_Stage_inst/mem_wr_inv1 (MEM_Stage_inst/mem_wr_inv)
     IOBUF:T->IO               3.272          exMemoryData_0_IOBUF (exMemoryData<0>)
    ----------------------------------------
    Total                      7.270ns (4.567ns logic, 2.703ns route)
                                       (62.8% logic, 37.2% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk'
  Total number of paths / destination ports: 6 / 6
-------------------------------------------------------------------------
Offset:              4.283ns (Levels of Logic = 1)
  Source:            IF_Stage_inst/PC_0 (FF)
  Destination:       exInstAddr<0> (PAD)
  Source Clock:      Clk rising

  Data Path: IF_Stage_inst/PC_0 to exInstAddr<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             1   0.591   0.420  IF_Stage_inst/PC_0 (IF_Stage_inst/PC_0)
     OBUF:I->O                 3.272          exInstAddr_0_OBUF (exInstAddr<0>)
    ----------------------------------------
    Total                      4.283ns (3.863ns logic, 0.420ns route)
                                       (90.2% logic, 9.8% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               6.878ns (Levels of Logic = 3)
  Source:            Clk (PAD)
  Destination:       exMemoryClk (PAD)

  Data Path: Clk to exMemoryClk
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            39   1.218   1.264  Clk_IBUF (Clk_IBUF1)
     INV:I->O              1   0.704   0.420  MEM_Stage_inst/mem_Clk_not0000<0>1_INV_0 (exMemoryClk_OBUFT)
     OBUFT:I->O                3.272          exMemoryClk_OBUFT (exMemoryClk)
    ----------------------------------------
    Total                      6.878ns (5.194ns logic, 1.684ns route)
                                       (75.5% logic, 24.5% route)

=========================================================================


Total REAL time to Xst completion: 28.00 secs
Total CPU time to Xst completion: 28.11 secs
 
--> 

Total memory usage is 328900 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :  255 (   0 filtered)
Number of infos    :    8 (   0 filtered)