Subversion Repositories fluid_core_2

--------------------------------------------------------------------------------
Release 14.5 Trace  (nt)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

C:\Xilinx\14.5\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 4 -n
3 -fastpaths -xml FluidCore_preroute.twx FluidCore_map.ncd -o
FluidCore_preroute.twr FluidCore.pcf -ucf Test_Bed.ucf -ucf FluidCore.ucf

Design file:              FluidCore_map.ncd
Physical constraint file: FluidCore.pcf
Device,package,speed:     xc3s500e,fg320,-4 (PRODUCTION 1.27 2013-03-26)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3284 - This timing report was generated using estimated delay 
   information.  For accurate numbers, please refer to the post Place and Route 
   timing report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.
INFO:Timing:3390 - This architecture does not support a default System Jitter 
   value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock 
   Uncertainty calculation.
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 
   'Phase Error' calculations, these terms will be zero in the Clock 
   Uncertainty calculation.  Please make appropriate modification to 
   SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase 
   Error.

================================================================================
Timing constraint: TS_Clk = PERIOD TIMEGRP "Clk" 200 MHz HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).

 12461 paths analyzed, 1856 endpoints analyzed, 1143 failing endpoints
 1143 timing errors detected. (1128 setup errors, 15 hold errors, 0 component switching limit errors)
 Minimum period is  10.716ns.
--------------------------------------------------------------------------------

Paths for end point ID_Stage_inst/buff_op_a_7 (SLICE_X52Y40.FXINA), 43 paths
--------------------------------------------------------------------------------
Slack (setup path):     -5.716ns (requirement - (data path - clock path skew + uncertainty))
  Source:               IF_ID_reg/pipeline_register_4 (FF)
  Destination:          ID_Stage_inst/buff_op_a_7 (LATCH)
  Requirement:          5.000ns
  Data Path Delay:      8.744ns (Levels of Logic = 5)(Component delays alone exceeds constraint)
  Clock Path Skew:      -1.972ns (2.137 - 4.109)
  Source Clock:         EX_MEM_reg/Clk_RST rising at 0.000ns
  Destination Clock:    Clk_IBUF rising at 5.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: IF_ID_reg/pipeline_register_4 to ID_Stage_inst/buff_op_a_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X38Y58.XQ      Tcko                  0.592   IF_ID_reg/pipeline_register<4>
                                                       IF_ID_reg/pipeline_register_4
    SLICE_X36Y63.G3      net (fanout=16)    e  0.659   IF_ID_reg/pipeline_register<4>
    SLICE_X36Y63.Y       Tilo                  0.759   ID_EX_reg/pipeline_register_77_BRB1
                                                       ID_Stage_inst/rrr_adm_SW0
    SLICE_X36Y63.F4      net (fanout=1)     e  0.342   ID_Stage_inst/rrr_adm_SW0/O
    SLICE_X36Y63.X       Tilo                  0.759   ID_EX_reg/pipeline_register_77_BRB1
                                                       ID_Stage_inst/rrr_adm
    SLICE_X65Y43.F2      net (fanout=6)     e  2.147   rrr_adm
    SLICE_X65Y43.X       Tilo                  0.704   reg_a<2>
                                                       ID_Stage_inst/RF_a<2>1
    SLICE_X52Y40.F1      net (fanout=128)   e  1.207   reg_a<2>
    SLICE_X52Y40.F5      Tif5                  1.033   ID_Stage_inst/buff_op_a<7>
                                                       Reg_File_inst/mux29_4
                                                       Reg_File_inst/mux29_3_f5
    SLICE_X52Y40.FXINA   net (fanout=1)     e  0.000   Reg_File_inst/mux29_3_f5
    SLICE_X52Y40.CLK     Tfxck                 0.542   ID_Stage_inst/buff_op_a<7>
                                                       Reg_File_inst/mux29_2_f6
                                                       ID_Stage_inst/buff_op_a_7
    -------------------------------------------------  ---------------------------
    Total                                      8.744ns (4.389ns logic, 4.355ns route)
                                                       (50.2% logic, 49.8% route)

--------------------------------------------------------------------------------
Slack (setup path):     -5.716ns (requirement - (data path - clock path skew + uncertainty))
  Source:               IF_ID_reg/pipeline_register_4 (FF)
  Destination:          ID_Stage_inst/buff_op_a_7 (LATCH)
  Requirement:          5.000ns
  Data Path Delay:      8.744ns (Levels of Logic = 5)(Component delays alone exceeds constraint)
  Clock Path Skew:      -1.972ns (2.137 - 4.109)
  Source Clock:         EX_MEM_reg/Clk_RST rising at 0.000ns
  Destination Clock:    Clk_IBUF rising at 5.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: IF_ID_reg/pipeline_register_4 to ID_Stage_inst/buff_op_a_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X38Y58.XQ      Tcko                  0.592   IF_ID_reg/pipeline_register<4>
                                                       IF_ID_reg/pipeline_register_4
    SLICE_X36Y63.G3      net (fanout=16)    e  0.659   IF_ID_reg/pipeline_register<4>
    SLICE_X36Y63.Y       Tilo                  0.759   ID_EX_reg/pipeline_register_77_BRB1
                                                       ID_Stage_inst/rrr_adm_SW0
    SLICE_X36Y63.F4      net (fanout=1)     e  0.342   ID_Stage_inst/rrr_adm_SW0/O
    SLICE_X36Y63.X       Tilo                  0.759   ID_EX_reg/pipeline_register_77_BRB1
                                                       ID_Stage_inst/rrr_adm
    SLICE_X65Y43.F2      net (fanout=6)     e  2.147   rrr_adm
    SLICE_X65Y43.X       Tilo                  0.704   reg_a<2>
                                                       ID_Stage_inst/RF_a<2>1
    SLICE_X52Y40.G1      net (fanout=128)   e  1.207   reg_a<2>
    SLICE_X52Y40.F5      Tif5                  1.033   ID_Stage_inst/buff_op_a<7>
                                                       Reg_File_inst/mux29_5
                                                       Reg_File_inst/mux29_3_f5
    SLICE_X52Y40.FXINA   net (fanout=1)     e  0.000   Reg_File_inst/mux29_3_f5
    SLICE_X52Y40.CLK     Tfxck                 0.542   ID_Stage_inst/buff_op_a<7>
                                                       Reg_File_inst/mux29_2_f6
                                                       ID_Stage_inst/buff_op_a_7
    -------------------------------------------------  ---------------------------
    Total                                      8.744ns (4.389ns logic, 4.355ns route)
                                                       (50.2% logic, 49.8% route)

--------------------------------------------------------------------------------
Slack (setup path):     -5.604ns (requirement - (data path - clock path skew + uncertainty))
  Source:               IF_ID_reg/pipeline_register_2 (FF)
  Destination:          ID_Stage_inst/buff_op_a_7 (LATCH)
  Requirement:          5.000ns
  Data Path Delay:      8.632ns (Levels of Logic = 5)(Component delays alone exceeds constraint)
  Clock Path Skew:      -1.972ns (2.137 - 4.109)
  Source Clock:         EX_MEM_reg/Clk_RST rising at 0.000ns
  Destination Clock:    Clk_IBUF rising at 5.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: IF_ID_reg/pipeline_register_2 to ID_Stage_inst/buff_op_a_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y62.YQ      Tcko                  0.652   IF_ID_reg/pipeline_register<1>
                                                       IF_ID_reg/pipeline_register_2
    SLICE_X36Y63.G1      net (fanout=14)    e  0.487   IF_ID_reg/pipeline_register<2>
    SLICE_X36Y63.Y       Tilo                  0.759   ID_EX_reg/pipeline_register_77_BRB1
                                                       ID_Stage_inst/rrr_adm_SW0
    SLICE_X36Y63.F4      net (fanout=1)     e  0.342   ID_Stage_inst/rrr_adm_SW0/O
    SLICE_X36Y63.X       Tilo                  0.759   ID_EX_reg/pipeline_register_77_BRB1
                                                       ID_Stage_inst/rrr_adm
    SLICE_X65Y43.F2      net (fanout=6)     e  2.147   rrr_adm
    SLICE_X65Y43.X       Tilo                  0.704   reg_a<2>
                                                       ID_Stage_inst/RF_a<2>1
    SLICE_X52Y40.G1      net (fanout=128)   e  1.207   reg_a<2>
    SLICE_X52Y40.F5      Tif5                  1.033   ID_Stage_inst/buff_op_a<7>
                                                       Reg_File_inst/mux29_5
                                                       Reg_File_inst/mux29_3_f5
    SLICE_X52Y40.FXINA   net (fanout=1)     e  0.000   Reg_File_inst/mux29_3_f5
    SLICE_X52Y40.CLK     Tfxck                 0.542   ID_Stage_inst/buff_op_a<7>
                                                       Reg_File_inst/mux29_2_f6
                                                       ID_Stage_inst/buff_op_a_7
    -------------------------------------------------  ---------------------------
    Total                                      8.632ns (4.449ns logic, 4.183ns route)
                                                       (51.5% logic, 48.5% route)

--------------------------------------------------------------------------------

Paths for end point ID_Stage_inst/buff_op_a_7 (SLICE_X52Y40.FXINB), 43 paths
--------------------------------------------------------------------------------
Slack (setup path):     -5.716ns (requirement - (data path - clock path skew + uncertainty))
  Source:               IF_ID_reg/pipeline_register_4 (FF)
  Destination:          ID_Stage_inst/buff_op_a_7 (LATCH)
  Requirement:          5.000ns
  Data Path Delay:      8.744ns (Levels of Logic = 5)(Component delays alone exceeds constraint)
  Clock Path Skew:      -1.972ns (2.137 - 4.109)
  Source Clock:         EX_MEM_reg/Clk_RST rising at 0.000ns
  Destination Clock:    Clk_IBUF rising at 5.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: IF_ID_reg/pipeline_register_4 to ID_Stage_inst/buff_op_a_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X38Y58.XQ      Tcko                  0.592   IF_ID_reg/pipeline_register<4>
                                                       IF_ID_reg/pipeline_register_4
    SLICE_X36Y63.G3      net (fanout=16)    e  0.659   IF_ID_reg/pipeline_register<4>
    SLICE_X36Y63.Y       Tilo                  0.759   ID_EX_reg/pipeline_register_77_BRB1
                                                       ID_Stage_inst/rrr_adm_SW0
    SLICE_X36Y63.F4      net (fanout=1)     e  0.342   ID_Stage_inst/rrr_adm_SW0/O
    SLICE_X36Y63.X       Tilo                  0.759   ID_EX_reg/pipeline_register_77_BRB1
                                                       ID_Stage_inst/rrr_adm
    SLICE_X65Y43.F2      net (fanout=6)     e  2.147   rrr_adm
    SLICE_X65Y43.X       Tilo                  0.704   reg_a<2>
                                                       ID_Stage_inst/RF_a<2>1
    SLICE_X52Y41.F1      net (fanout=128)   e  1.207   reg_a<2>
    SLICE_X52Y41.F5      Tif5                  1.033   Reg_File_inst/mux29_4_f5
                                                       Reg_File_inst/mux29_51
                                                       Reg_File_inst/mux29_4_f5
    SLICE_X52Y40.FXINB   net (fanout=1)     e  0.000   Reg_File_inst/mux29_4_f5
    SLICE_X52Y40.CLK     Tfxck                 0.542   ID_Stage_inst/buff_op_a<7>
                                                       Reg_File_inst/mux29_2_f6
                                                       ID_Stage_inst/buff_op_a_7
    -------------------------------------------------  ---------------------------
    Total                                      8.744ns (4.389ns logic, 4.355ns route)
                                                       (50.2% logic, 49.8% route)

--------------------------------------------------------------------------------
Slack (setup path):     -5.716ns (requirement - (data path - clock path skew + uncertainty))
  Source:               IF_ID_reg/pipeline_register_4 (FF)
  Destination:          ID_Stage_inst/buff_op_a_7 (LATCH)
  Requirement:          5.000ns
  Data Path Delay:      8.744ns (Levels of Logic = 5)(Component delays alone exceeds constraint)
  Clock Path Skew:      -1.972ns (2.137 - 4.109)
  Source Clock:         EX_MEM_reg/Clk_RST rising at 0.000ns
  Destination Clock:    Clk_IBUF rising at 5.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: IF_ID_reg/pipeline_register_4 to ID_Stage_inst/buff_op_a_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X38Y58.XQ      Tcko                  0.592   IF_ID_reg/pipeline_register<4>
                                                       IF_ID_reg/pipeline_register_4
    SLICE_X36Y63.G3      net (fanout=16)    e  0.659   IF_ID_reg/pipeline_register<4>
    SLICE_X36Y63.Y       Tilo                  0.759   ID_EX_reg/pipeline_register_77_BRB1
                                                       ID_Stage_inst/rrr_adm_SW0
    SLICE_X36Y63.F4      net (fanout=1)     e  0.342   ID_Stage_inst/rrr_adm_SW0/O
    SLICE_X36Y63.X       Tilo                  0.759   ID_EX_reg/pipeline_register_77_BRB1
                                                       ID_Stage_inst/rrr_adm
    SLICE_X65Y43.F2      net (fanout=6)     e  2.147   rrr_adm
    SLICE_X65Y43.X       Tilo                  0.704   reg_a<2>
                                                       ID_Stage_inst/RF_a<2>1
    SLICE_X52Y41.G1      net (fanout=128)   e  1.207   reg_a<2>
    SLICE_X52Y41.F5      Tif5                  1.033   Reg_File_inst/mux29_4_f5
                                                       Reg_File_inst/mux29_6
                                                       Reg_File_inst/mux29_4_f5
    SLICE_X52Y40.FXINB   net (fanout=1)     e  0.000   Reg_File_inst/mux29_4_f5
    SLICE_X52Y40.CLK     Tfxck                 0.542   ID_Stage_inst/buff_op_a<7>
                                                       Reg_File_inst/mux29_2_f6
                                                       ID_Stage_inst/buff_op_a_7
    -------------------------------------------------  ---------------------------
    Total                                      8.744ns (4.389ns logic, 4.355ns route)
                                                       (50.2% logic, 49.8% route)

--------------------------------------------------------------------------------
Slack (setup path):     -5.604ns (requirement - (data path - clock path skew + uncertainty))
  Source:               IF_ID_reg/pipeline_register_2 (FF)
  Destination:          ID_Stage_inst/buff_op_a_7 (LATCH)
  Requirement:          5.000ns
  Data Path Delay:      8.632ns (Levels of Logic = 5)(Component delays alone exceeds constraint)
  Clock Path Skew:      -1.972ns (2.137 - 4.109)
  Source Clock:         EX_MEM_reg/Clk_RST rising at 0.000ns
  Destination Clock:    Clk_IBUF rising at 5.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: IF_ID_reg/pipeline_register_2 to ID_Stage_inst/buff_op_a_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y62.YQ      Tcko                  0.652   IF_ID_reg/pipeline_register<1>
                                                       IF_ID_reg/pipeline_register_2
    SLICE_X36Y63.G1      net (fanout=14)    e  0.487   IF_ID_reg/pipeline_register<2>
    SLICE_X36Y63.Y       Tilo                  0.759   ID_EX_reg/pipeline_register_77_BRB1
                                                       ID_Stage_inst/rrr_adm_SW0
    SLICE_X36Y63.F4      net (fanout=1)     e  0.342   ID_Stage_inst/rrr_adm_SW0/O
    SLICE_X36Y63.X       Tilo                  0.759   ID_EX_reg/pipeline_register_77_BRB1
                                                       ID_Stage_inst/rrr_adm
    SLICE_X65Y43.F2      net (fanout=6)     e  2.147   rrr_adm
    SLICE_X65Y43.X       Tilo                  0.704   reg_a<2>
                                                       ID_Stage_inst/RF_a<2>1
    SLICE_X52Y41.G1      net (fanout=128)   e  1.207   reg_a<2>
    SLICE_X52Y41.F5      Tif5                  1.033   Reg_File_inst/mux29_4_f5
                                                       Reg_File_inst/mux29_6
                                                       Reg_File_inst/mux29_4_f5
    SLICE_X52Y40.FXINB   net (fanout=1)     e  0.000   Reg_File_inst/mux29_4_f5
    SLICE_X52Y40.CLK     Tfxck                 0.542   ID_Stage_inst/buff_op_a<7>
                                                       Reg_File_inst/mux29_2_f6
                                                       ID_Stage_inst/buff_op_a_7
    -------------------------------------------------  ---------------------------
    Total                                      8.632ns (4.449ns logic, 4.183ns route)
                                                       (51.5% logic, 48.5% route)

--------------------------------------------------------------------------------

Paths for end point ID_Stage_inst/buff_op_a_18 (SLICE_X64Y52.FXINA), 43 paths
--------------------------------------------------------------------------------
Slack (setup path):     -5.680ns (requirement - (data path - clock path skew + uncertainty))
  Source:               IF_ID_reg/pipeline_register_4 (FF)
  Destination:          ID_Stage_inst/buff_op_a_18 (LATCH)
  Requirement:          5.000ns
  Data Path Delay:      8.708ns (Levels of Logic = 5)(Component delays alone exceeds constraint)
  Clock Path Skew:      -1.972ns (2.137 - 4.109)
  Source Clock:         EX_MEM_reg/Clk_RST rising at 0.000ns
  Destination Clock:    Clk_IBUF rising at 5.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: IF_ID_reg/pipeline_register_4 to ID_Stage_inst/buff_op_a_18
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X38Y58.XQ      Tcko                  0.592   IF_ID_reg/pipeline_register<4>
                                                       IF_ID_reg/pipeline_register_4
    SLICE_X36Y63.G3      net (fanout=16)    e  0.659   IF_ID_reg/pipeline_register<4>
    SLICE_X36Y63.Y       Tilo                  0.759   ID_EX_reg/pipeline_register_77_BRB1
                                                       ID_Stage_inst/rrr_adm_SW0
    SLICE_X36Y63.F4      net (fanout=1)     e  0.342   ID_Stage_inst/rrr_adm_SW0/O
    SLICE_X36Y63.X       Tilo                  0.759   ID_EX_reg/pipeline_register_77_BRB1
                                                       ID_Stage_inst/rrr_adm
    SLICE_X65Y43.F2      net (fanout=6)     e  2.147   rrr_adm
    SLICE_X65Y43.X       Tilo                  0.704   reg_a<2>
                                                       ID_Stage_inst/RF_a<2>1
    SLICE_X64Y52.F1      net (fanout=128)   e  1.171   reg_a<2>
    SLICE_X64Y52.F5      Tif5                  1.033   ID_Stage_inst/buff_op_a<18>
                                                       Reg_File_inst/mux9_4
                                                       Reg_File_inst/mux9_3_f5
    SLICE_X64Y52.FXINA   net (fanout=1)     e  0.000   Reg_File_inst/mux9_3_f5
    SLICE_X64Y52.CLK     Tfxck                 0.542   ID_Stage_inst/buff_op_a<18>
                                                       Reg_File_inst/mux9_2_f6
                                                       ID_Stage_inst/buff_op_a_18
    -------------------------------------------------  ---------------------------
    Total                                      8.708ns (4.389ns logic, 4.319ns route)
                                                       (50.4% logic, 49.6% route)

--------------------------------------------------------------------------------
Slack (setup path):     -5.680ns (requirement - (data path - clock path skew + uncertainty))
  Source:               IF_ID_reg/pipeline_register_4 (FF)
  Destination:          ID_Stage_inst/buff_op_a_18 (LATCH)
  Requirement:          5.000ns
  Data Path Delay:      8.708ns (Levels of Logic = 5)(Component delays alone exceeds constraint)
  Clock Path Skew:      -1.972ns (2.137 - 4.109)
  Source Clock:         EX_MEM_reg/Clk_RST rising at 0.000ns
  Destination Clock:    Clk_IBUF rising at 5.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: IF_ID_reg/pipeline_register_4 to ID_Stage_inst/buff_op_a_18
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X38Y58.XQ      Tcko                  0.592   IF_ID_reg/pipeline_register<4>
                                                       IF_ID_reg/pipeline_register_4
    SLICE_X36Y63.G3      net (fanout=16)    e  0.659   IF_ID_reg/pipeline_register<4>
    SLICE_X36Y63.Y       Tilo                  0.759   ID_EX_reg/pipeline_register_77_BRB1
                                                       ID_Stage_inst/rrr_adm_SW0
    SLICE_X36Y63.F4      net (fanout=1)     e  0.342   ID_Stage_inst/rrr_adm_SW0/O
    SLICE_X36Y63.X       Tilo                  0.759   ID_EX_reg/pipeline_register_77_BRB1
                                                       ID_Stage_inst/rrr_adm
    SLICE_X65Y43.F2      net (fanout=6)     e  2.147   rrr_adm
    SLICE_X65Y43.X       Tilo                  0.704   reg_a<2>
                                                       ID_Stage_inst/RF_a<2>1
    SLICE_X64Y52.G1      net (fanout=128)   e  1.171   reg_a<2>
    SLICE_X64Y52.F5      Tif5                  1.033   ID_Stage_inst/buff_op_a<18>
                                                       Reg_File_inst/mux9_5
                                                       Reg_File_inst/mux9_3_f5
    SLICE_X64Y52.FXINA   net (fanout=1)     e  0.000   Reg_File_inst/mux9_3_f5
    SLICE_X64Y52.CLK     Tfxck                 0.542   ID_Stage_inst/buff_op_a<18>
                                                       Reg_File_inst/mux9_2_f6
                                                       ID_Stage_inst/buff_op_a_18
    -------------------------------------------------  ---------------------------
    Total                                      8.708ns (4.389ns logic, 4.319ns route)
                                                       (50.4% logic, 49.6% route)

--------------------------------------------------------------------------------
Slack (setup path):     -5.568ns (requirement - (data path - clock path skew + uncertainty))
  Source:               IF_ID_reg/pipeline_register_2 (FF)
  Destination:          ID_Stage_inst/buff_op_a_18 (LATCH)
  Requirement:          5.000ns
  Data Path Delay:      8.596ns (Levels of Logic = 5)(Component delays alone exceeds constraint)
  Clock Path Skew:      -1.972ns (2.137 - 4.109)
  Source Clock:         EX_MEM_reg/Clk_RST rising at 0.000ns
  Destination Clock:    Clk_IBUF rising at 5.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: IF_ID_reg/pipeline_register_2 to ID_Stage_inst/buff_op_a_18
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y62.YQ      Tcko                  0.652   IF_ID_reg/pipeline_register<1>
                                                       IF_ID_reg/pipeline_register_2
    SLICE_X36Y63.G1      net (fanout=14)    e  0.487   IF_ID_reg/pipeline_register<2>
    SLICE_X36Y63.Y       Tilo                  0.759   ID_EX_reg/pipeline_register_77_BRB1
                                                       ID_Stage_inst/rrr_adm_SW0
    SLICE_X36Y63.F4      net (fanout=1)     e  0.342   ID_Stage_inst/rrr_adm_SW0/O
    SLICE_X36Y63.X       Tilo                  0.759   ID_EX_reg/pipeline_register_77_BRB1
                                                       ID_Stage_inst/rrr_adm
    SLICE_X65Y43.F2      net (fanout=6)     e  2.147   rrr_adm
    SLICE_X65Y43.X       Tilo                  0.704   reg_a<2>
                                                       ID_Stage_inst/RF_a<2>1
    SLICE_X64Y52.G1      net (fanout=128)   e  1.171   reg_a<2>
    SLICE_X64Y52.F5      Tif5                  1.033   ID_Stage_inst/buff_op_a<18>
                                                       Reg_File_inst/mux9_5
                                                       Reg_File_inst/mux9_3_f5
    SLICE_X64Y52.FXINA   net (fanout=1)     e  0.000   Reg_File_inst/mux9_3_f5
    SLICE_X64Y52.CLK     Tfxck                 0.542   ID_Stage_inst/buff_op_a<18>
                                                       Reg_File_inst/mux9_2_f6
                                                       ID_Stage_inst/buff_op_a_18
    -------------------------------------------------  ---------------------------
    Total                                      8.596ns (4.449ns logic, 4.147ns route)
                                                       (51.8% logic, 48.2% route)

--------------------------------------------------------------------------------

Hold Paths: TS_Clk = PERIOD TIMEGRP "Clk" 200 MHz HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point ID_EX_reg/pipeline_register_69_BRB0 (SLICE_X36Y43.BY), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      -0.566ns (requirement - (clock path skew + uncertainty - data path))
  Source:               ID_Stage_inst/buff_op_b_7 (LATCH)
  Destination:          ID_EX_reg/pipeline_register_69_BRB0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.406ns (Levels of Logic = 0)
  Clock Path Skew:      1.972ns (4.109 - 2.137)
  Source Clock:         Clk_IBUF rising at 5.000ns
  Destination Clock:    EX_MEM_reg/Clk_RST rising at 5.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: ID_Stage_inst/buff_op_b_7 to ID_EX_reg/pipeline_register_69_BRB0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X39Y44.YQ      Tcklo                 0.533   ID_Stage_inst/buff_op_b<7>
                                                       ID_Stage_inst/buff_op_b_7
    SLICE_X36Y43.BY      net (fanout=1)     e  0.721   ID_Stage_inst/buff_op_b<7>
    SLICE_X36Y43.CLK     Tckdi       (-Th)    -0.152   ID_EX_reg/pipeline_register_45_BRB0
                                                       ID_EX_reg/pipeline_register_69_BRB0
    -------------------------------------------------  ---------------------------
    Total                                      1.406ns (0.685ns logic, 0.721ns route)
                                                       (48.7% logic, 51.3% route)

--------------------------------------------------------------------------------

Paths for end point ID_EX_reg/pipeline_register_61_BRB0 (SLICE_X37Y56.BX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      -0.371ns (requirement - (clock path skew + uncertainty - data path))
  Source:               ID_Stage_inst/buff_op_b_15 (LATCH)
  Destination:          ID_EX_reg/pipeline_register_61_BRB0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.601ns (Levels of Logic = 0)
  Clock Path Skew:      1.972ns (4.109 - 2.137)
  Source Clock:         Clk_IBUF rising at 5.000ns
  Destination Clock:    EX_MEM_reg/Clk_RST rising at 5.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: ID_Stage_inst/buff_op_b_15 to ID_EX_reg/pipeline_register_61_BRB0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X43Y58.YQ      Tcklo                 0.533   ID_Stage_inst/buff_op_b<15>
                                                       ID_Stage_inst/buff_op_b_15
    SLICE_X37Y56.BX      net (fanout=1)     e  0.975   ID_Stage_inst/buff_op_b<15>
    SLICE_X37Y56.CLK     Tckdi       (-Th)    -0.093   ID_EX_reg/pipeline_register_61_BRB0
                                                       ID_EX_reg/pipeline_register_61_BRB0
    -------------------------------------------------  ---------------------------
    Total                                      1.601ns (0.626ns logic, 0.975ns route)
                                                       (39.1% logic, 60.9% route)

--------------------------------------------------------------------------------

Paths for end point ID_EX_reg/pipeline_register_53_BRB0 (SLICE_X34Y45.BX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      -0.360ns (requirement - (clock path skew + uncertainty - data path))
  Source:               ID_Stage_inst/buff_op_b_23 (LATCH)
  Destination:          ID_EX_reg/pipeline_register_53_BRB0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.612ns (Levels of Logic = 0)
  Clock Path Skew:      1.972ns (4.109 - 2.137)
  Source Clock:         Clk_IBUF rising at 5.000ns
  Destination Clock:    EX_MEM_reg/Clk_RST rising at 5.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: ID_Stage_inst/buff_op_b_23 to ID_EX_reg/pipeline_register_53_BRB0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X35Y52.YQ      Tcklo                 0.533   ID_Stage_inst/buff_op_b<23>
                                                       ID_Stage_inst/buff_op_b_23
    SLICE_X34Y45.BX      net (fanout=1)     e  0.945   ID_Stage_inst/buff_op_b<23>
    SLICE_X34Y45.CLK     Tckdi       (-Th)    -0.134   ID_EX_reg/pipeline_register_53_BRB0
                                                       ID_EX_reg/pipeline_register_53_BRB0
    -------------------------------------------------  ---------------------------
    Total                                      1.612ns (0.667ns logic, 0.945ns route)
                                                       (41.4% logic, 58.6% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_Clk = PERIOD TIMEGRP "Clk" 200 MHz HIGH 50%;
--------------------------------------------------------------------------------
Slack: 1.808ns (period - (min low pulse limit / (low pulse / period)))
  Period: 5.000ns
  Low pulse: 2.500ns
  Low pulse limit: 1.596ns (Trpw)
  Physical resource: exMemoryAddr<0>/SR
  Logical resource: EX_MEM_reg/pipeline_register_68/SR
  Location pin: V15.SR
  Clock network: EX_MEM_reg/zero
--------------------------------------------------------------------------------
Slack: 1.808ns (period - (min high pulse limit / (high pulse / period)))
  Period: 5.000ns
  High pulse: 2.500ns
  High pulse limit: 1.596ns (Trpw)
  Physical resource: exMemoryAddr<0>/SR
  Logical resource: EX_MEM_reg/pipeline_register_68/SR
  Location pin: V15.SR
  Clock network: EX_MEM_reg/zero
--------------------------------------------------------------------------------
Slack: 1.808ns (period - (min low pulse limit / (low pulse / period)))
  Period: 5.000ns
  Low pulse: 2.500ns
  Low pulse limit: 1.596ns (Trpw)
  Physical resource: exMemoryAddr<1>/SR
  Logical resource: EX_MEM_reg/pipeline_register_69/SR
  Location pin: U15.SR
  Clock network: EX_MEM_reg/zero
--------------------------------------------------------------------------------


1 constraint not met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock Clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
Clk            |   10.716|         |         |         |
RST            |   10.716|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock RST
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
Clk            |    8.165|         |         |         |
RST            |    8.165|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 1143  Score: 2952759  (Setup/Max: 2949354, Hold: 3405)

Constraints cover 12461 paths, 0 nets, and 3911 connections

Design statistics:
   Minimum period:  10.716ns{1}   (Maximum frequency:  93.318MHz)


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Mon Apr 27 19:19:28 2015 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 143 MB